JP7028553B2 - Semiconductor devices and their manufacturing methods - Google Patents

Semiconductor devices and their manufacturing methods Download PDF

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JP7028553B2
JP7028553B2 JP2016228004A JP2016228004A JP7028553B2 JP 7028553 B2 JP7028553 B2 JP 7028553B2 JP 2016228004 A JP2016228004 A JP 2016228004A JP 2016228004 A JP2016228004 A JP 2016228004A JP 7028553 B2 JP7028553 B2 JP 7028553B2
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wiring layer
sealing
electrode
power element
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俊寛 岩崎
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株式会社アムコー・テクノロジー・ジャパン
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Description

本発明は半導体装置及びその製造方法に関するものである。 The present invention relates to a semiconductor device and a method for manufacturing the same.

半導体装置の一種であるパワーモジュールは、負荷への電力の供給を担う主電流（負荷電流）を断続するなど主電流の流れを変調制御する電力用半導体素子を備えるパワー回路と、この電力用半導体素子の動作を制御する制御回路とが、１個の装置に組み込まれた半導体装置である。このパワーモジュールは、例えば、モータ等の動作を制御するインバータ、あるいは無停電電源などに利用が拡大しつつある。以下では「パワーモジュール」を「半導体装置」ということがある。 A power module, which is a type of semiconductor device, is a power circuit equipped with a power semiconductor element that modulates and controls the flow of the main current, such as interrupting the main current (load current) that supplies power to the load, and this power semiconductor. The control circuit that controls the operation of the element is a semiconductor device incorporated in one device. The use of this power module is expanding, for example, for an inverter that controls the operation of a motor or the like, an uninterruptible power supply, or the like. Hereinafter, the "power module" may be referred to as a "semiconductor device".

パワーモジュールのパワー回路は電力回路であり、例えば、スイッチング素子（例えばＩＧＢＴ（Ｉｎｓｕｌａｔｅｄ Ｇａｔｅ Ｂｉｐｏｌａｒ Ｔｒａｎｓｉｓｔｏｒ）、ＭＯＳＦＥＴ（Ｍｅｔａｌ－Ｏｘｉｄｅ－Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｆｉｅｌｄ－Ｅｆｆｅｃｔ Ｔｒａｎｓｉｓｔｏｒ）等）等のパワー素子を含む。パワー素子には、一方の面にソース電極とゲート電極を、また、他方の面にドレイン電極を配置し、ソース電極からドレイン電極に垂直方向に通電する縦型構造のものと、ソース電極とドレイン電極とゲート電極とが同一面に配置され、ソース電極からドレイン電極に水平方向に通電する横型構造のものとがある。 The power circuit of the power module is a power circuit, and includes, for example, a power element such as a switching element (for example, an IGBT (Insulated Gate Bipolar Transistor), a MOSFET (Metal-Oxide-Semiconductor Doctor), etc.). The power element has a vertical structure in which a source electrode and a gate electrode are arranged on one surface and a drain electrode is arranged on the other surface, and electricity is supplied from the source electrode to the drain electrode in the vertical direction. There is a horizontal structure in which the electrode and the gate electrode are arranged on the same surface and the source electrode and the drain electrode are electrically energized in the horizontal direction.

ＭＯＳＦＥＴやＩＧＢＴ等のパワー素子は、ロジック素子やメモリ素子と異なり、１Ａ以上の電流、または１００Ｖ以上の電圧が２電極間に印加され、ゲート端子への数Ｖ程度のＯＮ／ＯＦＦ電圧を印加することにより、大電流、または大電圧出力のＯＮ／ＯＦＦのスイッチング素子として機能する。
一方の制御回路は弱電回路であって、その回路素子には微弱な電流しか流れない。 Unlike logic elements and memory elements, power elements such as MOSFETs and IGBTs have a current of 1 A or more or a voltage of 100 V or more applied between the two electrodes, and an ON / OFF voltage of about several V is applied to the gate terminal. Thereby, it functions as an ON / OFF switching element of a large current or a large voltage output.
One of the control circuits is a weak electric circuit, and only a weak current flows through the circuit element.

特許文献１には、パワー素子部分と制御回路部分とを同一基板上に配置した半導体装置が開示されている。
特許文献１に記載の半導体装置を図１６に示す。
放熱機能とモジュール全体の基板としての機能とを果たす第１の金属基板１上には、第１の絶縁層２が設けられている。パワースィッチング素子群６は、第１の金属基板１上にある第１の絶縁層２の露出面に形成してある金属配線層５ａにより、この第１の絶縁層２の露出面に搭載されている。
第１の絶縁層２の露出面の一部に第２の金属基板３が配置され、第２の金属基板３上には第２の絶縁層４が配置されている。第２の金属基板３は第２の絶縁層４に設けられた基板アース用ホール１２を介して、ボンディングワイヤ２０で金属配線層５に接続されることにより接地電位に保たれた導電層を形成している。第２の絶縁層４の表面にパワースィッチング素子群６を駆動し制御するための駆動制御回路を集積回路化したプリドラィバＩＣ８が配置されている。 Patent Document 1 discloses a semiconductor device in which a power element portion and a control circuit portion are arranged on the same substrate.
The semiconductor device described in Patent Document 1 is shown in FIG.
A first insulating layer 2 is provided on the first metal substrate 1 that functions as a heat dissipation function and a substrate of the entire module. The power switching element group 6 is mounted on the exposed surface of the first insulating layer 2 by the metal wiring layer 5a formed on the exposed surface of the first insulating layer 2 on the first metal substrate 1. There is.
The second metal substrate 3 is arranged on a part of the exposed surface of the first insulating layer 2, and the second insulating layer 4 is arranged on the second metal substrate 3. The second metal substrate 3 is connected to the metal wiring layer 5 by a bonding wire 20 via a substrate grounding hole 12 provided in the second insulating layer 4 to form a conductive layer maintained at the ground potential. is doing. A pre-driver IC 8 in which a drive control circuit for driving and controlling the power switching element group 6 is integrated is arranged on the surface of the second insulating layer 4.

しかしながら、パワー素子部分と制御回路部分とを同一基板上に設ける構造である場合、上記両部分の電磁干渉（ＥＭＩ：Ｅｌｅｃｔｒｏ Ｍａｇｎｅｔｉｃ Ｉｎｔｅｒｆｅｒｅｎｃｅ）を防止するため、上記両部分の配線の間を一定距離以上に保つ必要がある。また、これらの回路を接続するボンディングワイヤの引き回しにより配線長が長くなり、モジュール全体としての損失が大きく、ボンディングワイヤの等価インダクタンスに起因してスイッチング時に発生するサージ電圧が大きくなる等の懸念点が認められていた。過大なサージ電圧は、例えば、パワースィッチング素子やドライブ回路の半導体素子等を損傷させる虞がある。 However, when the structure is such that the power element portion and the control circuit portion are provided on the same substrate, in order to prevent electromagnetic interference (EMI) between the two portions, a certain distance or more is provided between the wirings of the two portions. Need to keep in. In addition, there are concerns that the wiring length becomes long due to the routing of the bonding wire connecting these circuits, the loss of the module as a whole is large, and the surge voltage generated during switching due to the equivalent inductance of the bonding wire increases. It was recognized. An excessive surge voltage may damage, for example, a power switching element, a semiconductor element of a drive circuit, or the like.

特許文献２及び特許文献３には、パワー素子部分と制御回路部分とを垂直方向に配置した半導体装置が開示されている。
特許文献２に記載の半導体装置を図１７に示す。
この半導体装置はＤＣ－ＤＣコンバータであり、スイッチング素子をオン・オフ制御して直流入力電圧を昇圧、降圧、反転、或いは昇降圧して出力電圧を生成するに係るものである。
このＤＣ－ＤＣコンバータは、基板１１、半導体チップ（ハイサイドトランジスタチップ）１３、配線プレート１４、半導体チップ（ローサイドトランジスタチップ）１５、及び制御ＩＣ（制御部）チップである半導体チップ１６が積層されることによって形成される。基板１１は絶縁性セラミックからなり、主面上に金属（例えば、Ｃｕ（銅））からなる板状リード１２ａ乃至１２ｅが設けられる。
半導体チップ１３は、板状リード１２ａの第一主面上に載置される。配線プレート１４は、半導体チップ１３の第一主面上に載置される。半導体チップ１５は、配線プレート１４の第一主面上に載置される。半導体チップ１６は、半導体チップ１５の第一主面上に載置される。このＤＣ－ＤＣコンバータは上記のように複数の半導体チップを積層形成してゲート配線長を短縮化し、ゲート配線インピーダンスを低減している。 Patent Document 2 and Patent Document 3 disclose a semiconductor device in which a power element portion and a control circuit portion are arranged in a vertical direction.
The semiconductor device described in Patent Document 2 is shown in FIG.
This semiconductor device is a DC-DC converter, and relates to a DC-DC converter, which controls a switching element on and off to boost, step down, reverse, or step up and down the DC input voltage to generate an output voltage.
In this DC-DC converter, a substrate 11, a semiconductor chip (high-side transistor chip) 13, a wiring plate 14, a semiconductor chip (low-side transistor chip) 15, and a semiconductor chip 16 which is a control IC (control unit) chip are laminated. Formed by The substrate 11 is made of an insulating ceramic, and plate-shaped leads 12a to 12e made of a metal (for example, Cu (copper)) are provided on the main surface.
The semiconductor chip 13 is placed on the first main surface of the plate-shaped lead 12a. The wiring plate 14 is placed on the first main surface of the semiconductor chip 13. The semiconductor chip 15 is placed on the first main surface of the wiring plate 14. The semiconductor chip 16 is placed on the first main surface of the semiconductor chip 15. In this DC-DC converter, as described above, a plurality of semiconductor chips are laminated and formed to shorten the gate wiring length and reduce the gate wiring impedance.

特許文献３に記載の半導体装置を図１８に示す。
この半導体装置は、第１電子回路基板２０上にパワー素子２１を搭載したパワー素子部分と、第２電子回路基板１０上に回路素子１２を搭載した制御回路部分とが垂直方向に積層されている。第２電子回路基板１０は、誘電体層からなる基材１４と、基材１４の開口部分に埋設された内層電極１５と、基板の第１電子回路側の表面である第１表面に形成された第１表面電極１６と、を含んでなる。第１表面電極１６は、基材１４の内部に埋設され、第２電子回路基板１０と第１電子回路基板２０との積層時にパワー素子２１の端子に対向する面が第１表面において露出している。第１電子回路基板２０のパワー素子２１が配設されている表面とは反対側の表面には、パワー素子２１から発生する熱を放出するための放熱手段として、ヒートシンク２２が設けられている。更に、ヒートシンク２２及び第２電子回路基板１０の外縁部には、ヒートシンク２２と第２電子回路基板１０とを接続するケース３０が設けられている。なお、内層電極１５が埋設された誘電体層と同一の誘電体層にはダミー内層電極１７が埋設されており、これにより、回路基板の主面に平行な平面内において同時焼成時における収縮挙動のバラツキが小さくなり、同時焼成時に発生し得る当該回路基板の変形、平面性の悪化等の問題が低減される。 The semiconductor device described in Patent Document 3 is shown in FIG.
In this semiconductor device, a power element portion in which a power element 21 is mounted on a first electronic circuit board 20 and a control circuit portion in which a circuit element 12 is mounted on a second electronic circuit board 10 are vertically laminated. .. The second electronic circuit board 10 is formed on a base material 14 made of a dielectric layer, an inner layer electrode 15 embedded in an opening portion of the base material 14, and a first surface which is a surface of the substrate on the first electronic circuit side. The first surface electrode 16 and the like are included. The first surface electrode 16 is embedded inside the base material 14, and the surface facing the terminal of the power element 21 is exposed on the first surface when the second electronic circuit board 10 and the first electronic circuit board 20 are laminated. There is. A heat sink 22 is provided on the surface of the first electronic circuit board 20 opposite to the surface on which the power element 21 is arranged as a heat radiating means for releasing heat generated from the power element 21. Further, a case 30 for connecting the heat sink 22 and the second electronic circuit board 10 is provided on the outer edge portion of the heat sink 22 and the second electronic circuit board 10. A dummy inner layer electrode 17 is embedded in the same dielectric layer as the dielectric layer in which the inner layer electrode 15 is embedded, whereby the shrinkage behavior at the time of simultaneous firing in a plane parallel to the main surface of the circuit board. The variation is reduced, and problems such as deformation of the circuit board and deterioration of flatness that may occur during simultaneous firing are reduced.

特許第３４６６３２９号公報Japanese Patent No. 3466329 特開２０１２－１９６１１１号公報Japanese Unexamined Patent Publication No. 2012-196111 特開２０１４－５３５７５号公報Japanese Unexamined Patent Publication No. 2014-53575

パワー素子と制御ＩＣを上下に積層し、ボンディングワイヤでの接続の代わりにパネル技術を用いて、パワー素子と制御ＩＣとをビア及び配線で接続することにより、配線経路長が短縮でき、低オン抵抗、低インピーダンス、パッケージの低背化が可能となる。
しかしながら、パワー素子と制御ＩＣを上下に積層する場合には、平面状に配置する場合に比べるとパワー素子と制御ＩＣとがより近接するため、制御ＩＣが大電圧に耐えられるような構造とすることが課題となる。
本発明は、少なくとも１つのパワー素子を備えたパワー回路部を含んだ半導体装置において、絶縁信頼性を向上させると共に薄型化、小型化を可能にした半導体装置を提供することを目的とする。 By stacking the power element and the control IC on the top and bottom and connecting the power element and the control IC with vias and wiring using panel technology instead of connecting with the bonding wire, the wiring path length can be shortened and the wiring path length can be shortened. It enables resistance, low impedance, and low package height.
However, when the power element and the control IC are stacked one above the other, the power element and the control IC are closer to each other than when they are arranged in a plane, so that the control IC has a structure that can withstand a large voltage. Is an issue.
An object of the present invention is to provide a semiconductor device including a power circuit unit including at least one power element, which can improve insulation reliability and can be made thinner and smaller.

本発明は以下に記載する通りの半導体装置及び半導体装置の製造方法に係るものである。
（１）少なくとも１つのパワー素子を備えたパワー回路部を含んだ半導体装置であって、
前記パワー素子は、主面に大電流通電用又は大電圧印加用の第１の電極と小電圧印加用の第２の電極とを有し、
前記パワー素子と、該パワー素子及びその周辺を封止する封止材とを含む第１の封止体と、
前記第１の封止体上に設けた第１の配線層と、該第１の配線層を封止する封止材とを含む、前記第１の封止体上に設けた第２の封止体と、
前記パワー素子の裏面側の前記第１の封止体側に設けた第２の配線層と、該第２の配線層を封止する封止材とを含む第３の封止体と、を含み、
前記第１の配線層は、前記パワー素子の前記第１の電極に金属ビアにより電気的に接続している第１の配線ａと、前記パワー素子の前記第２の電極と金属ビアにより電気的に接続している第１の配線ｂとを有する、半導体装置。
（２）少なくとも１つのパワー素子を備えたパワー回路部と、少なくとも１つの制御素子を備えた制御回路部とを含んだ半導体装置であって、
前記パワー素子は、主面に大電流通電用又は大電圧印加用の第１の電極と小電圧印加用の第２の電極を有し、
前記制御素子は主面に第４の電極を有し、
前記パワー素子と、該パワー素子及びその周辺を封止する封止材とを含む第１の封止体と、
前記第１の封止体上に設けた第１の配線層と、該第１の配線層を封止する封止材とを含む、前記第１の封止体上に設けた第２の封止体と、
前記第２の封止体上に配置された前記制御素子と、該制御素子及びその周辺を封止する封止材とを含む第４の封止体と、
前記第４の封止体上に設けた第３の配線層と、該第３の配線層を封止する封止材とを含む、前記第４の封止体上に設けた第５の封止体と、を含み、
前記第１の配線層は、前記パワー素子の前記第１の電極に金属ビアにより電気的に接続している第１の配線ａと、前記パワー素子の第２の電極に金属ビアにより電気的に接続している第１の配線ｂとを有し、
前記第３の配線層は前記制御素子の前記第４の電極と金属ビアにより電気的に接続されており、
前記第３の配線層と前記第１の配線ｂとは前記第４の封止体に設けた金属ビアを介して電気的に接続されている、半導体装置。
（３）前記第２の封止体の封止材がフィラーを含む、上記（１）又は（２）に記載の半導体装置。
（４）前記第２の封止体の封止材中のフィラーの含有量が７０質量％以上である、上記（３）に記載の半導体装置。
（５）前記フィラーの最大粒径が前記第２の封止体の厚さの２／３以下である、上記（３）又は（４）に記載の半導体装置。
（６）前記第２の封止体の厚みは２０μｍ以上であり、かつ前記第２の封止体の封止材の絶縁抵抗率が１０１１Ω・ｃｍである、上記（１）～（５）のいずれか１項に記載の半導体装置。
（７）前記第２の封止体内に前記第１の配線層が多層に形成されており、前記第１の配線ａ及び前記第１の配線ｂの両方の配線の一部又は一方の配線の一部が異なる配線層に設けられている、上記（１）～（６）のいずれか１項に記載の半導体装置。
（８）前記パワー素子が裏面に第３の電極を有し、該第３の電極と前記第２の配線層との間に導電材を設けた、上記（１）～（７）のいずれか１項に記載の半導体装置。
（９）前記導電材は複数の金属ビアである、上記（８）に記載の半導体装置。
（１０）前記金属ビアの周りに前記第１の封止体の封止材の樹脂とは異なる樹脂を設けた、上記（９）に記載の半導体装置。
（１１）前記パワー素子はＭＯＳＦＥＴであり、前記第１の電極がソース電極であり、前記第２の電極がゲート電極であり、前記第３の電極がドレイン電極である、上記（８）～（１０）のいずれか１項に記載の半導体装置。
（１２）前記制御素子は、前記パワー回路部上にワイヤボンディングにより前記第１の配線ｂと電気的に接続され、封止材によって封止されている、上記（２）に記載の半導体装置。
（１３）前記制御素子は、前記パワー回路部上にフリップチップボンディングにより前記第１の配線ｂと電気的に接続され、アンダーフィル封止された、上記（２）に記載の半導体装置。
（１４）前記第２の封止体における封止材が補強繊維を含まない封止材である、上記（１）又は（２）に記載の半導体装置。
（１５）前記封止材は補強繊維を含まない封止材であり、
前記第１の封止体とは反対側の封止体の主面側に、封止体の反りを相殺して、半導体装置の反りを低減する反り調整層を備えている、上記（１）又は（２）に記載の半導体装置。
（１６）上記（１）に記載の半導体装置の製造方法であって、
支持体の表面に少なくとも一つのパワー素子を搭載する工程と、
前記パワー素子を封止材によって封止して第１の封止体を得る工程と、
前記第１の封止体の表面から、パワー素子の電極に達する金属ビア用の開口を形成する工程と、
前記第１の封止体上に第１の配線層を形成すると共に金属ビアを形成する工程と、
前記第１の配線層を封止材によって封止して第２の封止体を得る工程と、
前記支持体を除去する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線層を形成する工程と、
前記第２の配線層を封止材によって封止して第３の封止体を得る工程と、
を含む、半導体装置の製造方法。
支持体の表面に少なくとも一つのパワー素子を搭載する工程と、
前記パワー素子を封止材によって封止して第１の封止体を得る工程と、
前記第１の封止体の表面から、パワー素子の電極に達する金属ビア用の開口を形成する工程と、
前記第１の封止体上に第１の配線層を形成すると共に金属ビアを形成する工程と、
前記第１の配線層を封止材によって封止して第２の封止体を得る工程と、
前記支持体を除去する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線層を形成する工程と、
前記第２の配線層を封止材によって封止して第３の封止体を得る工程と、
を含む、半導体装置の製造方法。
（１７）上記（２）に記載の半導体装置の製造方法であって、
支持体の表面に少なくとも一つのパワー素子を搭載する工程と、
前記パワー素子を封止材によって封止して第１の封止体を得る工程と、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程と、
前記第１の封止体上に第１の配線を形成すると共に金属ビアを形成する工程と、
前記第１の配線層を封止材によって封止して第２の封止体を得る工程と、
前記第２の封止体上に制御素子を搭載する工程と、
前記制御素子を封止材によって封止して第４の封止体を得る工程と、
前記第４の封止体の表面から、前記制御素子の電極に達する金属ビア用の開口と、前記第１の配線層に達する金属ビア用の開口とを形成する工程と
前記第４の封止体上に第３の配線を形成すると共に金属ビアを形成する工程と、
前記第３の配線を封止材によって封止して第５の封止体を得る工程と、
前記支持体を除去する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線層を形成する工程と、
第２の配線層を封止材によって封止して第３の封止体を得る工程と、
を含む半導体装置の製造方法。
（１８）前記支持体の表面にパワー素子を搭載する工程の前に、前記支持体の表面に第６の封止体を形成する工程を有する、上記（１６）又は（１７）に記載の半導体装置の製造方法。
（１９）前記支持体の表面にパワー素子を搭載する工程の前に、前記支持体の表面に金属配線層を形成する工程を含み、
前記パワー素子を封止材によって封止して第１の封止体を得る工程が、前記パワー素子と金属配線層とを封止材によって封止して第１の封止体を得る工程であり、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程が、前記パワー素子の電極に達する金属ビア用の開口を形成すると共に、金属薄膜配線層に達する金属ビア用の開口を形成する工程であり、
前記第１の封止体上に第１の配線を形成すると共に金属ビアを形成する工程が、第１の配線を形成すると共に前記パワー素子の電極に達する金属ビア及び金属薄膜配線層に達する金属ビアを形成する工程である、
上記（１６）～（１８）のいずれか１項に記載の半導体装置の製造方法。
（２０）予め前記支持体の表面に応力緩和層を形成する工程を含む、上記（１６）又は（１７）に記載の半導体装置の製造方法。
（２１）前記支持体を除去する際に前記応力緩和層を同時に除去する、上記（２０）に記載の半導体装置の製造方法。
（２２）前記パワー素子が裏面に第３の電極を有しており、
前記支持体を除去した後に、
前記パワー素子の前記第３の電極に達する金属ビア用の開口を形成する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線を形成すると共に金属ビアを形成する工程と
を含む上記（１６）又は（１７）に記載の半導体装置の製造方法。
（２３）前記支持体の表面にパワー素子を搭載する工程が、支持体上に形成した金属配線層上に導電材を用いてパワー素子を搭載する工程である、上記（１９）に記載の半導体装置の製造方法。
（２４）上記（１）又は（２）に記載の半導体装置の製造方法であって、
支持体の表面にパワー素子を搭載する工程と、
前記パワー素子を補強繊維を含まない封止材によって封止して第１の封止体を得る工程と、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程と、
前記第１の封止体上に第１の配線を形成すると共に金属ビアを形成する工程と、
前記第１の配線を封止材によって封止して第２の封止体を得る工程と
前記第２の封止体上に反り調整層を形成する工程と、
前記支持体を除去する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線層を形成する工程と、
前記第２の配線層を封止材によって封止して第３の封止体を得る工程と
を含む半導体装置の製造方法。
（２５）前記支持体の表面にパワー素子を搭載する工程の前に、前記支持体の表面に金属配線層を形成する工程を含み、
前記第１の封止体を得る工程が、前記パワー素子と前記金属配線層とを補強繊維を含まない封止材によって封止して第１の封止体を得る工程であり、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程が、前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成すると共に、前記金属配線層に達する金属ビア用の開口を形成する工程であり、
前記第１の封止体上に第１の配線を形成すると共に金属ビアを形成する工程が、第１の配線を形成すると共にパワー素子の電極に達する金属ビア及び金属配線層に達する金属ビアを形成する工程である、
上記（２４）に記載の半導体装置の製造方法。
（２６）前記支持体の表面に予め応力緩和層を形成する工程を含む、上記（２４）又は（２５）に記載の半導体装置の製造方法。 The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device as described below.
(1) A semiconductor device including a power circuit unit including at least one power element.
The power element has a first electrode for energizing a large current or applying a large voltage and a second electrode for applying a small voltage on the main surface.
A first sealing body including the power element and a sealing material for sealing the power element and its surroundings, and
A second seal provided on the first sealant, comprising a first wiring layer provided on the first sealant and a sealant for sealing the first wiring layer. With a still body,
A second wiring layer provided on the first sealing body side on the back surface side of the power element, and a third sealing body including a sealing material for sealing the second wiring layer are included. ,
The first wiring layer is electrically connected to the first electrode of the power element by a first wiring a electrically connected to the first electrode of the power element by a metal via, and by the second electrode of the power element and the metal via. A semiconductor device having a first wire b connected to the device.
(2) A semiconductor device including a power circuit unit including at least one power element and a control circuit unit including at least one control element.
The power element has a first electrode for energizing a large current or applying a large voltage and a second electrode for applying a small voltage on the main surface.
The control element has a fourth electrode on the main surface and has a fourth electrode.
A first sealing body including the power element and a sealing material for sealing the power element and its surroundings, and
A second seal provided on the first sealant, comprising a first wiring layer provided on the first sealant and a sealant for sealing the first wiring layer. With a still body,
A fourth sealing body including the control element arranged on the second sealing body and a sealing material for sealing the control element and its surroundings.
A fifth seal provided on the fourth sealant, including a third wiring layer provided on the fourth sealant and a sealant for sealing the third wiring layer. Including the stationary body,
The first wiring layer has a first wiring a electrically connected to the first electrode of the power element by a metal via and a metal via electrically connected to the second electrode of the power element. It has a first wiring b that is connected, and has
The third wiring layer is electrically connected to the fourth electrode of the control element by a metal via.
A semiconductor device in which the third wiring layer and the first wiring b are electrically connected via a metal via provided in the fourth sealing body.
(3) The semiconductor device according to (1) or (2) above, wherein the sealing material of the second sealing body contains a filler.
(4) The semiconductor device according to (3) above, wherein the content of the filler in the sealing material of the second sealing body is 70% by mass or more.
(5) The semiconductor device according to (3) or (4) above, wherein the maximum particle size of the filler is 2/3 or less of the thickness of the second encapsulant.
(6) The thickness of the second encapsulant is 20 μm or more, and the insulation resistivity of the encapsulant of the second encapsulant is 10 11 Ω · cm. ). The semiconductor device according to any one of the following items.
(7) The first wiring layer is formed in multiple layers in the second sealing body, and a part or one of the wirings of both the first wiring a and the first wiring b is formed. The semiconductor device according to any one of (1) to (6) above, which is partially provided in a different wiring layer.
(8) Any of the above (1) to (7), wherein the power element has a third electrode on the back surface, and a conductive material is provided between the third electrode and the second wiring layer. The semiconductor device according to item 1.
(9) The semiconductor device according to (8) above, wherein the conductive material is a plurality of metal vias.
(10) The semiconductor device according to (9) above, wherein a resin different from the resin of the sealing material of the first sealing body is provided around the metal via.
(11) The power element is a MOSFET, the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode. The semiconductor device according to any one of 10).
(12) The semiconductor device according to (2) above, wherein the control element is electrically connected to the first wiring b on the power circuit unit by wire bonding and is sealed by a sealing material.
(13) The semiconductor device according to (2) above, wherein the control element is electrically connected to the first wiring b on the power circuit unit by flip-chip bonding and is underfill-sealed.
(14) The semiconductor device according to (1) or (2) above, wherein the sealing material in the second sealing body is a sealing material that does not contain reinforcing fibers.
(15) The sealing material is a sealing material that does not contain reinforcing fibers.
The warp adjusting layer for canceling the warp of the encapsulant and reducing the warp of the semiconductor device is provided on the main surface side of the encapsulant on the side opposite to the first encapsulant (1). Or the semiconductor device according to (2).
(16) The method for manufacturing a semiconductor device according to (1) above.
The process of mounting at least one power element on the surface of the support,
The step of sealing the power element with a sealing material to obtain a first sealing body, and
A step of forming an opening for a metal via that reaches the electrode of the power element from the surface of the first encapsulant.
The step of forming the first wiring layer and forming the metal via on the first sealing body, and
The step of sealing the first wiring layer with a sealing material to obtain a second sealing body, and
The step of removing the support and
A step of forming a second wiring layer on the back surface side of the sealed body that was in contact with the support, and
The step of sealing the second wiring layer with a sealing material to obtain a third sealing body, and
A method for manufacturing a semiconductor device, including.
The process of mounting at least one power element on the surface of the support,
The step of sealing the power element with a sealing material to obtain a first sealing body, and
A step of forming an opening for a metal via that reaches the electrode of the power element from the surface of the first encapsulant.
The step of forming the first wiring layer and forming the metal via on the first sealing body, and
The step of sealing the first wiring layer with a sealing material to obtain a second sealing body, and
The step of removing the support and
A step of forming a second wiring layer on the back surface side of the sealed body that was in contact with the support, and
The step of sealing the second wiring layer with a sealing material to obtain a third sealing body, and
A method for manufacturing a semiconductor device, including.
(17) The method for manufacturing a semiconductor device according to (2) above.
The process of mounting at least one power element on the surface of the support,
The step of sealing the power element with a sealing material to obtain a first sealing body, and
A step of forming an opening for a metal via from the surface of the first sealing body to reach the electrode of the power element, and
The step of forming the first wiring and forming the metal via on the first sealing body, and
The step of sealing the first wiring layer with a sealing material to obtain a second sealing body, and
The process of mounting the control element on the second sealing body and
The step of sealing the control element with a sealing material to obtain a fourth sealing body, and
A step of forming an opening for a metal via that reaches the electrode of the control element and an opening for a metal via that reaches the first wiring layer from the surface of the fourth sealing body, and the fourth sealing. The process of forming a third wire on the body and forming a metal via,
The step of sealing the third wiring with a sealing material to obtain a fifth sealing body, and
The step of removing the support and
A step of forming a second wiring layer on the back surface side of the sealed body that was in contact with the support, and
The process of sealing the second wiring layer with a sealing material to obtain a third sealing body, and
A method for manufacturing a semiconductor device including.
(18) The semiconductor according to (16) or (17) above, which has a step of forming a sixth encapsulant on the surface of the support before the step of mounting the power element on the surface of the support. How to manufacture the device.
(19) A step of forming a metal wiring layer on the surface of the support is included before the step of mounting the power element on the surface of the support.
The step of sealing the power element with a sealing material to obtain a first sealing body is a step of sealing the power element and the metal wiring layer with a sealing material to obtain a first sealing body. can be,
The step of forming an opening for a metal via that reaches the electrode of the power element from the surface of the first sealing body forms an opening for the metal via that reaches the electrode of the power element, and also forms a metal thin film wiring layer. Is the process of forming openings for metal vias that reach
The step of forming the first wiring and forming the metal via on the first sealing body forms the first wiring and the metal via that reaches the electrode of the power element and the metal that reaches the metal thin film wiring layer. The process of forming vias,
The method for manufacturing a semiconductor device according to any one of (16) to (18) above.
(20) The method for manufacturing a semiconductor device according to (16) or (17) above, which comprises a step of forming a stress relaxation layer on the surface of the support in advance.
(21) The method for manufacturing a semiconductor device according to (20) above, wherein the stress relaxation layer is simultaneously removed when the support is removed.
(22) The power element has a third electrode on the back surface, and the power element has a third electrode.
After removing the support
A step of forming an opening for a metal via that reaches the third electrode of the power element, and
The method for manufacturing a semiconductor device according to (16) or (17) above, which comprises a step of forming a second wiring and forming a metal via on the back surface side of the sealed body that has been in contact with the support.
(23) The semiconductor according to (19) above, wherein the step of mounting the power element on the surface of the support is a step of mounting the power element on the metal wiring layer formed on the support by using a conductive material. How to manufacture the device.
(24) The method for manufacturing a semiconductor device according to (1) or (2) above.
The process of mounting a power element on the surface of the support,
The step of sealing the power element with a sealing material containing no reinforcing fiber to obtain a first sealed body, and
A step of forming an opening for a metal via from the surface of the first sealing body to reach the electrode of the power element, and
The step of forming the first wiring and forming the metal via on the first sealing body, and
A step of sealing the first wiring with a sealing material to obtain a second sealed body, and a step of forming a warp adjusting layer on the second sealed body.
The step of removing the support and
A step of forming a second wiring layer on the back surface side of the sealed body that was in contact with the support, and
A method for manufacturing a semiconductor device, which comprises a step of sealing the second wiring layer with a sealing material to obtain a third sealing body.
(25) A step of forming a metal wiring layer on the surface of the support is included before the step of mounting the power element on the surface of the support.
The step of obtaining the first sealed body is a step of sealing the power element and the metal wiring layer with a sealing material containing no reinforcing fiber to obtain the first sealed body.
The step of forming an opening for a metal via that reaches the electrode of the power element from the surface of the first encapsulation body is for the metal via that reaches the electrode of the power element from the surface of the first encapsulation. This is a step of forming an opening for a metal via that reaches the metal wiring layer.
The step of forming the first wiring and forming the metal via on the first sealing body forms the first wiring and forms the metal via that reaches the electrode of the power element and the metal via that reaches the metal wiring layer. The process of forming,
The method for manufacturing a semiconductor device according to (24) above.
(26) The method for manufacturing a semiconductor device according to (24) or (25) above, which comprises a step of forming a stress relaxation layer on the surface of the support in advance.

本発明によれば、絶縁信頼性を向上させると共に薄型化、小型化を可能にした半導体装置を提供することができる。 According to the present invention, it is possible to provide a semiconductor device capable of improving insulation reliability and making it thinner and smaller.

図１は本発明の第１の実施形態の半導体装置の構造を示す図である。FIG. 1 is a diagram showing a structure of a semiconductor device according to the first embodiment of the present invention. 図２は本発明の第２の実施形態の半導体装置の構造を示す図である。FIG. 2 is a diagram showing the structure of the semiconductor device according to the second embodiment of the present invention. 図３は本発明の第３の実施形態の半導体装置の構造を示す図である。FIG. 3 is a diagram showing the structure of the semiconductor device according to the third embodiment of the present invention. 図４は本発明の第４の実施形態の半導体装置の構造を示す図である。FIG. 4 is a diagram showing the structure of the semiconductor device according to the fourth embodiment of the present invention. 図５Ａ、図５Ｂは本発明の第４の実施形態の半導体装置の構造を説明する図である。5A and 5B are diagrams illustrating the structure of the semiconductor device according to the fourth embodiment of the present invention. 図６は本発明の第５の実施形態の半導体装置の構造を示す図である。FIG. 6 is a diagram showing the structure of the semiconductor device according to the fifth embodiment of the present invention. 図７は本発明の第６の実施形態の半導体装置の構造を示す図である。FIG. 7 is a diagram showing the structure of the semiconductor device according to the sixth embodiment of the present invention. 図８は本発明の第７の実施形態の半導体装置の構成部材のレイアウトを示す図である。FIG. 8 is a diagram showing a layout of components of the semiconductor device according to the seventh embodiment of the present invention. 図９は本発明の第８の実施形態の半導体装置の構成部材のレイアウトを示す図である。FIG. 9 is a diagram showing a layout of components of the semiconductor device according to the eighth embodiment of the present invention. 図１０Ａ～図１０Ｅは本発明の半導体装置の回路図と半導体装置断面の一例を示す図である。10A to 10E are diagrams showing a circuit diagram of the semiconductor device of the present invention and an example of a cross section of the semiconductor device. 図１１Ａ～図１１Ｅは本発明の第１の実施形態の半導体装置の製造工程の一部を示す図である。11A to 11E are diagrams showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図１１Ｆ～図１１Ｉは本発明の第１の実施形態の半導体装置の製造工程の一部を示す図である。11F to 11I are diagrams showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図１１Ｊ～図１１Ｍは本発明の第１の実施形態の半導体装置の製造工程の一部を示す図である。11J to 11M are diagrams showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図１１Ｎ～図１１Ｐは本発明の第１の実施形態の半導体装置の製造工程の一部を示す図である。11N to 11P are diagrams showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図１２Ａ～図１２Ｃは、本発明の第１の実施形態の半導体装置の製造工程の１部を示す図である。12A to 12C are diagrams showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention. 図１３Ａ、図１３Ｂは、本発明の第１の実施形態の図１１Ｂの別の製造工程の１部を示す図である。13A and 13B are diagrams showing a part of another manufacturing process of FIG. 11B according to the first embodiment of the present invention. 図１４は縦型のパワー素子を複数の封止体層に配置した場合の半導体装置の構造を説明する図である。FIG. 14 is a diagram illustrating a structure of a semiconductor device when a vertical power element is arranged in a plurality of encapsulant layers. 図１５は横型のパワー素子を用いた場合の半導体装置の構造を説明する図である。FIG. 15 is a diagram illustrating a structure of a semiconductor device when a horizontal power element is used. 図１６は従来の半導体装置の構造を示す図である。FIG. 16 is a diagram showing the structure of a conventional semiconductor device. 図１７は従来の半導体装置の構造を示す図である。FIG. 17 is a diagram showing the structure of a conventional semiconductor device. 図１８は従来の半導体装置の構造を示す図である。FIG. 18 is a diagram showing the structure of a conventional semiconductor device.

以下に、本発明を実施するための形態を図面に基づいて説明する。なお、いわゆる当業者は本発明を変更・修正をして他の実施形態をなすことは容易であり、これらの変更・修正は本発明に含まれるものであり、以下の説明はこの発明における実施の形態の例を例示するものであって、本発明を限定するものではない。 Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings. It should be noted that it is easy for a person skilled in the art to modify / modify the present invention to form another embodiment, and these changes / modifications are included in the present invention, and the following description is carried out in the present invention. This is an example of the form of the above, and does not limit the present invention.

本発明の基本的な構成は次の通りである。本発明の半導体装置は、少なくとも１つのパワー素子を備えたパワー回路部を含んでいる。
パワー素子は主面に大電流通電用又は大電圧印加用の第１の電極と小電圧印加用の第２の電極とを有しており、封止材によって第1の封止体内に封止されている。
第１の封止体上には第１の配線層が設けられ、この第１の配線層は封止材によって第２の封止体内に封止されている。
パワー素子の裏面側の第１の封止体側に設けた第２の配線層は封止材によって第３の封止体内に封止されている。
第１の配線層は、パワー素子の第１の電極に金属ビアにより電気的に接続している第１の配線ａと、パワー素子の第２の電極と金属ビアにより電気的に接続している第１の配線ｂとを有している。
第１の配線層は第１の配線ａ（大電流通電用配線又は大電圧印加用配線）、第1の配線ｂ（小電圧印加用配線）とグラウンド、電源配線からなっている。例えばＭＯＳＦＥＴを例に説明すると、第１の配線ａはパワー素子のソース電極及びドレイン電極と電気的に接続されており、第1の配線ｂは制御回路部の制御素子の電極及びパワー素子のゲート電極と電気的に接続されている。
以下では、大電流通電用配線又は大電圧印加用配線である第１の配線ａを「大電流通電配線」といい、小電圧印加用配線である第1の配線ｂを「小電流通電配線」ということがある。 The basic configuration of the present invention is as follows. The semiconductor device of the present invention includes a power circuit unit including at least one power element.
The power element has a first electrode for energizing a large current or applying a large voltage and a second electrode for applying a small voltage on the main surface, and is sealed in the first encapsulation body by a sealing material. Has been done.
A first wiring layer is provided on the first sealing body, and the first wiring layer is sealed in the second sealing body by a sealing material.
The second wiring layer provided on the first sealing body side on the back surface side of the power element is sealed in the third sealing body by the sealing material.
The first wiring layer is electrically connected to the first electrode of the power element by a metal via and the first wiring a, and is electrically connected to the second electrode of the power element by a metal via. It has a first wiring b.
The first wiring layer is composed of a first wiring a (wiring for applying a large current or a wiring for applying a large voltage), a first wiring b (wiring for applying a small voltage), a ground, and a power supply wiring. Taking MOSFET as an example, the first wiring a is electrically connected to the source electrode and the drain electrode of the power element, and the first wiring b is the electrode of the control element of the control circuit unit and the gate of the power element. It is electrically connected to the electrodes.
In the following, the first wiring a, which is a wiring for applying a large current or a wiring for applying a large voltage, is referred to as a "wiring for energizing a large current", and the first wiring b, which is a wiring for applying a small current, is referred to as a "wiring for energizing a small current". There is that.

以下では、上記の本発明の基本的な構成を備えた種々の実施形態について説明する。
なお、本発明は、第１の電極に１Ａ以上の大電流が流れる場合、及び、第１の電極に流れる電流が１Ａ未満であるが第１の電極に１００Ｖ以上の電圧が印加される場合を実施形態として含む。
また、以下では、「封止体」については「第１の封止体」、「第２の封止体」、「第３の封止体」、「第４の封止体」および「第５の封止体」というに５種類の封止体があるが、それぞれの用語は次のように区別して用いている。
第１の封止体： パワー素子を封止する封止体である。第１の封止体を複数設けて、それぞれにパワー素子を封止してもよい。また、制御ICもパワー素子と共に封止されていてもよい。
第２の封止体：前記第１の配線ａと前記第１の配線ｂとを含む配線層を封止する封止体であり、パワー素子及び制御ICを封止しない。第２の封止体を複数層設ける場合には、第１の配線ａを含む配線層を封止した第２の封止体の上方又は下方に第１の配線ｂもしくは小電圧動作チップが設置されている配線を封止した第２の封止体を設ける。
第３の封止体：パワー素子の裏面側の第１の封止体側に設けた第２の配線層を封止する封止体である。
第４の封止体：制御ＩＣのような小電圧動作素子のみを封止する封止体である。
第５の封止体：配線層を封止する封止体で有り、第４の封止体上に形成される。
第５の封止体は、封止される配線層に前記第１の配線ａを含む場合は第２の封止体と同様に耐電圧性を有することが望ましい。 Hereinafter, various embodiments including the above-mentioned basic configurations of the present invention will be described.
In the present invention, there are cases where a large current of 1 A or more flows through the first electrode, and cases where the current flowing through the first electrode is less than 1 A but a voltage of 100 V or more is applied to the first electrode. Included as an embodiment.
Further, in the following, as for the "sealing body", the "first sealing body", the "second sealing body", the "third sealing body", the "fourth sealing body" and the "fourth sealing body" are used. There are five types of encapsulants called "5 encapsulants", and the terms are used separately as follows.
First sealant: A sealant that seals a power element. A plurality of first sealing bodies may be provided, and a power element may be sealed to each of them. Further, the control IC may also be sealed together with the power element.
Second sealant: A sealant that seals the wiring layer including the first wiring a and the first wiring b, and does not seal the power element and the control IC. When a plurality of layers of the second encapsulant are provided, the first wiring b or the small voltage operating chip is installed above or below the second encapsulant that encloses the wiring layer including the first wiring a. A second sealing body that seals the wiring is provided.
Third sealing body: A sealing body that seals a second wiring layer provided on the first sealing body side on the back surface side of the power element.
Fourth sealant: A sealant that seals only a small voltage operating element such as a control IC.
Fifth sealant: A sealant that seals the wiring layer, and is formed on the fourth sealant.
When the wiring layer to be sealed contains the first wiring a, it is desirable that the fifth sealing body has withstand voltage like the second sealing body.

（第１の実施形態）
本実施形態の半導体装置を図１に示す。
本実施形態の半導体装置はパワー素子を含むパワー回路部と、制御素子を含む制御回路部とをワンパッケージ化したものである。
以下では「パワー素子」を「第１のチップ」といい、「パワー素子」を制御する「制御素子」を「第２のチップ」という。
第１のチップは例えばＭＯＳＦＥＴのようなパワー素子である。
以下では、パワー素子として、表裏両面に電極を有する縦型構造のものを使用する場合について述べる。
パワー素子が縦型構造である場合、チップの主面Ｓ１に形成されている第１の電極１１はソース電極であり、第２の電極１２はゲート電極であり、チップの裏面Ｓ２に形成されている第３の電極１３はドレイン電極である。このパワー素子においてはドレイン電極に大電圧を印加し、小電圧のゲート電圧により、ソース電極へのドレイン電流のＯＮ／ＯＦＦの制御が行われる。 (First Embodiment)
The semiconductor device of this embodiment is shown in FIG.
The semiconductor device of this embodiment is a package of a power circuit unit including a power element and a control circuit unit including a control element.
Hereinafter, the "power element" is referred to as a "first chip", and the "control element" that controls the "power element" is referred to as a "second chip".
The first chip is a power element such as a MOSFET.
Hereinafter, a case where a vertical structure having electrodes on both the front and back surfaces is used as the power element will be described.
When the power element has a vertical structure, the first electrode 11 formed on the main surface S1 of the chip is a source electrode, the second electrode 12 is a gate electrode, and is formed on the back surface S2 of the chip. The third electrode 13 is a drain electrode. In this power element, a large voltage is applied to the drain electrode, and ON / OFF of the drain current to the source electrode is controlled by a small gate voltage.

第１のチップ１は主面Ｓ１及び側面Ｓ３が封止材によって封止されて第１の封止体５１が形成されている。
第１の封止体５１の上面には第１の配線層３１が形成されており、第１の配線層３１は封止材によって封止されて第２の封止体５２が形成されている。
第１の配線層３１は第１のチップ１の第１の電極１１と金属ビア４３によって電気的に接続されている。
また、第１の配線層３１は第１の封止体５１内に形成された金属ビア４１によって第２の配線層３２と電気的に接続し、外部端子６０と電気的に接続している。 The main surface S1 and the side surface S3 of the first chip 1 are sealed with a sealing material to form the first sealing body 51.
A first wiring layer 31 is formed on the upper surface of the first sealing body 51, and the first wiring layer 31 is sealed with a sealing material to form a second sealing body 52. ..
The first wiring layer 31 is electrically connected to the first electrode 11 of the first chip 1 by a metal via 43.
Further, the first wiring layer 31 is electrically connected to the second wiring layer 32 by the metal via 41 formed in the first sealing body 51, and is electrically connected to the external terminal 60.

このように、第１のチップ１上の第１の電極１１から第１のチップ１以外の領域の第１の封止体５１に形成した金属ビア４１により、第１のチップ１に対して第３の電極１３と同じ側の第２の配線層３２に電気的に接続した構造にすることにより、例えば、図１６及び図１７に示すボンディングワイヤを用いる場合と比較して、幅広の配線及び大径のビア、多数のビアを設けることが可能となり、導通経路の低抵抗化と、経路短縮による低インダクタンス化が図れ、大電流通電によるジュール発熱の低減やサージ電圧低減が可能となる。 As described above, the metal via 41 formed in the first sealing body 51 in the region other than the first chip 1 from the first electrode 11 on the first chip 1 causes the first chip 1 to be the first. By adopting a structure that is electrically connected to the second wiring layer 32 on the same side as the electrode 13 of 3, the wiring is wider and larger than the case where the bonding wires shown in FIGS. 16 and 17 are used, for example. It is possible to provide vias with a diameter and a large number of vias, reduce the resistance of the conduction path, reduce the inductance by shortening the path, reduce Joule heat generation by energizing a large current, and reduce the surge voltage.

第２の封止体５２の表面には第４の電極１４を有する第２のチップ２が積層されており、第２のチップ２は封止材によって封止されて第４の封止体５３が形成されている。
第４の封止体５３の表面には第３の配線層３３が形成され、この第３の配線層３３は封止材によって封止されて第５の封止体５４が形成されている。
第３の配線層３３は第４の封止体５３内に形成された金属ビア４４によって第２のチップ２の第４の電極１４と電気的に接続されている。また、第３の配線層３３は第４の封止体５３内に形成された金属ビア４２によって第１の配線層３１と電気的に接続されている。 A second chip 2 having a fourth electrode 14 is laminated on the surface of the second sealing body 52, and the second chip 2 is sealed with a sealing material to form a fourth sealing body 53. Is formed.
A third wiring layer 33 is formed on the surface of the fourth sealing body 53, and the third wiring layer 33 is sealed with a sealing material to form a fifth sealing body 54.
The third wiring layer 33 is electrically connected to the fourth electrode 14 of the second chip 2 by the metal via 44 formed in the fourth sealing body 53. Further, the third wiring layer 33 is electrically connected to the first wiring layer 31 by a metal via 42 formed in the fourth sealing body 53.

第１のチップ１の場合と同様に、第２のチップ２の第４の電極１４から第２のチップ２以外の領域の第４の封止体５３に形成した金属ビア４２により、第２のチップ２に対して第４の電極１４と逆側の第１の配線層３１と電気的接続した構造にすることにより、例えば、図１６及び図１７に示すボンディングワイヤを用いる場合と比較して、幅広の配線及び大径のビア、多数の金属ビアを設けることが可能となり、低インダクタンスにより、より高速制御が可能となる。 As in the case of the first chip 1, the metal via 42 formed in the fourth sealant 53 in the region other than the second chip 2 from the fourth electrode 14 of the second chip 2 causes the second chip 2. By making the chip 2 electrically connected to the first wiring layer 31 on the opposite side of the fourth electrode 14, for example, as compared with the case where the bonding wires shown in FIGS. 16 and 17 are used. Wide wiring, large diameter vias, and a large number of metal vias can be provided, and low inductance enables higher speed control.

上記のように半導体装置を構成することにより、第２の配線層３２、金属ビア４１、第１の配線層３１、第１の電極（ソース電極）１１及び第３の電極（ドレイン電極）１３によって大電圧の電気的接続Ｃ１が形成される。一方、第２のチップ２の第４の電極１４、金属ビア４４、第３の配線層３３、金属ビア４２、第１の配線層３１、金属ビア４３及び第２の電極（ゲート電極）１２との間に小電圧の電気的接続Ｃ２が形成される。
そして、第１の電極（ソース電極）１１と第３の電極（ドレイン電極）１３との間に大電圧を印加しておき、第４の電極１４と第２の電極（ゲート電極）１２との間に制御用の小電圧を印加することにより、ソース電極へのドレイン電流のＯＮ／ＯＦＦの制御が行われる。 By configuring the semiconductor device as described above, the second wiring layer 32, the metal via 41, the first wiring layer 31, the first electrode (source electrode) 11 and the third electrode (drain electrode) 13 are used. A high voltage electrical connection C1 is formed. On the other hand, the fourth electrode 14, the metal via 44, the third wiring layer 33, the metal via 42, the first wiring layer 31, the metal via 43, and the second electrode (gate electrode) 12 of the second chip 2 A small voltage electrical connection C2 is formed between the two.
Then, a large voltage is applied between the first electrode (source electrode) 11 and the third electrode (drain electrode) 13, and the fourth electrode 14 and the second electrode (gate electrode) 12 are combined. By applying a small voltage for control between them, ON / OFF of the drain current to the source electrode is controlled.

第２の封止体５２は、第２の封止体上に配置されている、動作電圧が低く／小電流で動作している第２のチップ２と、大電圧が印加されて大電流が通電される第１の配線層３１との間にリーク電流が発生するのを防ぐために設けられる。第１の配線層３１には大電流が流れても第１の配線層３１は第２の封止体５２の封止材によって封止され絶縁が確保されているため、リーク電流によって第２のチップ２の動作に影響を与えることがない。 The second encapsulant 52 has a second chip 2 arranged on the second encapsulant and operating at a low operating voltage / small current, and a large current is applied to the second chip 2. It is provided to prevent a leak current from being generated between the first wiring layer 31 and the energized first wiring layer 31. Even if a large current flows through the first wiring layer 31, the first wiring layer 31 is sealed by the sealing material of the second sealing body 52 to ensure insulation, so that the second wiring layer 31 is seconded by the leak current. It does not affect the operation of the chip 2.

リーク電流の発生を防ぐため、第２の封止体５２の厚みは、金属ビアにより配線間を接続する場合は、金属ビアの製造上適度な厚み範囲が必要であり、例えば、第１の配線層上から概略２０μｍ以上であることが望ましい。
また、第２の封止体５２の絶縁抵抗率は１０１１Ω・ｃｍ以上であることが望ましい。つまり、厚みのバラツキを考慮して、第２の封止体の厚みが１０μｍ以上であれば、第１の配線層３１の面積を例えば１ｃｍ２程度とすると絶縁抵抗は１０８Ω程度となる。第１のチップ２のＳｉ基板の抵抗は数～数百Ωであるので、抵抗比からリーク電流は主に第２の封止体５２の絶縁抵抗値に依存し、中電圧域の数百Ｖの電圧が第１の配線層３１に印加されても、そのリーク電流は１μＡ以下である。このため、数ｍＡ／数ｍＶで動作する第２のチップ２及び後述する第４の実施形態における第４の配線層３４への影響を抑えることができる。第２の封止体の絶縁抵抗率は、１０１４Ω・ｃｍ以上であることが好ましく、この場合、高電圧域の数千Ｖの電圧が印加されてもリーク電圧は、数ｎＡ程度となり、汎用ＣＭＯＳのリーク電流と同等となる。 In order to prevent the generation of leakage current, the thickness of the second encapsulant 52 needs to be in an appropriate thickness range for manufacturing the metal via when connecting the wirings with the metal vias. For example, the first wiring It is desirable that the thickness is approximately 20 μm or more from the layer.
Further, it is desirable that the insulation resistivity of the second sealing body 52 is 10 11 Ω · cm or more. That is, in consideration of the variation in thickness, if the thickness of the second encapsulant is 10 μm or more, the insulation resistance is about 108 Ω if the area of the first wiring layer 31 is, for example, about 1 cm 2 . Since the resistance of the Si substrate of the first chip 2 is several to several hundred Ω, the leakage current mainly depends on the insulation resistance value of the second encapsulant 52 from the resistance ratio, and is several hundred V in the medium voltage range. Even if the voltage of 1 is applied to the first wiring layer 31, the leakage current is 1 μA or less. Therefore, it is possible to suppress the influence on the second chip 2 operating at several mA / several mV and the fourth wiring layer 34 in the fourth embodiment described later. The insulation resistivity of the second sealant is preferably 10 14 Ω · cm or more, and in this case, the leak voltage is about several nA even if a voltage of several thousand V in the high voltage range is applied. It is equivalent to the leakage current of general-purpose CMOS.

第２の封止体５２の封止材としては、少なくとも、第１のチップ１、第１の配線層３１との熱応力ミスマッチを抑えるためにＳｉＯ２等の無機物のフィラーを７０質量％以上の高充填率で含有したエポキシ等の絶縁体を用いることが好ましい。フィラーとしてはエポキシ等の樹脂成分より体積抵抗率が高いものを用いるが、その場合、含有するフィラー表面に沿ってリーク電流が流れることを防止するために、エポキシ等樹脂との密着を確保するとともに、樹脂成分内にフィラーが内包されるようにする必要がある。
そのためには、フィラー粒径は第２の封止体の厚みの２／３以下であることが好ましく、最大粒子径が１０μｍ以下であることが好ましく、さらには６μｍ以下であることがより好ましい。
また、最大粒子径以上の粒子はフィラー全体の２質量％以下であることが望ましい。
第２の封止体は、チップの発熱に対する耐熱性を確保するために、少なくとも、ガラス転移点（ＤＭＡ法）が１５０℃以上であることが望ましい。
封止体の例としては次のものを挙げることができる。
エポキシ系樹脂（ガラス転移温度（ＤＭＡ）：１７２℃、熱膨張係数（α１）：２３ｐｐｍ／℃、弾性率（ＲＴ）：３５ＧＰａ以下） As the sealing material of the second sealing body 52, at least 70% by mass or more of an inorganic filler such as SiO 2 is added in order to suppress a thermal stress mismatch with the first chip 1 and the first wiring layer 31. It is preferable to use an insulator such as epoxy contained in a high filling rate. As the filler, a filler having a higher volume resistance than the resin component such as epoxy is used, but in that case, in order to prevent a leak current from flowing along the surface of the contained filler, adhesion with a resin such as epoxy is ensured and adhesion is ensured. , It is necessary to enclose the filler in the resin component.
For that purpose, the filler particle size is preferably 2/3 or less of the thickness of the second encapsulant, the maximum particle size is preferably 10 μm or less, and more preferably 6 μm or less.
Further, it is desirable that the particles having a maximum particle diameter or more are 2% by mass or less of the total amount of the filler.
It is desirable that the second encapsulant has at least a glass transition point (DMA method) of 150 ° C. or higher in order to secure heat resistance against heat generation of the chip.
Examples of the sealed body include the following.
Epoxy resin (glass transition temperature (DMA): 172 ° C, thermal expansion coefficient (α1): 23 ppm / ° C, elastic modulus (RT): 35 GPa or less)

第１の配線層３１は比較的大電流が通電するため、第１の配線層３１の配線層の厚さは、第２のチップ２と接続される第３の配線層３３の配線層の厚さよりも厚くしてもよい。例えば第３の配線層３３の配線層の厚さが１５μｍである場合、第１の配線層３１の配線層の厚みは３０μｍ以上としてよい。
このため、パワー回路部を比較的大電流を通電する複数の第１のチップ（パワー素子）で構成する場合、第１のチップを第１の封止体５１の１層に横に並べて搭載し、比較的厚い第１の配線層３１を形成することにより、大電流通電するパワー素子の配線層を１層形成し、かつ、より微細パッドピッチの制御素子に対しても第３の配線層３３の配線層厚を薄くでき、より微細配線の形成が可能となり、素子の選択の自由度が増すので望ましい。 Since the first wiring layer 31 is energized with a relatively large current, the thickness of the wiring layer of the first wiring layer 31 is the thickness of the wiring layer of the third wiring layer 33 connected to the second chip 2. It may be thicker than that. For example, when the thickness of the wiring layer of the third wiring layer 33 is 15 μm, the thickness of the wiring layer of the first wiring layer 31 may be 30 μm or more.
Therefore, when the power circuit unit is composed of a plurality of first chips (power elements) that carry a relatively large current, the first chips are mounted side by side on one layer of the first encapsulant 51. By forming a relatively thick first wiring layer 31, a wiring layer of a power element that conducts a large current is formed, and a third wiring layer 33 is also formed for a control element having a finer pad pitch. It is desirable because the thickness of the wiring layer can be reduced, finer wiring can be formed, and the degree of freedom in selecting the element is increased.

前記したように、パワー素子には、ＳｉのＭＯＳＦＥＴ、ＩＧＢＴのようにチップの主面とチップの裏面との両面に電極を持ち、チップ内を垂直方向に大電流通電させる縦型構造のものと、ＧａＮ ｏｎ Ｓｉのように片面にのみ、つまり主面にのみ電極をもち水平方向へ大電流を通電する横型構造のものとがある。
上記実施形態では縦型構造のものを用いた場合について説明したが、縦型構造及び横型構造のいずれにおいても、パワー回路部と制御回路部とを積層する場合には、第２の封止体５２の耐電圧性は重要である。 As described above, the power element has a vertical structure such as Si MOSFET and IGBT, which has electrodes on both the main surface of the chip and the back surface of the chip and energizes the inside of the chip with a large current in the vertical direction. , GaN on Si, which has an electrode on only one side, that is, on the main side, and has a horizontal structure in which a large current is applied in the horizontal direction.
In the above embodiment, the case where the vertical structure is used has been described, but in both the vertical structure and the horizontal structure, when the power circuit unit and the control circuit unit are laminated, the second sealed body is used. The withstand voltage of 52 is important.

第１の電極１１及び第２の電極１２は、ＳｉＮやＳｉＯ２のパッシベーション膜に開口が形成されたＡｌ等の電極であり、その上にシードメタル層を形成し、このシードメタル層上にめっき技術等を用いて５ｕｍ厚程度のＣｕ膜等を形成すると、レーザーによるビア用開口形成の際のＡｌ電極のダメージを防止できる。また、第３の電極１３は、Ｓｉ、ＳｉＣの半導体基板に電極としてバックメタルが全面に形成され、オーミック接続されており、同様に必要に応じてめっき技術等を用いて５μｍ厚程度のＣｕ膜等を形成してもよい。 The first electrode 11 and the second electrode 12 are electrodes such as Al having an opening formed in the passivation film of SiN or SiO 2 , and a seed metal layer is formed on the electrode, and plating is performed on the seed metal layer. By forming a Cu film or the like having a thickness of about 5 um by using a technique or the like, it is possible to prevent damage to the Al electrode when forming an opening for via by a laser. Further, the third electrode 13 has a back metal formed on the entire surface as an electrode on a Si, SiC semiconductor substrate and is ohmic-connected. Similarly, if necessary, a Cu film having a thickness of about 5 μm is used by using plating technology or the like. Etc. may be formed.

図１ではパワー素子の裏面側の接続構造については詳細には示していないので、この接続構造について述べる。
縦型構造のパワー素子の場合は、そのチップ裏面にバックメタルと呼ばれる金属膜層を形成し、これと第２の配線層３２とを電気的に接続する。その接続には、例えば５０μｍ厚の銀や銅の焼結材やはんだ材等の導電性材料を用いてダイボンドする方法や、大電流通電が可能なように多数の金属ビアを用いて接続する方法がある。 Since the connection structure on the back surface side of the power element is not shown in detail in FIG. 1, this connection structure will be described.
In the case of a power element having a vertical structure, a metal film layer called a back metal is formed on the back surface of the chip, and this is electrically connected to the second wiring layer 32. For the connection, for example, a method of die-bonding using a conductive material such as a 50 μm thick silver or copper sintered material or a solder material, or a method of connecting using a large number of metal vias so that a large current can be energized. There is.

チップ裏面に層状に設けた導電性材料を用いて接続する場合と、金属ビアを用いて接続する場合とを比較する。
層状に設けた導電性材料によって接続する場合、導電性材料として現在一般的に用いられている鉛含有量が９５質量％のはんだの熱伝導率は３５Ｗ／ｍ・Ｋである。これに対し、金属ビアの材料であるＣｕの熱伝導率は３９８Ｗ／ｍ・Ｋであり、はんだの熱伝導率の約１１倍である。このため、金属ビアを用いて接続することが好ましい。また、金属ビアの熱伝導率を良くするために、Ｃｕのフィルドビアを第１のチップの面積に対して１／１０以上、例えば１／４以上の面積率で形成することが好ましい。
実際には、パッケージ熱抵抗のような温度低下に対して、熱伝導率の影響は反比例するため、１／４以上の面積のフィルドビアによる接続であれば、約２００Ｗ／ｍ・Ｋ以上の焼結Ａｇ材を層状に設けた場合と比べても、実際の温度低下はあまり大きく変わらない。 The case of connecting using a conductive material provided in a layer on the back surface of the chip and the case of connecting using a metal via are compared.
When connected by a conductive material provided in a layer, the thermal conductivity of solder having a lead content of 95% by mass, which is generally used as a conductive material at present, is 35 W / m · K. On the other hand, the thermal conductivity of Cu, which is a material for metal vias, is 398 W / m · K, which is about 11 times the thermal conductivity of solder. Therefore, it is preferable to connect using a metal via. Further, in order to improve the thermal conductivity of the metal via, it is preferable to form the Cu filled via with an area ratio of 1/10 or more, for example, 1/4 or more with respect to the area of the first chip.
In reality, the effect of thermal conductivity is inversely proportional to the temperature drop such as package thermal resistance, so if the connection is made with filled vias with an area of 1/4 or more, sintering of about 200 W / m · K or more. The actual temperature drop does not change much even when the Ag material is provided in layers.

また、金属ビアの周囲には、チップをダイアタッチするための接着材を設けてもよい。その場合には、第１のチップ１と第２の配線層３２との熱膨張ミスマッチを吸収するために、ビア面積率を１／１０以上にし、第１のチップ領域の第２の配線層３２の配線層にスリット等を設け、接着材の弾性率を数十Ｍ～数ＧＰａとし、厚みを例えば５～２０μｍの範囲としてもよい。この接着材は封止材に用いた樹脂とは異なる樹脂から選択してもよい。 Further, an adhesive material for die-attaching the chip may be provided around the metal via. In that case, in order to absorb the thermal expansion mismatch between the first chip 1 and the second wiring layer 32, the via area ratio is set to 1/10 or more, and the second wiring layer 32 in the first chip region 32. The wiring layer may be provided with a slit or the like, the elastic modulus of the adhesive may be several tens of M to several GPa, and the thickness may be in the range of, for example, 5 to 20 μm. This adhesive may be selected from a resin different from the resin used for the sealing material.

また、第１のチップ１を支持体１０１にダイアタッチするための接着材と支持体との間にさらに追加の封止体を設けてもよい。接着材は、樹脂成分が多く、比較的柔らかいものを用いると、チップとの熱膨張ミスマッチが緩和できるために望ましいが、追加の第６の封止体を設けると、接着材が第１の封止体と追加の第６の封止体とに囲まれているので、第２の配線層３２の導電パターン形成の際のエッチング等の工程で接着材に求められる耐エッチング液性を必ずしも必要としないので、接着材の選択範囲が広がる。 Further, an additional sealing body may be provided between the adhesive for attaching the first chip 1 to the support 101 and the support. It is desirable to use an adhesive having a large amount of resin component and being relatively soft because the thermal expansion mismatch with the chip can be alleviated. However, if an additional sixth encapsulant is provided, the adhesive becomes the first seal. Since it is surrounded by a stationary body and an additional sixth sealing body, it is not always necessary to have the etching resistance required for the adhesive in steps such as etching when forming the conductive pattern of the second wiring layer 32. Since it does not, the selection range of the adhesive is widened.

パワーデバイスは大電流を通電させると、オン抵抗によるジュール熱により温度上昇するために、放熱経路の確保が重要となる。第２の配線層３２を厚くすると、発生した熱が第２の配線層３２内を伝熱し、第１のチップ１の裏面側の放熱面積が増加し、放熱性向上が得られる。また、第１のチップ１の領域の第２の配線層を外部端子とすると、実装する有機基板、冷却板等への放熱経路が短く、ほぼ第１のチップと同サイズ、もしくはそれ以上の放熱領域が得ることができる。 When a large current is applied to a power device, the temperature rises due to Joule heat due to the on-resistance, so it is important to secure a heat dissipation path. When the second wiring layer 32 is made thicker, the generated heat is transferred to the inside of the second wiring layer 32, the heat dissipation area on the back surface side of the first chip 1 is increased, and the heat dissipation is improved. Further, when the second wiring layer in the region of the first chip 1 is used as an external terminal, the heat dissipation path to the organic substrate, the cooling plate, etc. to be mounted is short, and the heat radiation is substantially the same size as or larger than that of the first chip. The area can be obtained.

第１のチップ１の裏面に電極を持つ場合には、第２の配線層３２が伝熱拡大層としての機能も有するが、チップの片面（Ｓ１面）にのみ電極を持つ場合でも、高熱伝導材料からなる第２の配線層３２を第１のチップ１の裏面の領域に設置することにより放熱性が向上する。 When the second wiring layer 32 also has a function as a heat transfer expansion layer when the electrode is provided on the back surface of the first chip 1, high heat conduction is achieved even when the electrode is provided on only one side (S1 surface) of the chip. By installing the second wiring layer 32 made of a material in the region on the back surface of the first chip 1, the heat dissipation is improved.

このようなパッケージ構造とすると、第２の封止体５２の厚みを薄く抑え、かつパワーデバイスで数千Ｖの電圧が印加しても耐圧を維持でき、ビアの挟ピッチ化や低背化の点で有利となる。
さらに好ましくは、第１の配線層３１の大電流通電配線上に第２のチップ（制御ＩＣ）２を配置するのではなく、例えば、第１の電極１１（ソース電極）や第３の電極１３（ドレイン電極）と電気接続する大電流通電配線上ではない領域の第２の封止体５２上や、第２の電極１２（ゲート電極）と電気的に接続する小電流通電配線上の領域の第２の封止体５２上に第２のチップ２を配置すると、第２のチップとの大電流／大電圧の耐電圧を確保でき、電界ノイズの影響を低減できる。 With such a package structure, the thickness of the second encapsulant 52 can be kept thin, and the withstand voltage can be maintained even when a voltage of several thousand V is applied by the power device. It is advantageous in terms of points.
More preferably, instead of arranging the second chip (control IC) 2 on the large current current-carrying wiring of the first wiring layer 31, for example, the first electrode 11 (source electrode) and the third electrode 13 On the second encapsulating body 52 in a region not on the large current energized wiring that is electrically connected to (drain electrode), or in the region on the small current energized wiring that is electrically connected to the second electrode 12 (gate electrode). By arranging the second chip 2 on the second sealing body 52, it is possible to secure a withstand voltage of a large current / a large voltage with the second chip, and it is possible to reduce the influence of electric field noise.

（第２の実施形態）
第２の実施形態を図２に示す。
本実施形態の半導体装置はパワー素子を含むパワー回路部と、制御素子を含む制御回路部とをワンパッケージ化したものである。
図２に示したものは、第２のチップ２を接着材３によって第１の配線層３１を封止材で封止した第２の封止体５２の上にダイボンドした後、ボンディングワイヤ２１によって第４の電極１４と第１の配線層３１の接続用ランド２２とをワイヤボンディングし、次いで、第２のチップ２及びボンディングワイヤ２１をモールド樹脂等の封止材で封止して第４の封止体５３を形成したものである。 (Second embodiment)
The second embodiment is shown in FIG.
The semiconductor device of this embodiment is a package of a power circuit unit including a power element and a control circuit unit including a control element.
In the one shown in FIG. 2, the second chip 2 is die-bonded onto the second encapsulant 52 in which the first wiring layer 31 is sealed with the encapsulant 3 by the adhesive material 3, and then the bonding wire 21 is used. The fourth electrode 14 and the connection land 22 of the first wiring layer 31 are wire-bonded, and then the second chip 2 and the bonding wire 21 are sealed with a sealing material such as a mold resin to form a fourth. The sealed body 53 is formed.

（第３の実施形態）
第３の実施形態を図３に示す。
本実施形態の半導体装置はパワー素子を含むパワー回路部と制御素子を含む制御回路部とをワンパッケージ化したものである。
図３に示したものは、第２の封止体５２の第１の配線層３１上に接続用ランド２３を設けて、第２のチップ２を第４の電極１４を下向きにして、この電極１４と接続用ランド２３とをフリップチップ接続したのち、アンダーフィル樹脂４を第２のチップ２と第２の封止体５２との間の隙間に充填したものである。第２のチップ上の第４の電極１４と接続用ランド２３とを直接電気接続できるため、導通経路短により低インダクタンスとなり、さらに高速制御が可能となる。 (Third embodiment)
A third embodiment is shown in FIG.
The semiconductor device of this embodiment is a package of a power circuit unit including a power element and a control circuit unit including a control element.
In the one shown in FIG. 3, a connection land 23 is provided on the first wiring layer 31 of the second sealing body 52, and the second chip 2 is oriented with the fourth electrode 14 facing downward. After flip-chip connecting the 14 and the connecting land 23, the underfill resin 4 is filled in the gap between the second chip 2 and the second sealing body 52. Since the fourth electrode 14 on the second chip and the connection land 23 can be directly electrically connected, the short conduction path results in low inductance and further high-speed control is possible.

（第４の実施形態）
第４の実施形態の半導体装置を図４に示す。
第４の実施形態の半導体装置はパワー素子を含むパワー回路部と制御素子を含む制御回路部とをワンパッケージ化したものである。
本実施形態の半導体装置は図１に示した第１の実施形態の半導体装置において、第１の配線層３１を封止材で封止してなる第２の封止体（Ａ）５２ａと、第２のチップ２を封止材で封止してなる第３の封止体５３との間に、第４の配線層３４を封止材で封止した第２の封止体（Ｂ）５２ｂ設けたものである。
この構造は次のようにして形成される。
第１の封止体５１上に第１の配線層３１を形成した後、この第１の配線層３１を封止材で封止して第２の封止体（Ａ）５２ａを形成する。次いで、第２の封止体（Ａ）５２ａ上に第４の配線層３４を形成し、この第４の配線層３４を封止材で封止して第２の封止体（Ｂ）５２ｂを形成する。
第２の封止体（Ｂ）５２ｂ上に第２のチップ２を積層し、第２のチップ２を封止材で封止して第４の封止体５３を形成する。
次いで、第４の封止体５３の表面に第３の配線層３３を形成し、この第３の配線層３３を封止材で封止して第５の封止体５４を形成する。
第２のチップ２の第４の電極１４は、金属ビア４４、第３の配線層３３、第４の封止体５３と第２の封止体（Ｂ）５２ｂとに形成された金属ビア４２を介して第４の配線層３４と電気的に接続されている。また、第４の配線層３４は第２の封止体（Ａ）５２ａ内に形成された金属ビア４５ｂ、第１の配線層３１及び金属ビア４６を介して第１のチップ１の第２の電極（ゲート電極）１２と電気的に接続されている。
このように、第１（第４）の配線層、第２の配線層及び第３の配線層を多層に設けることは、必要に応じて、金属ビア、封止体、配線層を逐次形成して、任意に実施することができる。 (Fourth Embodiment)
The semiconductor device of the fourth embodiment is shown in FIG.
The semiconductor device of the fourth embodiment is a package in which a power circuit unit including a power element and a control circuit unit including a control element are packaged.
The semiconductor device of this embodiment is the semiconductor device of the first embodiment shown in FIG. 1, in which the first wiring layer 31 is sealed with a sealing material and the second sealing body (A) 52a is formed. A second sealing body (B) in which a fourth wiring layer 34 is sealed with a sealing material between the second chip 2 and a third sealing body 53 formed by sealing with a sealing material. 52b is provided.
This structure is formed as follows.
After forming the first wiring layer 31 on the first sealing body 51, the first wiring layer 31 is sealed with a sealing material to form the second sealing body (A) 52a. Next, a fourth wiring layer 34 is formed on the second sealing body (A) 52a, and the fourth wiring layer 34 is sealed with a sealing material to seal the second sealing body (B) 52b. To form.
The second chip 2 is laminated on the second sealing body (B) 52b, and the second chip 2 is sealed with a sealing material to form the fourth sealing body 53.
Next, a third wiring layer 33 is formed on the surface of the fourth sealing body 53, and the third wiring layer 33 is sealed with a sealing material to form a fifth sealing body 54.
The fourth electrode 14 of the second chip 2 is a metal via 42 formed of a metal via 44, a third wiring layer 33, a fourth sealant 53, and a second sealant (B) 52b. It is electrically connected to the fourth wiring layer 34 via the wire. Further, the fourth wiring layer 34 is the second of the first chip 1 via the metal via 45b formed in the second sealing body (A) 52a, the first wiring layer 31 and the metal via 46. It is electrically connected to the electrode (gate electrode) 12.
In this way, by providing the first (fourth) wiring layer, the second wiring layer, and the third wiring layer in multiple layers, the metal via, the encapsulant, and the wiring layer are sequentially formed as needed. It can be carried out arbitrarily.

本実施形態である図４では、第２の封止体（Ａ）５２ａ内の第１の配線層３１に大電流通電配線及び小電流通電配線を含み、第２の封止体（Ｂ）５２ｂ内の第４の配線層３４に小電流通電配線と、大電流通電配線と同電位の配線とを含んでいる。
第２の封止体（Ａ）５２ａ及び第２の封止体（Ｂ）５２ｂはそれぞれ大電流通電配線と電気的に接続される第１の配線層及び第４の配線層を含む封止体であり、その耐電圧性は重要である。
また、このように第１のチップ１と第２のチップ２との間に複数の封止体層を設け、第２のチップ２と第１の配線層３１の大電流通電配線との間にグラウンドに接続した導電パターンを第４の配線層３４に設けると、リーク電流は第２のチップ２のＳｉ基板とは接続されず、特にパワー素子のスイッチング周波数が大きくなっても、第２のチップ２の信号が安定する。 In FIG. 4 of the present embodiment, the first wiring layer 31 in the second encapsulating body (A) 52a includes a large current energizing wiring and a small current energizing wiring, and the second encapsulating body (B) 52b. The fourth wiring layer 34 includes a small current energized wiring and a wiring having the same potential as the large current energized wiring.
The second sealing body (A) 52a and the second sealing body (B) 52b are sealing bodies including a first wiring layer and a fourth wiring layer that are electrically connected to the high-current energized wiring, respectively. And its withstand voltage is important.
Further, in this way, a plurality of encapsulant layers are provided between the first chip 1 and the second chip 2, and between the second chip 2 and the large current current-carrying wiring of the first wiring layer 31. When the conductive pattern connected to the ground is provided in the fourth wiring layer 34, the leakage current is not connected to the Si substrate of the second chip 2, and even if the switching frequency of the power element is increased, the second chip is not connected. The signal of 2 is stable.

第２の封止体５２内に配線層を多層に設ける場合には、大電流通電配線上に小電流通電配線を設けないことがより望ましいが、大電流通電配線上に小電流通電配線を設ける場合には、第４の配線層３４に含まれる小電流配線の電流は数十ｍＡであるので、リーク電流は数十μＡ以下であることが望ましい。
封止体の厚みバラツキを考慮すると、第２の封止体の封止材の絶縁抵抗率が１０１２Ω・ｃｍ以上であれば、第４の配線層３４が、第１の配線層３１の上にあって、第１の配線層３１上の第４の配線層３４の面積が例えば１ｃｍ２程度あったとしても、第２の封止体の厚みが１０μｍ以上あれば、第１の配線層３１と第４の配線層３４間の絶縁抵抗は１０９Ω程度となり、リーク電流を数μＡ以下に抑えることができる。 When the wiring layers are provided in multiple layers in the second encapsulating body 52, it is more desirable not to provide the small current energization wiring on the large current energization wiring, but to provide the small current energization wiring on the large current energization wiring. In this case, since the current of the small current wiring included in the fourth wiring layer 34 is several tens of mA, it is desirable that the leakage current is several tens of μA or less.
Considering the variation in the thickness of the encapsulant, if the insulation resistivity of the encapsulant of the second encapsulant is 10 12 Ω · cm or more, the fourth wiring layer 34 is the first wiring layer 31. Even if the area of the fourth wiring layer 34 on the first wiring layer 31 is, for example, about 1 cm 2 , if the thickness of the second sealant is 10 μm or more, the first wiring layer is on the top. The insulation resistance between 31 and the fourth wiring layer 34 is about 109 Ω, and the leakage current can be suppressed to several μA or less.

図４に示した構造においては、第２のチップ（制御素子）２のチップ厚が５０μｍ厚の場合は、第２のチップ２の回路面から第１の配線層３１までの距離が概略６０μｍ以上となるため、パワー素子のスイッチングによる電磁気ノイズに対する制御素子の影響を軽減できる。
また、大電流通電する第１の配線層３１上に第４の配線層３４を設け、第１の配線層３１と第４の配線層３４とを図４の点線で示すようにコの字上に電気的に接続すると第１の配線層３１の大電流の電流変化に対して逆位相の電界が生じ、パワー素子のスイッチングノイズが低減され、第３の配線層や、第２のチップ２への影響を小さくすることができる。この場合の大電流通電する第１の配線層３１と第４の配線層３４の電気的接続は、図４の点線で示すように第１の配線層３１のチップ外に引き出される通電経路の反対側に位置する金属ビア４５ａにより接続されることが望ましい。 In the structure shown in FIG. 4, when the chip thickness of the second chip (control element) 2 is 50 μm, the distance from the circuit surface of the second chip 2 to the first wiring layer 31 is approximately 60 μm or more. Therefore, the influence of the control element on the electromagnetic noise due to the switching of the power element can be reduced.
Further, a fourth wiring layer 34 is provided on the first wiring layer 31 that is energized with a large current, and the first wiring layer 31 and the fourth wiring layer 34 are shown in a U shape as shown by the dotted line in FIG. When electrically connected to the first wiring layer 31, an electric field having an opposite phase is generated with respect to a large current change of the first wiring layer 31, the switching noise of the power element is reduced, and the wiring is connected to the third wiring layer or the second chip 2. The effect of can be reduced. In this case, the electrical connection between the first wiring layer 31 and the fourth wiring layer 34, which is energized with a large current, is opposite to the energization path drawn out of the chip of the first wiring layer 31 as shown by the dotted line in FIG. It is desirable to be connected by a metal via 45a located on the side.

またパワー素子１の過電流検知のために、グラウンドに接続された第１の電極１１、第１の配線層３１（第４の配線層３４）、金属ビア４２、第３の配線層３３及び金属ビア４４を介して第２のチップ２の第４の電極１４に電気的に接続する配線パターンを形成することもできる。このような層状の配線層を形成することは、電気接続経路の設計自由度が向上する。 Further, for detecting the overcurrent of the power element 1, the first electrode 11 connected to the ground, the first wiring layer 31 (fourth wiring layer 34), the metal via 42, the third wiring layer 33, and the metal. It is also possible to form a wiring pattern that is electrically connected to the fourth electrode 14 of the second chip 2 via the via 44. Forming such a layered wiring layer improves the degree of freedom in designing the electrical connection path.

実施形態１においては第２の封止体５２による半導体装置の厚さ方向の絶縁性向上効果に関して述べた。ところで第２の封止体５２の封止材は、ガラスクロスや不織布等の補強繊維を含まない、ポリイミド樹脂、エポキシ樹脂、エポキシ樹脂等にフィラーを含有させた縦横の構成が同じ絶縁体であることが好ましい。補強繊維を含まない封止材を用いることにより、補強繊維を含まない封止材は第１の配線層３１の上面だけではなく第１の配線層３１の側面にも配置されているので、半導体装置の水平方向に関しても同様の絶縁性向上効果が得られる。 In the first embodiment, the effect of improving the insulating property in the thickness direction of the semiconductor device by the second sealing body 52 has been described. By the way, the sealing material of the second sealing body 52 is an insulator that does not contain reinforcing fibers such as glass cloth and non-woven fabric and has the same vertical and horizontal configurations in which a filler is contained in a polyimide resin, an epoxy resin, an epoxy resin or the like. Is preferable. By using a sealing material that does not contain reinforcing fibers, the sealing material that does not contain reinforcing fibers is arranged not only on the upper surface of the first wiring layer 31 but also on the side surface of the first wiring layer 31, so that the semiconductor is used. A similar effect of improving insulation can be obtained in the horizontal direction of the device.

（第５の実施形態）
第５の実施形態の半導体装置を図５Ａ，図５Ｂに示す。
図５Ａは第４の実施形態の半導体装置の第１の封止体５１の部分と第２の封止体（Ａ）５２ａと第２の封止体（Ｂ）５２ｂの部分とを示したものである。
図５Ａに示した構造を有する構造体をパッケージ化してパワー素子を含むパッケージとして用いることができる。
第１のチップ１においては大電流通電／大電圧通電用の第１の電極１１と、小電流通電／小電圧通電用の第２の電極１２とが同一面に設置されており、大電流通電／大電圧印加用の配線である第１の配線（Ａ）３１ａは第１の電極１１の上方に設けられ、小電流通電／小電圧印加用の配線である第１の配線（Ｂ）３１ｂは第２の電極１２の上方に設けられている。
そして、第１の配線（Ａ）３１ａと第１の配線（Ｂ）３１ｂとの間には第２の封止体（Ａ）５２ａが存在し絶縁性が良いため第１の配線３１ａと第１の配線３１ｂとの水平方向の間隔ｄ２がより小さくでき、小型化、高密度配線化が可能となる。
また、第２の封止体５２を用いることにより厚み方向の配線間の間隔ｄ１をより小さくすることができる。このため、第２の封止体を用いると、パワー回路部の薄膜化が可能となる。 (Fifth Embodiment)
The semiconductor device of the fifth embodiment is shown in FIGS. 5A and 5B.
FIG. 5A shows a portion of the first encapsulation body 51, a portion of the second encapsulation body (A) 52a, and a portion of the second encapsulation body (B) 52b of the semiconductor device of the fourth embodiment. Is.
The structure having the structure shown in FIG. 5A can be packaged and used as a package including a power element.
In the first chip 1, the first electrode 11 for large current energization / large voltage energization and the second electrode 12 for small current energization / small voltage energization are installed on the same surface, and the large current energization is performed. / The first wiring (A) 31a, which is a wiring for applying a large voltage, is provided above the first electrode 11, and the first wiring (B) 31b, which is a wiring for energizing a small current / applying a small voltage, is provided. It is provided above the second electrode 12.
Since the second sealing body (A) 52a exists between the first wiring (A) 31a and the first wiring (B) 31b and the insulating property is good, the first wiring 31a and the first wiring (B) 31b are present. The horizontal distance d2 from the wiring 31b can be made smaller, and miniaturization and high-density wiring can be achieved.
Further, by using the second sealing body 52, the distance d1 between the wirings in the thickness direction can be made smaller. Therefore, if the second encapsulant is used, the power circuit portion can be made thinner.

なお、この効果は、第４の実施形態で示した第４の配線層３４を設ける場合のみでなく、下記のいずれの場合にも奏される。
・大電流通電用／大電圧印加用の配線と、小電圧印加用の配線とが同一配線層内にある場合
・大電流通電用／大電圧印加用の配線と小電圧印加用の配線とが多層配線である場合
・大電流通電用／大電圧印加用の配線と小電圧印加用の配線とが同一配線層内にあり、更にその上に小電流通電の配線層がある場合 It should be noted that this effect is exhibited not only when the fourth wiring layer 34 shown in the fourth embodiment is provided, but also in any of the following cases.
-When the wiring for high current energization / large voltage application and the wiring for small voltage application are in the same wiring layer-The wiring for large current energization / large voltage application and the wiring for small voltage application are In the case of multi-layer wiring-When the wiring for high current energization / large voltage application and the wiring for small voltage application are in the same wiring layer, and there is a wiring layer for small current energization above it.

例えば、従来の半導体装置は、製造工程時における反り防止および製品としての反り防止や強度確保の目的から、封止材として少なくとも一部に補強繊維にエポキシ樹脂などの熱硬化性樹脂を含浸し硬化させてなる剛性を有する複合材料（以下「プリプレグ」ということもある）からなる絶縁材料が用いられる。一方、第２の封止体５２は封止材としてガラスクロスや不織布等の補強繊維を含まない、縦横の構成が同じ絶縁材料を用いるため、耐電圧に対して同一配線層内及び厚さ方向ともに同様の効果が得られる。必ずしも、図５Ａに示すように第１の配線層３１と第４の配線層３４とからなる多層構造でなくとも、図５Ｂに示すように、１層の第１の配線層３１でも同様の効果が得られる。なお、第１のチップ１の第２の電極１２と金属ビア４３で電気的に接続されている第１の配線層３１ｂは、図示していないが、例えば、金属ビア４１、第２の配線層３２を介して、外部端子へ電気的接続される。
図５Ｂに示した構造を有する構造体をパッケージ化してパワー素子を含むパッケージとして用いることができる。 For example, a conventional semiconductor device is cured by impregnating at least a part of a reinforcing fiber with a thermosetting resin such as an epoxy resin as a sealing material for the purpose of preventing warpage during the manufacturing process, preventing warpage as a product, and ensuring strength. An insulating material made of a composite material having rigidity (hereinafter, also referred to as "prepreg") is used. On the other hand, since the second encapsulant 52 uses an insulating material having the same vertical and horizontal configurations, which does not contain reinforcing fibers such as glass cloth and non-woven fabric as the encapsulant, it is in the same wiring layer and in the thickness direction with respect to the withstand voltage. Both have the same effect. It is not always the case that the multilayer structure is composed of the first wiring layer 31 and the fourth wiring layer 34 as shown in FIG. 5A, but the same effect can be obtained with the first wiring layer 31 of one layer as shown in FIG. 5B. Is obtained. Although the first wiring layer 31b electrically connected to the second electrode 12 of the first chip 1 by the metal via 43 is not shown, for example, the metal via 41 and the second wiring layer It is electrically connected to the external terminal via 32.
The structure having the structure shown in FIG. 5B can be packaged and used as a package including a power element.

また、チップ、金属ビアのいずれかが隣接している第１の封止体５１においても、第２の封止体５２において用いた封止材と同一、または同様の特徴をもつ封止材を用いることにより、第１のチップ上の第１の電極１１と第２の電極１２との間隔をデバイス特性が得られる距離まで縮めて、第１の電極１１のサイズをより大きくし、第１の配線層３１との接続用の金属ビアをより多く形成できるため、パッケージのオン抵抗を下げることもできる。また、第１のチップの横に設置されるビア／チップ間、またはビア間の耐電圧を向上できる。 Further, even in the first encapsulant 51 to which either the chip or the metal via is adjacent, the encapsulant having the same or the same characteristics as the encapsulant used in the second encapsulant 52 can be used. By using, the distance between the first electrode 11 and the second electrode 12 on the first chip is shortened to a distance where the device characteristics can be obtained, and the size of the first electrode 11 is increased to obtain the first electrode. Since more metal vias for connection with the wiring layer 31 can be formed, the on-resistance of the package can be lowered. Further, the withstand voltage between vias / chips installed next to the first chip or between vias can be improved.

また、第２のチップ２は、例えば、Ｓｉデバイスの制御ＩＣの他、数Ａ以下／数Ｖ以下の小電流通電／小電圧印加で動作するセンサー等小電流動作素子であってもよい。さらに、制御回路部はパワー回路部のパッケージと図１、図２、図３に示したように積層しなくても、パワー回路部のパッケージの外部端子を介して電気的に接続される別パッケージを実装ボードでモジュール化してもよい。 Further, the second chip 2 may be, for example, a small current operating element such as a sensor that operates by applying a small current of several A or less / several V or less / applying a small voltage, in addition to the control IC of the Si device. Further, the control circuit unit is a separate package that is electrically connected to the power circuit unit package via the external terminal of the power circuit unit package without stacking as shown in FIGS. 1, 2, and 3. May be modularized on the mounting board.

図５Ａ又は図５Ｂに示す構造を有するパワー素子を含むパッケージと、制御素子をパッケージ化してなるパッケージと組み合わせてパワーモジュールとして使用することができる。 It can be used as a power module in combination with a package including a power element having the structure shown in FIG. 5A or FIG. 5B and a package in which the control element is packaged.

（第６の実施形態）
第６の実施形態を図６に示す。
本実施形態の半導体装置はパワー素子を含むパワー回路部と制御素子を含む制御回路部とをワンパッケージ化したものである。
図６に示したものは、第２のチップ２を接着材３によって第２の封止体（Ｂ）５２ｂにダイボンドした後、ボンディングワイヤ２１によって第４の電極１４と第４の配線層３４の接続用ランド２２とをワイヤボンディングし、次いで、第２のチップ、及びボンディングワイヤ２１を封止材で封止して第４の封止体５３を形成したものである。 (Sixth Embodiment)
A sixth embodiment is shown in FIG.
The semiconductor device of this embodiment is a package of a power circuit unit including a power element and a control circuit unit including a control element.
In the one shown in FIG. 6, the second chip 2 is die-bonded to the second sealing body (B) 52b by the adhesive material 3, and then the fourth electrode 14 and the fourth wiring layer 34 are formed by the bonding wire 21. The connecting land 22 is wire-bonded, and then the second chip and the bonding wire 21 are sealed with a sealing material to form a fourth sealing body 53.

（第７の実施形態）
第７の実施形態を図７に示す。
本実施形態の半導体装置はパワー素子を含むパワー回路部と制御素子を含む制御回路部とをワンパッケージ化したものである。
図７に示したものは、第２の封止体（Ｂ）５２ｂの上に接続用ランド２３を設けて、第２のチップ２を電極１４が下向きになるようにし、この電極１４と接続用ランド２３とをフリップチップ接続したのち、アンダーフィル樹脂４を第２のチップ２と第２の封止体（Ｂ）５２ｂとの間の隙間に充填したものである。 (7th Embodiment)
A seventh embodiment is shown in FIG.
The semiconductor device of this embodiment is a package of a power circuit unit including a power element and a control circuit unit including a control element.
In the one shown in FIG. 7, a connecting land 23 is provided on the second sealing body (B) 52b so that the electrode 14 of the second chip 2 faces downward, and the second chip 2 is connected to the electrode 14. After the land 23 is flip-chip connected, the underfill resin 4 is filled in the gap between the second chip 2 and the second sealing body (B) 52b.

（第８の実施形態）
第８の実施形態を図８に示す。
図８は、図１に示した半導体装置において、ひとつの第１のチップ１として、その表面に第１の電極１１と第２の電極１２を、裏面に第３の電極をもつ縦型構造のパワー素子を用いた場合の、第１の配線層３１の配線層のパターンと第１のチップ１、第１のチップ横の金属ビア４１、第１の電極１１及び第２の電極１２上の金属ビア４３、第２の電極１２と第２のチップを電気的に接続する第２のチップ横の金属ビア４２のレイアウトの例を示したものである。なお、図１で積層された第２のチップは図８には図示していない。また第２のチップは別パッケージとして、実装ボード上でモジュール化してもよい。
図８では、オン抵抗を低減し、許容電流をアップするために、第１の電極１１と大電流通電配線である第１の配線層３１とを接続するための金属ビア４３を多数形成すると共に、第１の配線層３１を図８の左右両側へ櫛歯状に引き出し、第１のチップ１の第３の電極と同じ面側に形成する第２の配線層と接続するための金属ビア４１を第１のチップ横に多数形成する。金属ビア４１は第２の配線層３２（図示なし）に接続し、外部端子６０に電気的接続する。また、小電流／小電圧の第２の電極１２からの信号を少なくともひとつの金属ビア４３を形成し第１の配線層３１と接続し、第２のチップ横の金属ビア４２を用いて、第４の電極１４と同一面側の第３の配線層３３と接続する。 (8th Embodiment)
An eighth embodiment is shown in FIG.
FIG. 8 shows a vertical structure in which the semiconductor device shown in FIG. 1 has a first electrode 11 and a second electrode 12 on the front surface thereof and a third electrode on the back surface thereof as one first chip 1. When a power element is used, the pattern of the wiring layer of the first wiring layer 31 and the metal on the first chip 1, the metal via 41 beside the first chip, the first electrode 11, and the second electrode 12. An example of the layout of the via 43, the metal via 42 next to the second chip that electrically connects the second electrode 12 and the second chip is shown. The second chip laminated in FIG. 1 is not shown in FIG. Further, the second chip may be modularized on the mounting board as a separate package.
In FIG. 8, in order to reduce the on-resistance and increase the allowable current, a large number of metal vias 43 for connecting the first electrode 11 and the first wiring layer 31 which is a large current current-carrying wiring are formed. , The metal via 41 for pulling out the first wiring layer 31 to the left and right sides of FIG. 8 in a comb-tooth shape and connecting to the second wiring layer formed on the same surface side as the third electrode of the first chip 1. Is formed on the side of the first chip. The metal via 41 is connected to the second wiring layer 32 (not shown) and electrically connected to the external terminal 60. Further, the signal from the second electrode 12 having a small current / small voltage is connected to the first wiring layer 31 by forming at least one metal via 43, and the metal via 42 beside the second chip is used to form a second metal via. It is connected to the third wiring layer 33 on the same surface side as the electrode 14 of 4.

第１のチップ１内を縦方向に通電する大電流は、第１のチップ１の外側の通電経路の抵抗が低い領域に偏る。このため、第１の電極１１と接続される第１のチップ横の金属ビア４１の配置を、第１の電極１１に対して対称の位置に設ける。金属ビア４１の配置を、第１の電極１１に対して対称の位置に設ない場合には第１のチップ１内の通電経路がビアを設けた側に偏るのに対して、このように対称の位置に設けた場合には第１のチップ１内の通電領域の偏りを低減することができる。また、第１のチップ１内の通電面積を大きくすることにより実質的な第１のチップ１のオン抵抗を下げることができる。さらに、大電流が通電する第１の配線層を複数に分割し、隣接する第１の配線に通電する電流の向きを逆にすることにより、周囲の電磁場が打ち消され、インダクタンスや電磁場ノイズを低減することができる。 The large current that energizes the inside of the first chip 1 in the vertical direction is biased to the region where the resistance of the energization path outside the first chip 1 is low. Therefore, the arrangement of the metal via 41 on the side of the first chip connected to the first electrode 11 is provided at a position symmetrical with respect to the first electrode 11. When the arrangement of the metal via 41 is not provided at a position symmetrical with respect to the first electrode 11, the energization path in the first chip 1 is biased to the side where the via is provided, whereas it is symmetrical in this way. When it is provided at the position of, it is possible to reduce the bias of the energized region in the first chip 1. Further, by increasing the energization area in the first chip 1, the on-resistance of the first chip 1 can be substantially reduced. Furthermore, by dividing the first wiring layer to which a large current is energized into a plurality of layers and reversing the direction of the current energizing the adjacent first wiring, the surrounding electromagnetic field is canceled and the inductance and the electromagnetic field noise are reduced. can do.

第１のチップ１が片面にのみ電極を持つ横型構造の場合には、チップ横のビアを形成せずに、第１の配線層３１と同一層、もしくは多層配線層を介して外部端子に電気的接続すると、第１のチップ１のサイズにより近いパッケージ外形となり、小型化ができる。 When the first chip 1 has a horizontal structure having electrodes on only one side, electricity is supplied to the external terminal via the same layer as the first wiring layer 31 or a multilayer wiring layer without forming vias on the side of the chip. When the target is connected, the package outer shape is closer to the size of the first chip 1, and the size can be reduced.

（第９の実施形態）
第９の実施形態を図９示す。
図９は、図１に示した半導体装置において、表裏に電極をもつ縦型構造の第１のチップ１を２つ使用する場合における、第１の配線層３１の配線パターンと、第１のチップ１、第１のチップ横の金属ビア４１、第１の電極１１及び第２の電極１２上の金属ビア４３、第２のチップ２、第２のチップ２横の金属ビア４２のレイアウトの例を示したものである。
第１のチップ１の第１の電極１１と第１の配線層３１とを金属ビア４３を介して電気的に接続し、第１の配線層３１は、第１のチップ横の金属ビア４１を介して第２の配線層３２（図示なし）に接続し、多層に形成した第２の配線層、もしくは単一層の第２の配線層３２を介して、外部端子６０に電気的に接続している。 (9th embodiment)
A ninth embodiment is shown in FIG.
FIG. 9 shows the wiring pattern of the first wiring layer 31 and the first chip when two first chips 1 having a vertical structure having electrodes on the front and back surfaces are used in the semiconductor device shown in FIG. 1. An example of the layout of the metal via 41 beside the first chip, the metal via 43 on the first electrode 11 and the second electrode 12, the second chip 2, and the metal via 42 beside the second chip 2. It is shown.
The first electrode 11 of the first chip 1 and the first wiring layer 31 are electrically connected via the metal via 43, and the first wiring layer 31 has a metal via 41 beside the first chip. It is connected to the second wiring layer 32 (not shown) via the second wiring layer 32 (not shown), and is electrically connected to the external terminal 60 via the second wiring layer formed in multiple layers or the second wiring layer 32 of a single layer. There is.

制御ＩＣなどの小電流／小電圧の第２のチップ２を、第１のチップ１の第２の電極１２と接続した第１の配線層３１を覆う第２の封止体５２上に配置する。第２の電極１２に金属ビア４３を介して電気的に接続された第１の配線層３１は、上側へ接続される第２の封止体５２および第４の封止体内５３に形成した金属ビア４２を介して、第３の配線層３３に電気的に接続されている。なお、図９には第３の電極１３側に形成する第２の配線層３２や、第２のチップ２の第４の電極１４側に形成する第４の配線は図示していない。 A small current / small voltage second chip 2 such as a control IC is placed on a second encapsulant 52 that covers the first wiring layer 31 connected to the second electrode 12 of the first chip 1. .. The first wiring layer 31 electrically connected to the second electrode 12 via the metal via 43 is a metal formed in the second sealing body 52 and the fourth sealing body 53 connected to the upper side. It is electrically connected to the third wiring layer 33 via the via 42. Note that FIG. 9 does not show the second wiring layer 32 formed on the third electrode 13 side and the fourth wiring formed on the fourth electrode 14 side of the second chip 2.

このように配置すると、第２の電極１２からの信号は小電流／小電圧の電気信号であり、第２の電極１２と接続された第１の配線を覆う第２の封止体５２上に配置された第２のチップ２は大電流通電配線と近接していないので、より耐電圧性、耐リーク性、耐ノイズ性が確保できる。
パッケージ設計の際、図４に示した半導体装置のように、第４の配線層３４を設ける場合においても、第２のチップ２や小電流／小電圧の第４の配線層３４の配置は、大電流／大電圧の第１の電極１１からビア接続された第１の配線層３１の領域以外に配置するのが望ましいが、パッケージ外形、配線制約等を考慮して、第２の封止体５２（Ａ）ａ、第２の封止体（Ｂ）５２ｂを設けることにより、第２の封止体（Ａ）５２ａ上に第４の配線層３４を設け、第２の封止体（Ｂ）５２ｂ上に第２のチップ２を設けることができる。 When arranged in this way, the signal from the second electrode 12 is a small current / small voltage electrical signal on the second encapsulation 52 that covers the first wiring connected to the second electrode 12. Since the arranged second chip 2 is not in close proximity to the large current energization wiring, more withstand voltage resistance, leakage resistance, and noise resistance can be ensured.
When designing the package, even when the fourth wiring layer 34 is provided as in the semiconductor device shown in FIG. 4, the arrangement of the second chip 2 and the small current / small voltage fourth wiring layer 34 is not applicable. It is desirable to dispose of it in a region other than the region of the first wiring layer 31 via a via connection from the first electrode 11 having a large current / large voltage, but in consideration of the package outer shape, wiring restrictions, etc., the second encapsulation body By providing 52 (A) a and the second sealing body (B) 52b, the fourth wiring layer 34 is provided on the second sealing body (A) 52a, and the second sealing body (B) is provided. ) The second chip 2 can be provided on 52b.

なお、図９における第２の配線層３２（図示なし）については、第１の電極１１から第１の配線層３１と第１のチップ横の金属ビア４１とを介して左右２つの第１のチップ１を接続する第２の配線層３２の結線と、外部端子に接続する第２の配線層３２の結線がある。つまり、第１のチップ１の大電流通電経路を直列に接続する場合は、図右の第１のチップ１に対して、外部端子から第２の配線層３２を介して図右の第１のチップ１の第３の電極１３へ結線され、図右の第１のチップ１内をとおり、その第１の電極１１に接続された第１の配線層３１を図右の第１のチップ１の左横の金属ビア４１を介して、第２の配線層３２に電気的に接続し、外部端子及び図左の第２のチップの第３の電極１３に電気的に接続している。さらに図左の第１のチップ１内をとおり、その第１の電極１１、金属ビア４３、第１の配線層３１、図左の第１のチップ１の左横の金属ビア４１を介して第２の配線層３２に接続し、外部端子に至る大電流通電の経路となる。大電流通電のＯＮ／ＯＦＦは左右の第１のチップそれぞれの第２の電極に金属ビア４２を介して印加される第２のチップの信号により制御する。 Regarding the second wiring layer 32 (not shown) in FIG. 9, the first left and right two first wiring layers 31 are passed through the first wiring layer 31 and the metal via 41 beside the first chip from the first electrode 11. There is a connection of the second wiring layer 32 connecting the chip 1 and a connection of the second wiring layer 32 connecting to the external terminal. That is, when the large current energization path of the first chip 1 is connected in series, the first chip 1 on the right of the figure is connected to the first chip 1 on the right of the figure via the second wiring layer 32 from the external terminal. The first wiring layer 31 which is connected to the third electrode 13 of the chip 1, passes through the first chip 1 on the right side of the figure, and is connected to the first electrode 11 thereof is attached to the first chip 1 on the right side of the figure. It is electrically connected to the second wiring layer 32 via the metal via 41 on the left side, and is electrically connected to the external terminal and the third electrode 13 of the second chip on the left side of the figure. Further, it passes through the first chip 1 on the left side of the figure, passes through the first electrode 11, the metal via 43, the first wiring layer 31, and the metal via 41 on the left side of the first chip 1 on the left side of the figure. It is connected to the wiring layer 32 of No. 2 and serves as a path for energizing a large current to an external terminal. The ON / OFF of the large current energization is controlled by the signal of the second chip applied to the second electrodes of the left and right first chips via the metal via 42.

図１０Ａに示した回路図は位置指令に基づいてモータ制御を行うための回路の一例である。また、図１０Ａに示すように、ゲート制御ＩＣ２０１ともう一組のＭＯＳＦＥＴを含んだ回路２００の構成をモジュール化（ワンパッケージ化）し、位置アンプ２０２、ポテンショメータ２０３、モータ２０４及び電源、グラウンド用の外部端子を設け、電気的に接続しモータの制御回路を形成することもできる。
図１０Ｂ、Ｃ、Ｅに示したものは、パワー回路部をパッケージ化したものと制御回路部をパッケージ化したものを中間基板２０８を用いてモジュール化し実装ボード２０７に実装したものである。
図１０Ｂ、Ｃには実装ボード２０７にパワー回路部２０５と制御回路部２０６が実装されている状態を示す。 The circuit diagram shown in FIG. 10A is an example of a circuit for performing motor control based on a position command. Further, as shown in FIG. 10A, the configuration of the circuit 200 including the gate control IC 201 and another set of MOSFETs is modularized (one package), and is used for the position amplifier 202, the potentiometer 203, the motor 204, the power supply, and the ground. It is also possible to provide an external terminal and electrically connect it to form a motor control circuit.
In FIGS. 10B, C, and E, a packaged power circuit unit and a packaged control circuit unit are modularized using the intermediate board 208 and mounted on the mounting board 207.
10B and C show a state in which the power circuit unit 205 and the control circuit unit 206 are mounted on the mounting board 207.

前記パワー回路部２０５としては、図５Ａ、図５Ｂに示したような、制御回路部を有さず、パワー素子と、該パワー素子及びその周辺を封止する封止材とを含む第１の封止体と、第１の封止体上に設けた第１の配線層と、該第１の配線層を封止する封止材とを含む、第１の封止体上に設けた第２の封止体とからなるものであって、制御回路部と電気的に接続することが可能な端子を形成したものを用いることができる。 The power circuit unit 205 does not have a control circuit unit as shown in FIGS. 5A and 5B, and includes a power element and a sealing material for sealing the power element and its surroundings. A first provided on a first encapsulation body comprising an encapsulant, a first wiring layer provided on the first encapsulating body, and a encapsulant for encapsulating the first wiring layer. It is possible to use the one made of the sealing body of No. 2 and having a terminal formed so as to be electrically connected to the control circuit unit.

また、図５Ａの第２の封止体（Ｂ）５２ｂ側、図５Ｂの第２の封止体５２側も放熱ゲルのような接着材でヒートスプレッダ、ヒートパイプや筐体等の冷却体に接着することにより、パワー回路部２０５の上下両面からの放熱が可能となり、放熱性が向上することができる。その際、漏電等を防止すれば、図５Ａの第２の封止体（Ｂ）５２ｂ、図５Ｂの第２の封止体５２側も配線層を露出させる等してもよい。図１のような積層構造の場合でも複数の金属ビア４２を介して表層となる第３の配線層３３に接続し、好ましくは第３の配線層３３を大面積で形成することにより、同様にパッケージ両面への放熱により熱特性が向上する。 Further, the second sealing body (B) 52b side in FIG. 5A and the second sealing body 52 side in FIG. 5B are also adhered to a cooling body such as a heat spreader, a heat pipe, or a housing with an adhesive such as heat dissipation gel. By doing so, heat can be dissipated from both the upper and lower sides of the power circuit unit 205, and heat dissipation can be improved. At that time, if leakage or the like is prevented, the wiring layer may be exposed on the second sealing body (B) 52b of FIG. 5A and the second sealing body 52 side of FIG. 5B. Even in the case of the laminated structure as shown in FIG. 1, by connecting to the third wiring layer 33 which is the surface layer via a plurality of metal vias 42, preferably, the third wiring layer 33 is formed in a large area in the same manner. Thermal characteristics are improved by heat dissipation to both sides of the package.

図１０Ｂに、第１のチップ１であるパワー素子（例えば逆電流防止用のダイオードを同一チップ内に形成したＭＯＳＦＥＴ）４つをそれぞれパッケージ化したパッケージ２０５と、第２のチップ２である制御素子をパッケージ化したパッケージ２０６とを、中間基板２０８を用いてモジュール化し、このモジュールを実装ボード２０７に実装した例を示す。
図９は一組のＭＯＳＦＥＴと１つの第２のチップ２をワンパッケージ化した場合であったが、図１０Ｃに、第２のチップ２を別パッケージ２０６とし、中間基板２０８に用いてモジュール化し、実装ボード２０７に実装した例を示す。
図１０Ｄに、第１のチップ１であるパワー素子を二つ直列に接続したものを二組並列に配置し、例えば第２のチップ２である制御素子と配線及び金属ビアを介してそれぞれの第１のチップ１上の計４つの第２の電極（ゲート）と電気接続しワンパッケージ化した半導体装置を直接実装ボード２０７に実装したものを示す。
図１０Ｅに、４つのパワー素子１をそれぞれパッケージ化したパッケージ２０５と１つの制御素子パッケージ化したパッケージ２０６とを、直接実装ボード２０７に実装した例を示す。
本発明は、上記したような、第１のチップを含むパッケージ２０５と第２のチップを含むパッケージとを中間基板２０８でモジュール化したもの(図１０Ｂ、１０Ｃ)、パワー回路部と制御回路部とをワンパッケージ化したもの(図１０Ｄ)、パワー素子をパッケージ化したもの（図１０Ｅに示すようなパワー回路部（パッケージ２０５）を実施形態として含む。
なお、ダイオードはパワー素子とは別素子であってもよく、その場合、パワー素子と同じパッケージに内蔵されていても、別に実装されていてもよい。 In FIG. 10B, a package 205 in which four power elements (for example, MOSFETs in which a diode for preventing reverse current is formed in the same chip), which is the first chip 1, are packaged, and a control element, which is the second chip 2, are shown. An example is shown in which the package 206 in which the above is packaged is modularized by using the intermediate board 208, and this module is mounted on the mounting board 207.
FIG. 9 shows a case where a set of MOSFETs and one second chip 2 are packaged in one package. However, in FIG. 10C, the second chip 2 is used as a separate package 206 and used as an intermediate board 208 for modularization. An example of mounting on the mounting board 207 is shown.
In FIG. 10D, two sets of power elements, which are the first chips 1 connected in series, are arranged in parallel, and for example, the control elements, which are the second chips 2, and the respective first chips via wiring and metal vias. A semiconductor device that is electrically connected to a total of four second electrodes (gates) on chip 1 and packaged in one package is directly mounted on a mounting board 207.
FIG. 10E shows an example in which a package 205 in which four power elements 1 are packaged and a package 206 in which one control element is packaged are directly mounted on a mounting board 207.
In the present invention, as described above, the package 205 including the first chip and the package containing the second chip are modularized by the intermediate substrate 208 (FIGS. 10B and 10C), and the power circuit unit and the control circuit unit are included. (FIG. 10D) and a package of power elements (power circuit unit (package 205) as shown in FIG. 10E) are included as embodiments.
The diode may be a separate element from the power element, and in that case, it may be built in the same package as the power element or may be mounted separately.

図１０Ａに示されるようにパワー素子は複数個用いられて回路を形成される。高耐圧で、小型化・薄型化可能な半導体装置であることの利点は、例えば、図１０Ａに示すように、ＭＯＳＦＥＴ（パワー素子）、及び制ゲート御ＩＣを個々にパッケージ化し、実装ボード上に設置してモジュール化しても、個々のパーケージが、図１６及び図１７に示すようにワイヤボンディングで接続する場合より、金属ビア４１を近接させ小型化・薄型化が可能であり、回路全体を小型、薄化型化できる。 As shown in FIG. 10A, a plurality of power elements are used to form a circuit. The advantage of being a semiconductor device that has high withstand voltage and can be made smaller and thinner is that, for example, as shown in FIG. 10A, MOSFETs (power elements) and gate control ICs are individually packaged and mounted on a mounting board. Even if it is installed and modularized, the metal vias 41 can be made closer and smaller and thinner than when the individual packages are connected by wire bonding as shown in FIGS. 16 and 17, and the entire circuit can be made smaller. , Can be thinned.

さらに複数の素子をワンパッケージ化すると、パッケージ内に結線する配線が封止されるため、マイグレーション等の生成物によるリーク電流を防止できるため、より耐圧長寿命化が狙える。その際、複数のパワー素子を第１の封止体５１内に設けると、大電流／大電圧が許容できる比較的厚い配線としては、第１の封止体５１の上方にある第１の配線層３１及び第１の封止体５１の下方にある第２の配線層３２のみ形成すればよい。
このパワー素子を直列に接続した基本構成とゲート制御ＩＣとの構成は、ＤＣ－ＤＣコンバータや、モータ制御用回路等に用いられ、ワンパッケージ化する素子の組み合わせ・数量は、設計制約等により逐次決定し、薄型化、小サイズ化が図れる。 Furthermore, if a plurality of elements are packaged in one package, the wiring connected in the package is sealed, so that leakage current due to products such as migration can be prevented, and the withstand voltage and life can be further extended. At that time, if a plurality of power elements are provided in the first sealing body 51, the first wiring above the first sealing body 51 is a relatively thick wiring that can tolerate a large current / large voltage. Only the second wiring layer 32 below the layer 31 and the first encapsulant 51 may be formed.
The basic configuration in which these power elements are connected in series and the configuration of the gate control IC are used in DC-DC converters, motor control circuits, etc., and the combination and quantity of elements to be packaged in one package are sequentially determined due to design restrictions, etc. It can be decided to make it thinner and smaller.

（半導体装置の製造方法）
第１の実施形態に係る半導体装置の製造方法について以下述べる。
＜第１のチップ及び支持体の準備工程（図１１Ａ参照）＞
図１１においては、パネルに多面付けされた製品単位の内、１つの製品単位部分の製造工程を示している。第１の電極１１、第２電極１２及び第３の電極１３を有する第１のチップ１と、第１のチップ１を支持するための支持体１０１と、第１のチップ１を支持体１０１に搭載するための接着材３を準備する。図１２Ａに示すように支持体１０１は、表面に応力緩和層１１６及び接着層１１７を介して銅箔キャリア１２１と極薄銅箔１２０とからなる銅箔キャリア付き極薄銅箔１１８を貼り付けて形成される。支持体１０１は、パネルに剛性を与え製造工程流動中の反り防止の役割を果たす。 (Manufacturing method of semiconductor device)
The method for manufacturing a semiconductor device according to the first embodiment will be described below.
<Preparation step of first chip and support (see FIG. 11A)>
FIG. 11 shows the manufacturing process of one product unit part among the product units mounted on the panel. A first chip 1 having a first electrode 11, a second electrode 12, and a third electrode 13, a support 101 for supporting the first chip 1, and a first chip 1 on the support 101. The adhesive material 3 for mounting is prepared. As shown in FIG. 12A, the support 101 has an ultra-thin copper foil 118 with a copper foil carrier, which is composed of a copper foil carrier 121 and an ultra-thin copper foil 120, attached to the surface thereof via a stress relaxation layer 116 and an adhesive layer 117. It is formed. The support 101 imparts rigidity to the panel and plays a role of preventing warpage during the flow in the manufacturing process.

前記応力緩和層について説明する。一般に金属と樹脂とでは熱膨張係数に大きな差があるため、支持体として金属基板を用いた半導体パッケージの製造工程においては、金属基板と半導体素子を封止する樹脂との間における熱膨張係数の差に起因して内部応力が発生し、封止体に反りが発生する。応力緩和層の役割は、平板１１５の物性値と第１の封止体５１の物性値との差に起因する内部応力（支持体１０１と第１の封止体５１との境界面に生じる応力）を低減することである。そのため、応力緩和層１１６としては、平板１１５及び第１の封止体５１の弾性率より小さい弾性率を有する絶縁層を用いることが望ましい。 The stress relaxation layer will be described. In general, there is a large difference in the coefficient of thermal expansion between metal and resin. Therefore, in the process of manufacturing a semiconductor package using a metal substrate as a support, the coefficient of thermal expansion between the metal substrate and the resin that seals the semiconductor element is Internal stress is generated due to the difference, and the sealed body is warped. The role of the stress relaxation layer is the internal stress caused by the difference between the physical property value of the flat plate 115 and the physical property value of the first sealing body 51 (stress generated at the interface between the support 101 and the first sealing body 51). ) Is to be reduced. Therefore, as the stress relaxation layer 116, it is desirable to use an insulating layer having an elastic modulus smaller than the elastic modulus of the flat plate 115 and the first sealing body 51.

具体的には、同一温度条件下で、平板１１５の弾性率をＡ、応力緩和層１１６の弾性率をＢ、第１の封止体５１の弾性率をＣとした場合、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂが成り立つように、平板１１５、応力緩和層１１６及び第１の封止体５１の組み合わせを決定すればよい。 Specifically, when the elastic modulus of the flat plate 115 is A, the elastic modulus of the stress relaxation layer 116 is B, and the elastic modulus of the first sealant 51 is C under the same temperature condition, A> C> B. Alternatively, the combination of the flat plate 115, the stress relaxation layer 116, and the first sealing body 51 may be determined so that C> A> B holds.

このように応力緩和層１１６は、低弾性であることが望ましい。例えば、約２５℃（室温）の温度領域で２ＧＰａ以下、かつ、１００℃を超える温度領域で１００ＭＰａ以下の弾性率を有することが望ましい。それぞれの温度領域において弾性率に上限を設けた理由は、それら上限値を超えると応力緩和層１１６が硬すぎて応力緩和層としての機能が落ちてしまうからである。 As described above, it is desirable that the stress relaxation layer 116 has low elasticity. For example, it is desirable to have an elastic modulus of 2 GPa or less in a temperature range of about 25 ° C. (room temperature) and 100 MPa or less in a temperature range exceeding 100 ° C. The reason why the upper limit of the elastic modulus is set in each temperature region is that the stress relaxation layer 116 is too hard and its function as a stress relaxation layer deteriorates when the upper limit is exceeded.

すなわち、室温においては、ある程度の硬さがあっても（弾性率が高くても）応力緩和層１１６として十分機能するため、応力緩和層１１６の弾性率は、少なくとも２ＧＰａ以下であればよい。一方、熱硬化性樹脂の硬化温度（１７０℃前後）付近など、１００℃を超える温度領域（望ましくは１５０℃を超える温度領域）においては、応力緩和層１１６の弾性率を１００ＭＰａ以下とする。そのような高温域で１００ＭＰａを上回ると、応力緩和層としての機能を果たせなくなる虞があるからである。 That is, at room temperature, the stress relaxation layer 116 may have an elastic modulus of at least 2 GPa or less because it sufficiently functions as the stress relaxation layer 116 even if it has a certain degree of hardness (even if it has a high elastic modulus). On the other hand, in a temperature region exceeding 100 ° C. (preferably a temperature region exceeding 150 ° C.) such as near the curing temperature (around 170 ° C.) of the thermosetting resin, the elastic modulus of the stress relaxation layer 116 is set to 100 MPa or less. This is because if it exceeds 100 MPa in such a high temperature range, it may not function as a stress relaxation layer.

なお、弾性率が低ければ低いほど応力緩和層としての機能は高くなるが、あまりにも弾性率が低すぎると流動性が極端に高くなり、もはや層としての形状を維持できなくなる虞がある。したがつて、室温から２６０℃（リフロー温度）の範囲内において形状を維持できる範囲の弾性率であることが条件となる。また、応力緩和層１１６として、上述した弾性率の関係を満たす絶縁層を用いた場合、結果的に、同一温度条件下で、平板１１５の線膨張係数をａ、応力緩和層の線膨張係数をｂ、第１の封止体５１の線膨張係数をｃとすると、ａ≦ｃ＜ｂ（又は、ａ≒ｃ＜ｂ）が成り立つ。一般的に、金属基板の線膨張係数は、２０ｐｐｍ／℃程度であり、第１の封止体５１の線膨張係数は、数十ｐｐｍ／℃程度である。そのため、本実施形態に係る半導体装置では、２００℃以下の温度領域において、線膨張係数が１００～２００ｐｐｍ／℃、望ましくは１００～１５０ｐｐｍ／℃である絶縁層を用いる。なお、２００℃以下の温度領域という条件は、半導体装置の製造工程における上限温度が２００℃前後であることに因る。少なくとも半導体装置の製造工程中において、線膨張係数が前述の範囲に収まることが望ましいという趣旨である。 The lower the elastic modulus, the higher the function as a stress relaxation layer, but if the elastic modulus is too low, the fluidity becomes extremely high, and there is a possibility that the shape as a layer can no longer be maintained. Therefore, it is a condition that the elastic modulus is in the range where the shape can be maintained within the range of room temperature to 260 ° C. (reflow temperature). Further, when an insulating layer satisfying the above-mentioned elastic modulus relationship is used as the stress relaxation layer 116, as a result, the linear expansion coefficient of the flat plate 115 is set to a and the linear expansion coefficient of the stress relaxation layer is set to a. b. Assuming that the linear expansion coefficient of the first sealing body 51 is c, a ≦ c <b (or a≈c <b) holds. Generally, the linear expansion coefficient of the metal substrate is about 20 ppm / ° C., and the linear expansion coefficient of the first encapsulant 51 is about several tens of ppm / ° C. Therefore, in the semiconductor device according to the present embodiment, an insulating layer having a linear expansion coefficient of 100 to 200 ppm / ° C., preferably 100 to 150 ppm / ° C. is used in a temperature region of 200 ° C. or lower. The condition of the temperature range of 200 ° C. or lower is due to the fact that the upper limit temperature in the manufacturing process of the semiconductor device is around 200 ° C. At least during the manufacturing process of the semiconductor device, it is desirable that the linear expansion coefficient falls within the above-mentioned range.

さらに、本発明の実施形態に係る半導体装置では、応力緩和層として、５％質量減少温度が３００℃以上である接着材を用いることが望ましい。この条件は、一般的なリフロー温度が２６０℃前後であるため、リフロー処理を経ても質量減少の少ない絶縁層（すなわち、リフロー耐性のある絶縁層）を用いることにより、半導体装置の信頼性の低下を防ぐためである。なお、「質量減少温度」とは、物質の耐熱性を示すために用いられる指標の一つであり、窒素ガスや空気を流しながら、室温から徐々に微量の物質を加熱していき、一定の質量減少が起きる温度で示す。ここでは、５％の質量減少が起きる温度を示している。 Further, in the semiconductor device according to the embodiment of the present invention, it is desirable to use an adhesive having a 5% mass reduction temperature of 300 ° C. or higher as the stress relaxation layer. Under this condition, since the general reflow temperature is around 260 ° C., the reliability of the semiconductor device is lowered by using an insulating layer (that is, an insulating layer having reflow resistance) whose mass loss is small even after reflow processing. This is to prevent. The "mass reduction temperature" is one of the indexes used to show the heat resistance of a substance, and a small amount of the substance is gradually heated from room temperature while flowing nitrogen gas or air to keep it constant. Shown by the temperature at which mass loss occurs. Here, the temperature at which the mass loss of 5% occurs is shown.

さらに、応力緩和層１１６として、平板１１５（鉄合金や銅合金等の代表的な金属材料で構成される基板）と第１の封止体５１（エポキシ系、フェノール系またはポリイミド系などの樹脂）の双方に対して、ＪＩＳの碁盤目テープ試験（旧ＪＩＳＫ５４００）において「分類０」に分類される密着力を有する樹脂を用いることが望ましい。これにより、平板と第１の封止体５１との聞の密着性を高め、さらに第１の封止体５１の膜剥がれを抑制することができる。 Further, as the stress relaxation layer 116, a flat plate 115 (a substrate made of a typical metal material such as an iron alloy or a copper alloy) and a first sealant 51 (a resin such as an epoxy-based, phenol-based or polyimide-based resin) are used. It is desirable to use a resin having an adhesive force classified as "Category 0" in the JIS grid tape test (formerly JIS K5400). As a result, the adhesion between the flat plate and the first sealing body 51 can be improved, and the film peeling of the first sealing body 51 can be suppressed.

上記のように、応力緩和層として、（１）同一温度条件下で、平板１１５の弾性率をＡ、応力緩和層１１６の弾性率をＢ、第１の５１封止体の弾性率をＣとした場合、Ａ＞Ｃ＞Ｂ若しくはＣ＞Ａ＞Ｂが成り立つこと、（２）同一温度条件下で、平板１１５の線膨張係数をａ、応力緩和層の線膨張係数をｂ、第１の封止体５１の線膨張係数をｃとした場合、ａ≦ｃ＜ｂ（又は、ａ≒ｃ＜ｂ）が成り立つこと、の少なくともいずれか１つ（望ましくは全て）を満たすことが好ましい。これにより、平板１１５と第１の封止体５１との間の物性値の差に起因する内部応力の発生を低減し、平板１１５や第１の封止体５１に極力反りを発生させないようにすることができる。
なお、応力緩和層１１６に関しては、特願２０１４－１２５９８２号（半導体パッケージ及びその製造方法）を参考にすることができる。 As described above, as the stress relaxation layer, (1) the elastic modulus of the flat plate 115 is A, the elastic modulus of the stress relaxation layer 116 is B, and the elastic modulus of the first 51 encapsulation is C under the same temperature condition. If so, A>C> B or C>A> B holds, (2) under the same temperature conditions, the linear expansion coefficient of the flat plate 115 is a, the linear expansion coefficient of the stress relaxation layer is b, and the first seal. When the linear expansion coefficient of the stationary body 51 is c, it is preferable that at least one (preferably all) of a ≦ c <b (or a≈c <b) is satisfied. As a result, the generation of internal stress due to the difference in the physical property values between the flat plate 115 and the first sealing body 51 is reduced, and the flat plate 115 and the first sealing body 51 are prevented from being warped as much as possible. can do.
Regarding the stress relaxation layer 116, Japanese Patent Application No. 2014-125982 (semiconductor package and its manufacturing method) can be referred to.

平板１１５は、樹脂硬化体又はステンレススチール、４２アロイ、銅、銅合金等の金属板を用い、サイズとしてはプリント配線板のワークサイズを適用し、例えば４００ｍｍ×５００ｍｍ、５００ｍｍ×６００ｍｍなどを用いることができる。従来のウェハレベルパッケージングに対し、大面積のパネル状態で製造工程を流動させることで生産効率が高まり、低コスト化が可能となる。前記銅箔キャリア付き極薄銅箔１１８の上下向きは、製品側が１．５μｍ～５μｍの極薄銅箔となるようにする。銅箔キャリア付き極薄銅箔１１８としては、プリント配線板のＭＳＡＰ（Ｍｏｄｉｆｉｅｄ Ｓｅｍｉ Ａｄｄｉｔｉｖｅ Ｐｒｏｃｅｓｓ）回路形用やコアレス基板の製造用途として広く使われている市販品を用いることができる。 For the flat plate 115, a hardened resin or a metal plate such as stainless steel, 42 alloy, copper, or copper alloy is used, and the work size of the printed wiring board is applied as the size, for example, 400 mm × 500 mm, 500 mm × 600 mm, or the like is used. Can be done. Compared to the conventional wafer level packaging, the production efficiency can be improved and the cost can be reduced by flowing the manufacturing process in a panel state with a large area. The vertical orientation of the ultrathin copper foil 118 with a copper foil carrier is such that the product side is an ultrathin copper foil having a thickness of 1.5 μm to 5 μm. As the ultrathin copper foil 118 with a copper foil carrier, a commercially available product widely used for MSAP (Modified Semi Adaptive Process) circuit type of printed wiring boards and for manufacturing coreless substrates can be used.

なお、製造工程を流動中に銅箔キャリア付き極薄銅箔１１８が剥がれるのを防止するために、銅箔キャリア付き極薄銅箔１１８のサイズを平板１１５、接着層１１７及び第１の封止体５１より小サイズとし、銅箔キャリア１２１と極薄銅箔１２０の境界端部を前記接着層１１７及び前記第１の封止体５１で被覆保護することができる。 In order to prevent the ultra-thin copper foil 118 with a copper foil carrier from peeling off during the flow in the manufacturing process, the size of the ultra-thin copper foil 118 with a copper foil carrier is set to the flat plate 115, the adhesive layer 117, and the first sealing. The size is smaller than that of the body 51, and the boundary end between the copper foil carrier 121 and the ultrathin copper foil 120 can be covered and protected by the adhesive layer 117 and the first sealing body 51.

後述する図１１Ｌに示されるように支持体１０１は製品から剥離される。なお、銅箔キャリア１２１と極薄銅箔１２０とからなる銅箔キャリア付き極薄銅箔１１８は支持体１０１を構成する部材であるが、支持体１０１を剥離する際には極薄銅箔は製品側に残され、次いでエッチングして除去される。 As shown in FIG. 11L described later, the support 101 is peeled off from the product. The ultra-thin copper foil 118 with a copper foil carrier composed of the copper foil carrier 121 and the ultra-thin copper foil 120 is a member constituting the support 101, but when the support 101 is peeled off, the ultra-thin copper foil is used. It is left on the product side and then etched and removed.

また、この応力緩和層１１６は支持体１０１の一部を構成して製造工程途中で第１の封止体５１から剥離されてもよく、半導体装置の製品側に残されてもよい。
応力緩和層１１６が製造工程途中で第１の封止体５１から剥離される場合は、応力緩和層１１６は製造工程中における半導体装置の反りを抑制するものである。この場合、支持体１０１を剥離した後における半導体装置の反り抑制の役割は、図１で示す半導体装置の場合には、第１のチップに対して支持体１０１と逆側の表面にある第４の封止体５３が、また、図５で示す半導体装置の場合には、第２の封止体５２（５２ａ及び５２ｂ）がそれぞれ反り調整層として機能することによって担う。 Further, the stress relaxation layer 116 may form a part of the support 101 and may be peeled off from the first sealing body 51 during the manufacturing process, or may be left on the product side of the semiconductor device.
When the stress relaxation layer 116 is peeled off from the first sealing body 51 during the manufacturing process, the stress relaxation layer 116 suppresses the warp of the semiconductor device during the manufacturing process. In this case, in the case of the semiconductor device shown in FIG. 1, the role of suppressing the warp of the semiconductor device after the support 101 is peeled off is the fourth on the surface opposite to the support 101 with respect to the first chip. In the case of the semiconductor device shown in FIG. 5, the second sealing body 52 (52a and 52b) functions as a warp adjusting layer, respectively.

支持体１０１を剥離する際には、図１２ＢのＡからＢの点線部分でパネルを切断し、銅箔キャリア１２１と極薄銅箔１２０の境界端部を再び露出させることで、支持体１０１の剥離は容易となる。さらに、工程能力を高める等の目的で製造工程途中でパネルを分割、切断する場合がある。このような場合には、銅箔キャリア付き極薄銅箔の剥がれ防止策として、図１２Ｃに示すように、切断部分（図１２ＣのＣからＤの点線部分）の銅箔キャリア付き極薄銅箔１１８を銅箔キャリア１２１の厚み方向の途中までハーフエンチングを行い銅箔キャリア付き極薄銅箔１１８に溝１２２を形成し、この溝１２２に第１の封止体５１を充填する。第１の封止体５１が充填されることで、パネルを分割、切断した後の銅箔キャリア１２１と極薄銅箔１２０の境界端部を前記第１の封止体５１によって被覆保護することができる。支持体１０１を剥離する際には、図１２ＣのＥからＦ、Ｅ’からＦ’の点線部分でパネルを切断し、銅箔キャリア１２１と極薄銅箔１２０の境界端部を再び露出させることで、支持体１０１の剥離が容易となる。 When the support 101 is peeled off, the panel is cut at the dotted lines from A to B in FIG. 12B, and the boundary end between the copper foil carrier 121 and the ultrathin copper foil 120 is exposed again to expose the support 101. Peeling is easy. Further, the panel may be divided or cut in the middle of the manufacturing process for the purpose of enhancing the process capability. In such a case, as a measure to prevent the ultra-thin copper foil with a copper foil carrier from peeling off, as shown in FIG. 12C, the ultra-thin copper foil with a copper foil carrier at the cut portion (the dotted line portion from C to D in FIG. 12C). The 118 is half-enched halfway in the thickness direction of the copper foil carrier 121 to form a groove 122 in the ultrathin copper foil 118 with a copper foil carrier, and the groove 122 is filled with the first sealing body 51. By filling the first sealing body 51, the boundary end portion between the copper foil carrier 121 and the ultrathin copper foil 120 after the panel is divided and cut is covered and protected by the first sealing body 51. Can be done. When the support 101 is peeled off, the panel is cut at the dotted lines from E to F and E'to F'in FIG. 12C to expose the boundary end between the copper foil carrier 121 and the ultrathin copper foil 120 again. Therefore, the support 101 can be easily peeled off.

次に図１１Ａに示すように極薄銅箔１２０上にセミアディティブ工法によって金属配線層１０２を形成する。セミアディティブ工法に限定されるものではないが、極薄銅箔１２０を電解銅めっきのシード層として使えることや、回路形成のファイン化に適している点などから、当該工法を適用するのが好ましい。 Next, as shown in FIG. 11A, the metal wiring layer 102 is formed on the ultrathin copper foil 120 by a semi-additive method. Although not limited to the semi-additive method, it is preferable to apply the method because the ultrathin copper foil 120 can be used as a seed layer for electrolytic copper plating and is suitable for finer circuit formation. ..

既に述べたように、第１のチップ１と接着材３との熱膨張ミスマッチを緩和する効果及び接着材３の耐エッチング液性の効果が得られるように、図１３Ａに示すように、金属配線層１０２上に前記第１の封止体５１を形成する前に第６の封止体６１を形成してもよい。また既に述べたように、放熱性を良好にするために、図１３Ｂで示すように金属配線層１０２を第１のチップ１の領域に形成し、第１のチップ１を導電材１０３でダイアタッチしてもよい。または、第１のチップ１を表裏面を逆に搭載して、第１の電極１１及び第２の電極１２を非導電性樹脂を予め設置したフリップチップボンディング（Ｎｏｎ Ｃｏｎｄｕｃｔｉｖｅ ＦｉｌｍまたはＰａｓｔｅ Ｆｌｉｐ－Ｃｈｉｐ Ｂｏｎｄｉｎｇ）により第２の配線層と接続してもよい。
これらの場合には、第２の配線層を金属薄膜配線１０２で兼ねることもできる。 As described above, as shown in FIG. 13A, the metal wiring has the effect of alleviating the thermal expansion mismatch between the first chip 1 and the adhesive material 3 and the effect of the etching solution resistance of the adhesive material 3. A sixth encapsulant 61 may be formed before the first encapsulant 51 is formed on the layer 102. Further, as already described, in order to improve heat dissipation, the metal wiring layer 102 is formed in the region of the first chip 1 as shown in FIG. 13B, and the first chip 1 is die-attached with the conductive material 103. You may. Alternatively, flip-chip bonding (Non Conductive Film or Paste Flip-Chip Bonding) in which the first chip 1 is mounted upside down and the first electrode 11 and the second electrode 12 are pre-installed with a non-conductive resin. ) May be connected to the second wiring layer.
In these cases, the second wiring layer can also be combined with the metal thin film wiring 102.

＜第１のチップの支持体への搭載工程（図１１Ｂ参照）＞
主面を上向きにした第１のチップ１を支持体１０１の表面に接着材３を介して搭載する。 <Step of mounting the first chip on the support (see FIG. 11B)>
The first chip 1 with the main surface facing upward is mounted on the surface of the support 101 via the adhesive material 3.

＜第１のチップの封止工程（図１１Ｃ参照）＞
第１のチップ及びそれらの周辺を層状の封止材で封止して第１の封止体５１を形成する。 <First chip sealing step (see FIG. 11C)>
The first chip and its periphery are sealed with a layered sealing material to form the first sealing body 51.

＜金属ビア用の開口を形成する工程（図１１Ｄ参照）＞
次に、第１の封止体５１に第１のチップ１の第１の電極１１及び第２の電極１２と第１の配線層３１とを接続する金属ビアを形成するための開口４３ａを形成する。また、同時に第１の配線層３１と第２の配線層３２とを接続する金属ビアを形成するための開口４１ａを形成する。開口形成には、Ｃ０２レーザー加工、ＵＶ一ＹＡＧレーザー加工等の従来技術を用いることができる。 <Step of forming an opening for a metal via (see FIG. 11D)>
Next, an opening 43a for forming a metal via connecting the first electrode 11 and the second electrode 12 of the first chip 1 and the first wiring layer 31 is formed in the first sealing body 51. do. At the same time, an opening 41a for forming a metal via connecting the first wiring layer 31 and the second wiring layer 32 is formed. Conventional techniques such as C02 laser processing and UV-YAG laser processing can be used for opening.

＜金属ビア形成工程（図１１Ｅ参照）＞
次に、セミアディティブ工法やＭＳＡＰ工法等の従来技術を用いて、開口４１ａ及び開口４３ａに金属ビア４１及び金属ビア４３を形成すると共に、第１の配線層３１を形成する。半導体装置を使用時、通電する最大電流仕様によりビアは導電材を充填したフィルドタイプや充填していないコンフォーマルタイプのビアを形成する。なお大電流通電ビアについては、導電材を充填したフィルドタイプのビアを形成しビア抵抗を低減するのが望ましい。 <Metal via forming process (see Fig. 11E)>
Next, the metal vias 41 and the metal vias 43 are formed in the openings 41a and 43a, and the first wiring layer 31 is formed by using conventional techniques such as the semi-additive method and the MSAP method. When using a semiconductor device, the vias form a filled type via filled with a conductive material or a conformal type via not filled with a conductive material depending on the maximum current specification to be energized. For large current energized vias, it is desirable to form a filled type via filled with a conductive material to reduce via resistance.

＜第２の封止体を形成する工程（図１１Ｆ参照）＞
次に、第１の配線層３１の上面及び側面を封止材で封止して第２の封止体５２を形成する。大電流通電配線が多層に及ぶ場合には、第２の封止体５２の形成、穴あけ加工、及び回路形成を繰り返すことで複数層からなる第２の封止体５２を形成することができる。例えば第２の封止体を図４に示したように５２ａ及び５２ｂからなる２層構成とすることができる。 <Step of forming the second sealed body (see FIG. 11F)>
Next, the upper surface and the side surface of the first wiring layer 31 are sealed with a sealing material to form the second sealing body 52. When the large-current energization wiring extends over multiple layers, the second encapsulation body 52 composed of a plurality of layers can be formed by repeating the formation of the second encapsulation body 52, the drilling process, and the circuit formation. For example, the second encapsulant can have a two-layer structure composed of 52a and 52b as shown in FIG.

＜第２のチップを搭載する工程（図１１Ｇ参照）＞
第２の封止体５２上に接着材３を用いて第２のチップ２を搭載する。本工程において用いる接着材としては、後述する図１１Ｎで示した工程におけるパターニング等処理条件が異なる場合、図１１Ａで用いた接着材と異なる材料を用いることができる。 <Process for mounting the second chip (see Fig. 11G)>
The second chip 2 is mounted on the second sealing body 52 by using the adhesive material 3. As the adhesive used in this step, a material different from the adhesive used in FIG. 11A can be used when the processing conditions such as patterning in the step shown in FIG. 11N, which will be described later, are different.

＜第４の封止体を形成し、開口を形成する工程（図１１Ｈ参照）＞
第２のチップ２及び第２の封止体５２の表面を封止材で封止して第４の封止体５３を形成する。 <Step of forming a fourth sealed body and forming an opening (see FIG. 11H)>
The surfaces of the second chip 2 and the second sealing body 52 are sealed with a sealing material to form the fourth sealing body 53.

＜金属ビア用の開口を形成する工程（図１１Ｉ参照）＞
図１１Ｄで示した工程と同様に、第４の封止体５３の表面から第２のチップ２の第４の電極１４にまで達する開口４４ａを形成する。また、第４の封止体５３の表面から第１の配線層３１まで達する開口４２ａを形成する。 <Step of forming an opening for a metal via (see FIG. 11I)>
Similar to the process shown in FIG. 11D, an opening 44a extending from the surface of the fourth sealing body 53 to the fourth electrode 14 of the second chip 2 is formed. Further, an opening 42a extending from the surface of the fourth sealing body 53 to the first wiring layer 31 is formed.

＜第３の配線層及び金属ビアを形成する工程（図１１Ｊ参照）＞
図１１Ｅに示した工程と同様に、第４の封止体５３の表面に第３の配線層３３を形成し、開口４２ａ及び開口４４ａに金属ビア４３及び金属ビア４４を形成する。 <Step of forming the third wiring layer and metal via (see FIG. 11J)>
Similar to the process shown in FIG. 11E, the third wiring layer 33 is formed on the surface of the fourth sealing body 53, and the metal vias 43 and the metal vias 44 are formed in the openings 42a and 44a.

＜第３の封止体を形成する工程（図１１Ｋ参照）＞
第３の配線層３３及び金属ビア４２、４４を封止材で封止して第５の封止体５４を形成する。第２のチップ２の第４の電極と接続される金属ビア４２、４４は、小電流／小電圧のみであれば、コンフォーマルタイプのビアであってもよく、第５の封止体５４でビアの中央分も充填する。以上により、第１の封止体５１、第２の封止体５２、第４の封止体５３及び第５の封止体５４からなる積層体を得る。
以下では上記積層体を絶縁材料層１３０ということがある。 <Step of forming a third sealed body (see FIG. 11K)>
The third wiring layer 33 and the metal vias 42 and 44 are sealed with a sealing material to form a fifth sealing body 54. The metal vias 42 and 44 connected to the fourth electrode of the second chip 2 may be conformal type vias as long as they have only a small current / small voltage, and the fifth sealant 54 may be used. Also fill the center of the via. As a result, a laminated body including the first sealing body 51, the second sealing body 52, the fourth sealing body 53, and the fifth sealing body 54 is obtained.
In the following, the laminate may be referred to as an insulating material layer 130.

＜支持体を分離する工程（図１１Ｌ、図１１Ｍ参照）＞
図１１Ｌに示すように、支持体１０１を前記絶縁材料層１３０から分離する。
図１１Ｍは支持体１０１を分離した後の状態を示す。支持体１０１は、平板１１５、応力緩和層１１６、銅箔キャリア１２１と極薄銅箔１２０とからなる銅箔キャリア付き極薄銅箔１１８で構成されるが、支持体１０１を剥離する際には銅箔キャリア１２１と極薄銅箔１２０との界面で分離し、極薄銅箔１２０は製品側に残され、次いでエッチングして除去される。また、銅箔キャリア１２１を第１のチップ１側にすることによって、銅箔キャリア１２１を製品側に残すこともできる。これにより、例えば、第１のチップ１を、導電材で比較的厚い銅箔キャリア１２１にダイアタッチし、支持体１０１を分離した後、銅箔キャリア１２１をエッチング等でパターニングすることにより、第２の配線層３２として用いることもできる。 <Step of separating the support (see FIGS. 11L and 11M)>
As shown in FIG. 11L, the support 101 is separated from the insulating material layer 130.
FIG. 11M shows a state after the support 101 is separated. The support 101 is composed of an ultra-thin copper foil 118 with a copper foil carrier composed of a flat plate 115, a stress relaxation layer 116, a copper foil carrier 121, and an ultra-thin copper foil 120. When the support 101 is peeled off, the support 101 is composed of an ultra-thin copper foil 118. Separated at the interface between the copper foil carrier 121 and the ultrathin copper foil 120, the ultrathin copper foil 120 is left on the product side and then etched and removed. Further, by setting the copper foil carrier 121 on the first chip 1 side, the copper foil carrier 121 can be left on the product side. Thereby, for example, the first chip 1 is die-attached to the copper foil carrier 121 which is relatively thick with a conductive material, the support 101 is separated, and then the copper foil carrier 121 is patterned by etching or the like. It can also be used as the wiring layer 32 of.

前述したように、第１の封止体５１、第２の封止体５２及び第４の封止体５３としては、ガラスクロスや不織布等の補強繊維を含まない熱硬化樹脂を用いる場合、支持体１０１はパネルに剛性を与え製造工程流動中の反り防止の役割を果たす。第１のチップ１を複数並べて配置するとパネルの剛性は向上するが、それでも支持体１０１を分離した後においては、製品部を形成する絶縁材料の種類、第１のチップ１（パワー素子）や第２のチップ２（制御Ｉ）の配置及び配置される層数、半導体装置の占める体積、銅箔部の面積比率（残同率）等に応じて一定の反りを示す。 As described above, when the first sealing body 51, the second sealing body 52, and the fourth sealing body 53 are supported by a thermosetting resin that does not contain reinforcing fibers such as glass cloth or non-woven fabric. The body 101 imparts rigidity to the panel and plays a role of preventing warpage during the flow in the manufacturing process. Although the rigidity of the panel is improved by arranging a plurality of the first chips 1 side by side, after the support 101 is separated, the type of insulating material forming the product part, the first chip 1 (power element) and the first chip 1 are still present. A constant warp is shown according to the arrangement of the chip 2 (control I) of 2 and the number of layers to be arranged, the volume occupied by the semiconductor device, the area ratio of the copper foil portion (residual ratio), and the like.

そこで、支持体１０１を分離する前に、支持体１０１とは反対側の表面に、製品部が示す反りの方向とは反対の方向の反りを示す層（以下、「反り調整層」という）を配置して製品部の反りを相殺し、もって半導体装置の反りを低減する。反り調整層は製品部との熱膨張係数のミスマッチによって反りを生じる層であり、例えば、図１の第５の封止体５４もしくは図５の第２の封止体（Ｂ）５２ｂのような単一の材料からなる層であっても良く、図２に示す電子部品を含む第４の封止体５３もしくは図７のアンダーフィル樹脂４であっても良い。具体的には、反り調整層は、絶縁樹脂からなる層又は１つないし複数の電子部品と該電子部品を封止する絶縁樹脂とからなる層が好ましい。反り調整層を第５の封止体５４もしくは図５の第２の封止体（Ｂ）５２ｂの単一の絶縁樹脂だけとする場合は、ゾルダーレジスト材料を適用してもよい。また、所望の物性値を得るなど樹脂組成物の設計の容易さを考えると、光硬化機構を用いない熱硬化型樹脂を適用するのが好ましい。熱硬化型の場合は、たとえば該樹脂を硬化させた後、レーザー直描や、銅箔またはドライフィルムをマスクにしてレーザー加工、ブラスト処理、過マンガン酸塩水溶液等でエッチングを行うことで所望のソルダーレジスト・パターンを形成することができる。 Therefore, before separating the support 101, a layer showing a warp in a direction opposite to the warp direction indicated by the product part (hereinafter referred to as "warp adjusting layer") is provided on the surface opposite to the support 101. By arranging it, the warp of the product part is offset, and the warp of the semiconductor device is reduced. The warp adjusting layer is a layer that causes warpage due to a mismatch in the coefficient of thermal expansion with the product portion, and is, for example, the fifth sealing body 54 in FIG. 1 or the second sealing body (B) 52b in FIG. It may be a layer made of a single material, or may be a fourth sealant 53 including the electronic component shown in FIG. 2 or the underfill resin 4 of FIG. 7. Specifically, the warp adjusting layer is preferably a layer made of an insulating resin or a layer made of one or a plurality of electronic components and an insulating resin that seals the electronic components. When the warp adjusting layer is only a single insulating resin of the fifth sealing body 54 or the second sealing body (B) 52b of FIG. 5, a zolder resist material may be applied. Further, considering the ease of designing the resin composition such as obtaining desired physical property values, it is preferable to apply a thermosetting resin that does not use a photocuring mechanism. In the case of the thermosetting type, for example, after curing the resin, it is desired to perform laser direct drawing, laser processing using a copper foil or a dry film as a mask, blasting, etching with a permanganate aqueous solution, or the like. A solder resist pattern can be formed.

また、例えば、第１のチップ１（パワー素子）を第１の封止体５１の１層に横に並べて搭載し、第２のチップ２（制御ＩＣ）を第４の封止体で封止した場合、図１０Ａの回路図で示すように、第１の封止体内に占めるチップ体積よりも、第４の封止体内に占めるチップ体積が小さくなる。従って、第１の封止体内に占める封止材の体積よりも第４の封止体内に占める封止材の体積が大きくなる。このため、反り調整層の材料としては、第４の封止体の成形後の硬化収縮、及び常温まで降温する際に生じる熱圧縮を相殺するように、第４の封止体より２００℃以下の温度領域における線膨張係数が小さい絶縁材料を用いるとよい。 Further, for example, the first chip 1 (power element) is mounted side by side on one layer of the first sealing body 51, and the second chip 2 (control IC) is sealed with the fourth sealing body. In this case, as shown in the circuit diagram of FIG. 10A, the chip volume occupied in the fourth encapsulation body is smaller than the chip volume occupied in the first encapsulation body. Therefore, the volume of the encapsulant in the fourth encapsulation is larger than the volume of the encapsulant in the first encapsulation. Therefore, as the material of the warp adjusting layer, the temperature is 200 ° C. or lower than that of the fourth sealed body so as to offset the curing shrinkage after molding of the fourth sealed body and the heat compression generated when the temperature is lowered to room temperature. It is preferable to use an insulating material having a small linear expansion coefficient in the temperature range of.

具体的には、例えば反り調整層として特定の絶縁樹脂からなる層を選択したとき、半導体装置の反りが低減されるように、絶縁材料層１３０の反りを調整するために、絶縁材料層１３０を形成する絶縁材料の種類、半導体素子の配置および配置する層数、半導体素子装置の占める体積率、銅箔部の面積比率（残銅率）等を設計することが考えられる。また、反り調整層として電子部品と該電子部品を封止する絶縁樹脂とからなる層を用いる場合には、絶縁材料層１３０の反りを相殺するように、絶縁材脂の種類、電子部品の配置及び電子部品の占める体積率等を設計することが考えられる。 Specifically, for example, when a layer made of a specific insulating resin is selected as the warp adjusting layer, the insulating material layer 130 is used to adjust the warp of the insulating material layer 130 so that the warp of the semiconductor device is reduced. It is conceivable to design the type of insulating material to be formed, the arrangement of semiconductor elements and the number of layers to be arranged, the volume ratio occupied by the semiconductor element device, the area ratio of the copper foil portion (residual copper ratio), and the like. Further, when a layer composed of an electronic component and an insulating resin for sealing the electronic component is used as the warp adjusting layer, the type of insulating material fat and the arrangement of the electronic component are arranged so as to cancel the warp of the insulating material layer 130. It is also conceivable to design the volume fraction occupied by electronic components.

＜金属ビア用の開口を形成、第２の配線層及び金属ビアを形成する工程（図１１Ｎ参照）＞
支持体１０１を分離し、製品側に残された極薄銅箔をエッチング除去したのち、反り調整層により反りを低減した状態で、第１のチップ１の第３の電極１３と電気的に接続する金属ビアを形成するための開口を第１のチップ１を支持体１０１に固着するために使用された接着材層にＣ０２レーザー加工、ＵＶ一ＹＡＧレーザー加工等の従来技術を用いて形成する。その後、第３の電極と電気的接続するように、セミアディティブエ法やＭＳＡＰ工法等の従来のめっき技術を用いて、絶縁材料層１３０の裏面に第２の配線層３２を形成すると同時に第１のチップ１の第３の電極１３と第２の配線層３２とは金属ビア４７によって接続する。 <Step of forming an opening for a metal via and forming a second wiring layer and a metal via (see FIG. 11N)>
After separating the support 101 and removing the ultrathin copper foil left on the product side by etching, it is electrically connected to the third electrode 13 of the first chip 1 in a state where the warp is reduced by the warp adjusting layer. An opening for forming a metal via is formed in the adhesive layer used for fixing the first chip 1 to the support 101 by using conventional techniques such as C02 laser processing and UV-1 YAG laser processing. .. After that, the second wiring layer 32 is formed on the back surface of the insulating material layer 130 by using conventional plating techniques such as the semi-additive method and the MSAP method so as to be electrically connected to the third electrode, and at the same time, the first one is formed. The third electrode 13 of the chip 1 and the second wiring layer 32 are connected by a metal via 47.

また、反り緩和層の効果と例えば図８もしくは図９で示したような比較的厚く広範囲に及んだ第１の配線層のパターンと第２の配線層で複数の第１のチップ１を挟んだ構造により、剛性を確保し、反りを抑制することができる。 Further, the effect of the warp mitigation layer and the pattern of the first wiring layer that is relatively thick and widespread as shown in FIG. 8 or 9, for example, and the second wiring layer sandwich the plurality of first chips 1. However, due to the structure, rigidity can be ensured and warpage can be suppressed.

ここまで第１のチップ１を、表面に第１の電極１１と第２の電極１２を有し、裏面側に第３の電極１３を有するように配置した場合を例に挙げて説明した。しかしながら、ここで説明したパターニングされた第２の配線層３２と金属ビア４７を介して第１のチップ１上の電極と電気的接続を得ることは、第１のチップ１の表裏面の電極数には無関係にできるため、第１のチップ１の表裏には限定されず、前記の第１のチップ１の表裏を逆にして、裏面に第１の電極１１と第２の電極１２を有し、表面に第３の電極１３を有するように配置してもよい。この場合には、第１の電極１１と第２の電極１２を有している側の第１の封止体と接している封止体が第１の封止体上に設けた第２の封止体となる。 Up to this point, the case where the first chip 1 is arranged so as to have the first electrode 11 and the second electrode 12 on the front surface and the third electrode 13 on the back surface side has been described as an example. However, obtaining an electrical connection with the electrodes on the first chip 1 via the patterned second wiring layer 32 and the metal via 47 described here is the number of electrodes on the front and back surfaces of the first chip 1. The first electrode 11 and the second electrode 12 are provided on the back surface of the first chip 1 with the front and back sides reversed, without being limited to the front and back surfaces of the first chip 1. , May be arranged to have a third electrode 13 on the surface. In this case, the encapsulant in contact with the first encapsulant on the side having the first electrode 11 and the second electrode 12 is provided on the first encapsulant. It becomes a sealed body.

＜配線保護層を形成する工程（図１１Ｏ参照）＞
第２の配線層３２上に配線保護層（ソルダーレジスト層）として第３の封止体５５を形成し、外部端子用開口６０ａを形成する。なお、この例では、外部端子６０ａを第１のチップ１の第１の電極１１と逆面側の第３の電極１３側に形成する例を示したが、第２の配線層３２は、電気的接続のみの用途で用い、外部端子６０を第１のチップ１の第１の電極１１と同じ面側に形成してもよく、その場合、外部端子は第５の封止体５４の形成時や、図５の第２の封止体（Ｂ）５２ｂの形成時に外部端子用の開口を設け、外部端子を形成してもよく、導通経路によるオン抵抗、放熱経路によるパッケージ熱抵抗、外部端子数等を考慮し、外部端子を配置する。
支持体１０１を分離した後の金属配線層（第２の配線層３２）及び配線保護層（第３の封止体５５）等は、層上に形成するため、１５０℃以下の比較的低温で形成し、熱収縮量を抑え、反りを低減することが望ましい。 <Step of forming the wiring protection layer (see Fig. 11O)>
A third sealant 55 is formed on the second wiring layer 32 as a wiring protection layer (solder resist layer), and an opening 60a for an external terminal is formed. In this example, an example is shown in which the external terminal 60a is formed on the third electrode 13 side opposite to the first electrode 11 of the first chip 1, but the second wiring layer 32 is electrically connected. The external terminal 60 may be formed on the same surface side as the first electrode 11 of the first chip 1, and the external terminal may be formed at the time of forming the fifth sealing body 54. Alternatively, an opening for an external terminal may be provided at the time of forming the second sealing body (B) 52b in FIG. 5, and an external terminal may be formed. Arrange external terminals in consideration of the number.
Since the metal wiring layer (second wiring layer 32), the wiring protection layer (third sealing body 55), and the like after separating the support 101 are formed on the layer, they are formed at a relatively low temperature of 150 ° C. or lower. It is desirable to form, suppress the amount of heat shrinkage, and reduce warpage.

＜外部端子を形成する工程（図１１Ｐ参照）＞
開口６０ａ内の第２の配線層３２にめっき膜を形成して外部端子６０を形成する。必要に応じて、はんだボール等を形成してもよい。次に、ブレード等で個片化することにより、本発明の第１の実施形態による半導体装置を得る。 <Step of forming an external terminal (see FIG. 11P)>
A plating film is formed on the second wiring layer 32 in the opening 60a to form the external terminal 60. If necessary, solder balls or the like may be formed. Next, the semiconductor device according to the first embodiment of the present invention is obtained by individualizing with a blade or the like.

なお、上記では図１に示される第１の実施形態の半導体装置の製造方法について述べたが、他の実施形態の半導体装置の製造は、上記第１の実施形態の半導体装置の製造方法の工程を省略したり、応用することにより当業者であれば容易になし得る。 Although the method for manufacturing the semiconductor device according to the first embodiment shown in FIG. 1 has been described above, the manufacturing of the semiconductor device according to another embodiment is the process of the method for manufacturing the semiconductor device according to the first embodiment. Can be easily done by a person skilled in the art by omitting or applying the above.

例えば、第２の封止体５２及び第４の封止体５３をそれぞれ複数設けることにより、複数個の第1のチップ１を複数の第２の封止体のそれぞれに配置し、第２のチップ２を複数の第４の封止体のそれぞれに配置することができる。
図１４に示した例は、二つの第１のチップ１を第1の封止体（Ａ）５１ａ中に配置し、第１の封止体（Ａ）５１ａの上に第１の配線（Ａ）３１ａを配置し、他の二つの第１のチップ１を第１の封止体（Ｂ）５１ｂ中に配置したものである。そして、第１の封止体（Ｂ）５１ｂの上に第１の配線層（Ｂ）３１ｂを封止材で封止した第２の封止体５２を積層し、この第２の封止体５２上に第２のチップ２を封止した第４の封止体５３を積層し、この第４の封止体５３上に第３の配線層３３を封止した第５の封止体５４を積層する。 For example, by providing a plurality of the second sealing body 52 and the fourth sealing body 53, the plurality of first chips 1 are arranged in each of the plurality of second sealing bodies, and the second The chip 2 can be placed in each of the plurality of fourth encapsulants.
In the example shown in FIG. 14, two first chips 1 are arranged in the first sealing body (A) 51a, and the first wiring (A) is placed on the first sealing body (A) 51a. ) 31a is arranged, and the other two first chips 1 are arranged in the first sealing body (B) 51b. Then, a second sealing body 52 in which the first wiring layer (B) 31b is sealed with a sealing material is laminated on the first sealing body (B) 51b, and the second sealing body is formed. A fourth sealing body 53 in which the second chip 2 is sealed is laminated on the 52, and a fifth sealing body 54 in which the third wiring layer 33 is sealed on the fourth sealing body 53. Are laminated.

また、上記ではパワー素子として、一方の面にソース電極とゲート電極を、また、他方の面にドレイン電極を配置し、ソース電極からドレイン電極に垂直方向に通電する縦型構造のものについて実施形態を説明した。
しかしながら、本発明は、ソース電極とドレイン電極とゲート電極とが同一面に配置され、ソース電極からドレイン電極に水平方向に通電する横型構造のものについても適用可能である。 Further, in the above, as a power element, an embodiment having a vertical structure in which a source electrode and a gate electrode are arranged on one surface and a drain electrode is arranged on the other surface and electricity is supplied from the source electrode to the drain electrode in a vertical direction is provided. Explained.
However, the present invention is also applicable to a horizontal structure in which the source electrode, the drain electrode, and the gate electrode are arranged on the same surface and the source electrode to the drain electrode are electrically energized in the horizontal direction.

図１５Ａに示すものは、二つの横型構造のパワー素子１を第１の封止体５１内に封止したものである。パワー素子１は一方の面にソース電極１１ａ、ドレイン電極１１ｂ及びゲート電極１２を有しており、その裏面にはバックメタル層７０が設けられている。
図に示すように電流はドレイン電極１１ｂ側からパワー素子内を通ってソース電極１１ａ側に流れ、第１の配線層３１及び金属ビア４１を通って外部端子６０に流れる。
図１５Ａに示したものでは、バックメタル層７０には金属ビア４７が接触しており、金属ビア４７は放熱経路を形成している What is shown in FIG. 15A is one in which two power elements 1 having a horizontal structure are sealed in a first sealing body 51. The power element 1 has a source electrode 11a, a drain electrode 11b, and a gate electrode 12 on one surface thereof, and a back metal layer 70 is provided on the back surface thereof.
As shown in the figure, the current flows from the drain electrode 11b side through the power element to the source electrode 11a side, and flows to the external terminal 60 through the first wiring layer 31 and the metal via 41.
In the one shown in FIG. 15A, the metal via 47 is in contact with the back metal layer 70, and the metal via 47 forms a heat dissipation path.

また、図１５Ｂに示したものは、図１５Ａに示したものにおいて、バックメタル層７０に導電材１０３を接触させたものであり、導電材１０３は放熱経路を形成している。 Further, in the one shown in FIG. 15B, in the one shown in FIG. 15A, the conductive material 103 is brought into contact with the back metal layer 70, and the conductive material 103 forms a heat dissipation path.

このように、ガラスクロスや不織布等の補強繊維を含まない熱硬化樹脂を封止体に用いると、付随する第１の配線層３１のファイン化、前記金属ビアの小径化、及び層間厚の薄化ができるため、高密度配線が可能となり、層数低減の効果等半導体装置の小型・薄型化が可能となる。また、大電流通電配線を封止する第１の封止体５１、第２の封止体５２、金属ビア及び金属配線層１０２を逐次積層によって行い多層化でき、第１のチップ１の複数層への配置も第１の封止体５１、第２の封止体５２の多層化、第２のチップ２の複数層への配置も封止する第４の封止体５３、第５の封止体５４、配線層を逐次積層できるので、任意の単数又は複数層面に任意の数のパワー素子、制御素子を搭載することが可能である。配線設計の自由度が増すほか、支持体１０１の剛性付与機能が、工程途中で反り調整層および第１の配線層／第１のチップ／第２の配線層の剛性へと引き継がれることにより、製造バンクエンドエ程中の流動品及び完成品の反り特性は低下することなく維持され、反り対策として残銅率等とのバランス設計が可能となる。
また、前記した本実施形態にかかる半導体装置の構造及び製造方法を採用することにより、前記図１０Ａに示したような回路に限らず、汎用性のある回路設計が可能となる。 As described above, when a thermosetting resin containing no reinforcing fiber such as glass cloth or non-woven fabric is used for the sealing body, the accompanying first wiring layer 31 is refined, the diameter of the metal via is reduced, and the interlayer thickness is reduced. Therefore, high-density wiring becomes possible, and semiconductor devices can be made smaller and thinner, such as the effect of reducing the number of layers. Further, the first encapsulating body 51, the second encapsulating body 52, the metal vias and the metal wiring layer 102 for encapsulating the large current current-carrying wiring can be sequentially laminated to form a multilayer, and a plurality of layers of the first chip 1 can be formed. The fourth sealer 53 and the fifth seal are arranged in the first sealer 51, the second sealer 52 is multi-layered, and the second chip 2 is arranged in multiple layers. Since the stop body 54 and the wiring layer can be sequentially laminated, it is possible to mount an arbitrary number of power elements and control elements on an arbitrary single or multiple layer surface. In addition to increasing the degree of freedom in wiring design, the rigidity imparting function of the support 101 is taken over by the rigidity of the warp adjusting layer and the first wiring layer / first chip / second wiring layer in the middle of the process. The warpage characteristics of fluid products and finished products in the manufacturing bank end process are maintained without deterioration, and it is possible to design a balance with the residual copper ratio, etc. as a countermeasure against warpage.
Further, by adopting the structure and manufacturing method of the semiconductor device according to the present embodiment described above, not only the circuit as shown in FIG. 10A but also a versatile circuit design becomes possible.

１ 第１のチップ（パワー素子）
２ 第２のチップ（制御素子）
３ 接着材
４ アンダーフィル樹脂
１１ 第１の電極（ソース電極）
１１ａ ソース電極
１１ｂ ドレイン電極
１２ 第２の電極（ゲート電極）
１３ 第３の電極（ドレイン電極）
１４ 第４の電極
２１ ボンディングワイヤ
２２、２３ 接続用ランド
３１ 第１の配線層
３１ａ 第１の配線（Ａ）、大電流通電配線
３１ｂ 第１の配線（Ｂ）、小電流通電配線
３２ 第２の配線層
３３ 第３の配線層
３４ 第４の配線層
４１、４２、４３、４４、４５ａ、４５ｂ、４６、４７ 金属ビア
４１ａ、４２ａ、４３ａ、４４ａ ビア用開口
５１ 第１の封止体
５２ 第２の封止体
５２ａ 第２の封止体（Ａ）
５２ｂ 第２の封止体（Ｂ）
５３ 第４の封止体
５４ 第５の封止体
５５ 第３の封止体（ソルダーレジスト層）
６０ 外部端子
６０ａ 外部端子用開口
６１ 第６の封止体
７０ バックメタル
１００ ２００ 半導体装置（パワーモジュール）
１０１ 支持体
１０２ 金属配線層
１０３ 導電材
１１５ 平板
１１６ 応力緩和層
１１７ 接着層
１１８ 銅箔キャリア付き極薄銅箔
１２０ 極薄銅箔
１２１ 銅箔キャリア
１２２ 銅箔キャリア付き極薄銅箔の溝
１３０ 絶縁材料層
２００ ゲート制御ＩＣとＭＯＳＦＥＴを含む回路
２０１ ゲート制御ＩＣ
２０２ 位置アンプ
２０３ ポテンショメータ
２０４ モータ
２０５ パワー回路部、パッケージ
２０６ 制御回路部、ッケージ
２０７ 実装ボード
２０８ 中間基板
Ｃ１ 大電圧の電気的接続
Ｃ２ 小電圧の電気的接続
Ｓ１ 第１チップの主面
Ｓ２ 第１チップの裏面
Ｓ３ 第１チップの側面
ｄ１、ｄ２ 間隔 1 First chip (power element)
2 Second chip (control element)
3 Adhesive 4 Underfill resin 11 First electrode (source electrode)
11a Source electrode 11b Drain electrode 12 Second electrode (gate electrode)
13 Third electrode (drain electrode)
14 Fourth electrode 21 Bonding wire 22, 23 Connection land
31 First wiring layer 31a First wiring (A), large current energization wiring 31b First wiring (B), small current energization wiring 32 Second wiring layer 33 Third wiring layer 34 Fourth wiring layer 41, 42, 43, 44, 45a, 45b, 46, 47 Metal vias 41a, 42a, 43a, 44a Via openings 51 First sealant 52 Second sealant 52a Second sealer (A) )
52b Second sealant (B)
53 Fourth encapsulant 54 Fifth encapsulant 55 Third encapsulant (solder resist layer)
60 External terminal 60a Opening for external terminal 61 Sixth sealant 70 Back metal 100 200 Semiconductor device (power module)
101 Support 102 Metal wiring layer 103 Conductive material 115 Flat plate 116 Stress relaxation layer 117 Adhesive layer 118 Ultra-thin copper foil with copper foil carrier 120 Ultra-thin copper foil 121 Copper foil carrier 122 Ultra-thin copper foil groove 130 with copper foil carrier Insulation Material layer 200 Circuit including gate control IC and MOSFET 201 Gate control IC
202 Position amplifier 203 Potentiometer 204 Motor 205 Power circuit section, Package 206 Control circuit section, Package 207 Mounting board 208 Intermediate board C1 High voltage electrical connection C2 Low voltage electrical connection S1 Main surface of 1st chip S2 1st chip Back side of S3 1st chip side surface d1, d2 spacing

Claims (26)

少なくとも１つのパワー素子を備えたパワー回路部を含んだ半導体装置であって、
前記パワー素子は、前記パワー素子の表面上に大電流通電用又は大電圧印加用の第１の電極と小電圧印加用の第２の電極とを有し、
前記パワー素子と、該パワー素子及びその周辺を封止する封止材とを含む第１の封止体と、
前記第１の封止体上に設けた第１の配線層と、該第１の配線層を封止する封止材とを含む、前記第１の封止体上に設けた第２の封止体と、
前記パワー素子の裏面側の前記第１の封止体側に設けた第２の配線層と、該第２の配線層を封止する封止材とを含む第３の封止体と、を含み、
前記第１の配線層は、前記パワー素子の前記第１の電極に金属ビアにより電気的に接続している第１の配線ａと、前記パワー素子の前記第２の電極と金属ビアにより電気的に接続している第１の配線ｂとを有し、
前記第１の配線ａは、前記第２の配線層が前記パワー素子の前記第１の電極に接続するように、前記第３の封止体の前記第２の配線層と前記第１の配線ａ及び前記第２の配線層の両方に接する金属ビアにより電気的に接続しており、
前記第３の封止体は、前記第２の配線層を露出する第１開口部を有し、前記第１の配線ａと前記第２の配線層とを接続する金属ビアは、前記第２の配線層の第１面で前記第２の配線層に接し、前記第１開口部は、前記第２の配線層における前記第１面と反対側の第２面を露出し、前記第１の開口部に隣接する前記第３の封止体の裏面側は、前記半導体装置の外面を含む、半導体装置。 A semiconductor device including a power circuit unit including at least one power element.
The power element has a first electrode for energizing a large current or applying a large voltage and a second electrode for applying a small voltage on the surface of the power element.
A first sealing body including the power element and a sealing material for sealing the power element and its surroundings, and
A second seal provided on the first sealant, comprising a first wiring layer provided on the first sealant and a sealant for sealing the first wiring layer. With a still body,
A second wiring layer provided on the first sealing body side on the back surface side of the power element, and a third sealing body including a sealing material for sealing the second wiring layer are included. ,
The first wiring layer is electrically connected to the first electrode of the power element by a first wiring a electrically connected to the first electrode of the power element by a metal via, and by the second electrode of the power element and a metal via. Has a first wire b connected to
The first wiring a is the second wiring layer of the third encapsulation and the first wiring so that the second wiring layer is connected to the first electrode of the power element. It is electrically connected by a metal via that is in contact with both a and the second wiring layer .
The third sealing body has a first opening that exposes the second wiring layer, and the metal via that connects the first wiring a and the second wiring layer is the second. The first surface of the wiring layer is in contact with the second wiring layer, and the first opening exposes the second surface of the second wiring layer opposite to the first surface. The back surface side of the third sealed body adjacent to the opening is a semiconductor device including an outer surface of the semiconductor device. 少なくとも１つのパワー素子を備えたパワー回路部と、少なくとも１つの制御素子を備えた制御回路部とを含んだ半導体装置であって、
前記パワー素子は、主面に大電流通電用又は大電圧印加用の第１の電極と小電圧印加用の第２の電極を有し、
前記制御素子は主面に第４の電極を有し、
前記パワー素子と、該パワー素子及びその周辺を封止する封止材とを含む第１の封止体と、
前記第１の封止体上に設けた第１の配線層と、該第１の配線層を封止する封止材とを含む、前記第１の封止体上に設けた第２の封止体と、
前記パワー素子の裏面側の前記第１の封止体側に設けた第２の配線層と、該第２の配線層を封止する封止材とを含む第３の封止体と、
前記第２の封止体上に配置された前記制御素子と、該制御素子及びその周辺を封止する封止材とを含む第４の封止体と、
前記第４の封止体上に設けた第３の配線層と、該第３の配線層を封止する封止材とを含む、前記第４の封止体上に設けた第５の封止体と、を含み、
前記第１の配線層は、前記パワー素子の前記第１の電極に金属ビアにより電気的に接続している第１の配線ａと、前記パワー素子の第２の電極に金属ビアにより電気的に接続している第１の配線ｂとを有し、
前記第３の配線層は前記制御素子の前記第４の電極と金属ビアにより電気的に接続されており、
前記第３の配線層と前記第１の配線ｂとは前記第４の封止体に設けた金属ビアを介して電気的に接続されている、半導体装置。 A semiconductor device including a power circuit unit including at least one power element and a control circuit unit including at least one control element.
The power element has a first electrode for energizing a large current or applying a large voltage and a second electrode for applying a small voltage on the main surface.
The control element has a fourth electrode on the main surface and has a fourth electrode.
A first sealing body including the power element and a sealing material for sealing the power element and its surroundings, and
A second seal provided on the first sealant, comprising a first wiring layer provided on the first sealant and a sealant for sealing the first wiring layer. With a still body,
A second wiring layer provided on the first sealing body side on the back surface side of the power element, and a third sealing body including a sealing material for sealing the second wiring layer.
A fourth sealing body including the control element arranged on the second sealing body and a sealing material for sealing the control element and its surroundings.
A fifth seal provided on the fourth sealant, including a third wiring layer provided on the fourth sealant and a sealant for sealing the third wiring layer. Including the stationary body,
The first wiring layer has a first wiring a electrically connected to the first electrode of the power element by a metal via and a metal via electrically connected to the second electrode of the power element. It has a first wiring b that is connected, and has
The third wiring layer is electrically connected to the fourth electrode of the control element by a metal via.
A semiconductor device in which the third wiring layer and the first wiring b are electrically connected via a metal via provided in the fourth sealing body. 前記第２の封止体の封止材がフィラーを含む請求項１または２に記載の半導体装置。 The semiconductor device according to claim 1 or 2, wherein the sealing material of the second sealing body contains a filler. 前記第２の封止体の封止材中のフィラーの含有量が７０質量％以上である請求項３に記載の半導体装置。 The semiconductor device according to claim 3, wherein the content of the filler in the sealing material of the second sealing body is 70% by mass or more. 前記フィラーの最大粒径が前記第２の封止体の厚さの２／３以下である請求項３又は４に記載の半導体装置。 The semiconductor device according to claim 3 or 4, wherein the maximum particle size of the filler is 2/3 or less of the thickness of the second encapsulant. 前記第２の封止体の厚みは２０μｍ以上であり、かつ前記第２の封止体の封止材の絶縁抵抗率が１０11Ω・ｃｍである、請求項１～５のいずれか１項に記載の半導体装置。 Any one of claims 1 to 5, wherein the thickness of the second encapsulant is 20 μm or more, and the insulating resistivity of the encapsulant of the second encapsulant is 10 11 Ω · cm. The semiconductor device described in. 前記第２の封止体内に前記第１の配線層が多層に形成されており、前記第１の配線ａ及び前記第１の配線ｂの両方の配線の一部又は一方の配線の一部が異なる配線層に設けられている、請求項１～６のいずれか１項に記載の半導体装置。 The first wiring layer is formed in multiple layers in the second sealing body, and a part of both wirings of the first wiring a and the first wiring b or a part of one wiring is formed. The semiconductor device according to any one of claims 1 to 6, which is provided in a different wiring layer. 前記パワー素子が裏面に第３の電極を有し、該第３の電極と前記第２の配線層との間に導電材を設けた、請求項１～７のいずれか１項に記載の半導体装置。 The semiconductor according to any one of claims 1 to 7, wherein the power element has a third electrode on the back surface and a conductive material is provided between the third electrode and the second wiring layer. Device. 前記導電材は複数の金属ビアである、請求項８に記載の半導体装置。 The semiconductor device according to claim 8, wherein the conductive material is a plurality of metal vias. 前記金属ビアの周りに前記第１の封止体の封止材の樹脂とは異なる樹脂を設けた、請求項９に記載の半導体装置。 The semiconductor device according to claim 9, wherein a resin different from the resin of the sealing material of the first sealing body is provided around the metal via. 前記パワー素子はＭＯＳＦＥＴであり、前記第１の電極がソース電極であり、前記第２の電極がゲート電極であり、前記第３の電極がドレイン電極である、請求項８～１０のいずれか１項に記載の半導体装置。 One of claims 8 to 10, wherein the power element is a MOSFET, the first electrode is a source electrode, the second electrode is a gate electrode, and the third electrode is a drain electrode. The semiconductor device described in the section. 少なくとも１つのパワー素子を備えたパワー回路部と、少なくとも１つの制御素子を備えた制御回路部とを含んだ半導体装置であって、
前記パワー素子は、主面に大電流通電用又は大電圧印加用の第１の電極と小電圧印加用の第２の電極を有し、
前記制御素子は主面に第４の電極を有し、
前記パワー素子と、該パワー素子及びその周辺を封止する封止材とを含む第１の封止体と、
前記第１の封止体上に設けた第１の配線層と、該第１の配線層を封止する封止材とを含む、前記第１の封止体上に設けた第２の封止体と、
前記パワー素子の裏面側の前記第１の封止体側に設けた第２の配線層と、該第２の配線層を封止する封止材とを含む第３の封止体と、
前記第２の封止体上に配置された前記制御素子と、該制御素子及びその周辺を封止する封止材とを含む第４の封止体と、を含み、
前記第１の配線層は、前記パワー素子の前記第１の電極に金属ビアにより電気的に接続している第１の配線ａと、前記パワー素子の第２の電極に金属ビアにより電気的に接続している第１の配線ｂとを有し、
前記制御素子は、前記パワー回路部上にワイヤボンディングにより前記第１の配線ｂと電気的に接続されている、半導体装置。 A semiconductor device including a power circuit unit including at least one power element and a control circuit unit including at least one control element.
The power element has a first electrode for energizing a large current or applying a large voltage and a second electrode for applying a small voltage on the main surface.
The control element has a fourth electrode on the main surface and has a fourth electrode.
A first sealing body including the power element and a sealing material for sealing the power element and its surroundings, and
A second seal provided on the first sealant, comprising a first wiring layer provided on the first sealant and a sealant for sealing the first wiring layer. With a still body,
A second wiring layer provided on the first sealing body side on the back surface side of the power element, and a third sealing body including a sealing material for sealing the second wiring layer.
A fourth encapsulant including the control element disposed on the second encapsulant and a encapsulant for encapsulating the control element and its surroundings.
The first wiring layer has a first wiring a electrically connected to the first electrode of the power element by a metal via and a metal via electrically connected to the second electrode of the power element. It has a first wiring b that is connected, and has
The control element is a semiconductor device that is electrically connected to the first wiring b on the power circuit unit by wire bonding. 少なくとも１つのパワー素子を備えたパワー回路部と、少なくとも１つの制御素子を備えた制御回路部とを含んだ半導体装置であって、
前記パワー素子は、主面に大電流通電用又は大電圧印加用の第１の電極と小電圧印加用の第２の電極を有し、
前記制御素子は主面に第４の電極を有し、
前記パワー素子と、該パワー素子及びその周辺を封止する封止材とを含む第１の封止体と、
前記第１の封止体上に設けた第１の配線層と、該第１の配線層を封止する封止材とを含む、前記第１の封止体上に設けた第２の封止体と、
前記パワー素子の裏面側の前記第１の封止体側に設けた第２の配線層と、該第２の配線層を封止する封止材とを含む第３の封止体と、
前記第２の封止体上に配置された前記制御素子と、を含み、
前記第１の配線層は、前記パワー素子の前記第１の電極に金属ビアにより電気的に接続している第１の配線ａと、前記パワー素子の第２の電極に金属ビアにより電気的に接続している第１の配線ｂとを有し、
前記制御素子は、前記パワー回路部上にフリップチップボンディングにより前記第１の配線ｂと電気的に接続され、アンダーフィル封止されている、半導体装置。 A semiconductor device including a power circuit unit including at least one power element and a control circuit unit including at least one control element.
The power element has a first electrode for energizing a large current or applying a large voltage and a second electrode for applying a small voltage on the main surface.
The control element has a fourth electrode on the main surface and has a fourth electrode.
A first sealing body including the power element and a sealing material for sealing the power element and its surroundings, and
A second seal provided on the first sealant, comprising a first wiring layer provided on the first sealant and a sealant for sealing the first wiring layer. With a still body,
A second wiring layer provided on the first sealing body side on the back surface side of the power element, and a third sealing body including a sealing material for sealing the second wiring layer.
The control element, which is arranged on the second sealing body, and the control element are included.
The first wiring layer has a first wiring a electrically connected to the first electrode of the power element by a metal via and a metal via electrically connected to the second electrode of the power element. It has a first wiring b that is connected, and has
A semiconductor device in which the control element is electrically connected to the first wiring b on the power circuit unit by flip-chip bonding and is underfill-sealed. 前記第２の封止体における封止材が補強繊維を含まない封止材である、請求項１または２に記載の半導体装置。 The semiconductor device according to claim 1 or 2, wherein the sealing material in the second sealing body is a sealing material that does not contain reinforcing fibers. 前記第１の封止体における封止材は補強繊維を含まない封止材であり、
前記第１の封止体とは反対側の前記第２の封止体の主面側に、前記第１の封止体の反りを相殺して、半導体装置の反りを低減する反り調整層を備えている、請求項１または２に記載の半導体装置。 The sealing material in the first sealing body is a sealing material that does not contain reinforcing fibers.
A warp adjusting layer that cancels the warp of the first encapsulation and reduces the warp of the semiconductor device is provided on the main surface side of the second encapsulation on the side opposite to the first encapsulation. The semiconductor device according to claim 1 or 2. 請求項１に記載の半導体装置の製造方法であって、
支持体の表面に少なくとも一つのパワー素子を搭載する工程と、
前記パワー素子を封止材によって封止して第１の封止体を得る工程と、
前記第１の封止体の表面から、パワー素子の電極に達する金属ビア用の開口を形成する工程と、
前記第１の封止体上に第１の配線層を形成すると共に金属ビアを形成する工程と、
前記第１の配線層を封止材によって封止して第２の封止体を得る工程と、
前記支持体を除去する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線層を形成する工程と、
前記第２の配線層を封止材によって封止して第３の封止体を得る工程と、
を含む、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1.
The process of mounting at least one power element on the surface of the support,
The step of sealing the power element with a sealing material to obtain a first sealing body, and
A step of forming an opening for a metal via that reaches the electrode of the power element from the surface of the first encapsulant.
The step of forming the first wiring layer and forming the metal via on the first sealing body, and
The step of sealing the first wiring layer with a sealing material to obtain a second sealing body, and
The step of removing the support and
A step of forming a second wiring layer on the back surface side of the sealed body that was in contact with the support, and
The step of sealing the second wiring layer with a sealing material to obtain a third sealing body, and
A method for manufacturing a semiconductor device, including. 請求項２に記載の半導体装置の製造方法であって、
支持体の表面に少なくとも一つのパワー素子を搭載する工程と、
前記パワー素子を封止材によって封止して第１の封止体を得る工程と、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程と、
前記第１の封止体上に第１の配線を形成すると共に金属ビアを形成する工程と、
前記第１の配線層を封止材によって封止して第２の封止体を得る工程と、
前記第２の封止体上に制御素子を搭載する工程と、
前記制御素子を封止材によって封止して第４の封止体を得る工程と、
前記第４の封止体の表面から、前記制御素子の電極に達する金属ビア用の開口と、前記第１の配線層に達する金属ビア用の開口とを形成する工程と、
前記第４の封止体上に第３の配線を形成すると共に金属ビアを形成する工程と、
前記第３の配線を封止材によって封止して第５の封止体を得る工程と、
前記支持体を除去する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線層を形成する工程と、
第２の配線層を封止材によって封止して第３の封止体を得る工程と、
を含む半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 2.
The process of mounting at least one power element on the surface of the support,
The step of sealing the power element with a sealing material to obtain a first sealing body, and
A step of forming an opening for a metal via from the surface of the first sealing body to reach the electrode of the power element, and
The step of forming the first wiring and forming the metal via on the first sealing body, and
The step of sealing the first wiring layer with a sealing material to obtain a second sealing body, and
The process of mounting the control element on the second sealing body and
The step of sealing the control element with a sealing material to obtain a fourth sealing body, and
A step of forming an opening for a metal via that reaches the electrode of the control element and an opening for a metal via that reaches the first wiring layer from the surface of the fourth sealing body.
The step of forming the third wiring and forming the metal via on the fourth sealing body, and
The step of sealing the third wiring with a sealing material to obtain a fifth sealing body, and
The step of removing the support and
A step of forming a second wiring layer on the back surface side of the sealed body that was in contact with the support, and
The process of sealing the second wiring layer with a sealing material to obtain a third sealing body, and
A method for manufacturing a semiconductor device including. 前記支持体の表面にパワー素子を搭載する工程の前に、前記支持体の表面に第６の封止体を形成する工程を有する、請求項１６又は１７に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 16 or 17, further comprising a step of forming a sixth encapsulation body on the surface of the support before the step of mounting the power element on the surface of the support. 前記支持体の表面にパワー素子を搭載する工程の前に、前記支持体の表面に金属配線層を形成する工程を含み、
前記パワー素子を封止材によって封止して第１の封止体を得る工程が、前記パワー素子と金属配線層とを封止材によって封止して第１の封止体を得る工程であり、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程が、前記パワー素子の電極に達する金属ビア用の開口を形成すると共に、金属薄膜配線層に達する金属ビア用の開口を形成する工程であり、
前記第１の封止体上に第１の配線を形成すると共に金属ビアを形成する工程が、第１の配線を形成すると共に前記パワー素子の電極に達する金属ビア及び金属薄膜配線層に達する金属ビアを形成する工程である、
請求項１６～１８のいずれか１項に記載の半導体装置の製造方法。 A step of forming a metal wiring layer on the surface of the support is included before the step of mounting the power element on the surface of the support.
The step of sealing the power element with a sealing material to obtain a first sealing body is a step of sealing the power element and the metal wiring layer with a sealing material to obtain a first sealing body. can be,
The step of forming an opening for a metal via that reaches the electrode of the power element from the surface of the first sealing body forms an opening for the metal via that reaches the electrode of the power element, and also forms a metal thin film wiring layer. Is the process of forming openings for metal vias that reach
The step of forming the first wiring and forming the metal via on the first sealing body forms the first wiring and the metal via that reaches the electrode of the power element and the metal that reaches the metal thin film wiring layer. The process of forming vias,
The method for manufacturing a semiconductor device according to any one of claims 16 to 18. 予め前記支持体の表面に応力緩和層を形成する工程を含む、請求項１６又は１７に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 16 or 17, further comprising a step of forming a stress relaxation layer on the surface of the support in advance. 前記支持体を除去する際に前記応力緩和層を同時に除去する、請求項２０に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 20, wherein the stress relaxation layer is simultaneously removed when the support is removed. 前記パワー素子が裏面に第３の電極を有しており、
前記支持体を除去した後に、
前記パワー素子の前記第３の電極に達する金属ビア用の開口を形成する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線を形成すると共に金属ビアを形成する工程と
を含む、請求項１６又は１７に記載の半導体装置の製造方法。 The power element has a third electrode on the back surface, and the power element has a third electrode on the back surface.
After removing the support
A step of forming an opening for a metal via that reaches the third electrode of the power element, and
The method for manufacturing a semiconductor device according to claim 16 or 17, comprising a step of forming a second wiring and forming a metal via on the back surface side of the sealed body that has been in contact with the support. 前記支持体の表面にパワー素子を搭載する工程が、支持体上に形成した金属配線層上に導電材を用いてパワー素子を搭載する工程である、請求項１９に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 19, wherein the step of mounting the power element on the surface of the support is a step of mounting the power element on a metal wiring layer formed on the support using a conductive material. .. 請求項１又は２に記載の半導体装置の製造方法であって、
支持体の表面にパワー素子を搭載する工程と、
前記パワー素子を補強繊維を含まない封止材によって封止して第１の封止体を得る工程と、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程と、
前記第１の封止体上に第１の配線を形成すると共に金属ビアを形成する工程と、
前記第１の配線を封止材によって封止して第２の封止体を得る工程と、
前記第２の封止体上に反り調整層を形成する工程と、
前記支持体を除去する工程と、
前記支持体と接触していた封止体の裏面側に第２の配線層を形成する工程と、
前記第２の配線層を封止材によって封止して第３の封止体を得る工程と
を含む、半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 1 or 2.
The process of mounting a power element on the surface of the support,
The step of sealing the power element with a sealing material containing no reinforcing fiber to obtain a first sealed body, and
A step of forming an opening for a metal via from the surface of the first sealing body to reach the electrode of the power element, and
The step of forming the first wiring and forming the metal via on the first sealing body, and
The step of sealing the first wiring with a sealing material to obtain a second sealing body, and
The step of forming the warp adjusting layer on the second sealing body and
The step of removing the support and
A step of forming a second wiring layer on the back surface side of the sealed body that was in contact with the support, and
A method for manufacturing a semiconductor device, which comprises a step of sealing the second wiring layer with a sealing material to obtain a third sealing body. 前記支持体の表面にパワー素子を搭載する工程の前に、前記支持体の表面に金属配線層を形成する工程を含み、
前記第１の封止体を得る工程が、前記パワー素子と前記金属配線層とを補強繊維を含まない封止材によって封止して第１の封止体を得る工程であり、
前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成する工程が、前記第１の封止体の表面から、前記パワー素子の電極に達する金属ビア用の開口を形成すると共に、前記金属配線層に達する金属ビア用の開口を形成する工程であり、
前記第１の封止体上に第１ の配線を形成すると共に金属ビアを形成する工程が、第１の配線を形成すると共にパワー素子の電極に達する金属ビア及び金属配線層に達する金属ビアを形成する工程である、請求項２４に記載の半導体装置の製造方法。 A step of forming a metal wiring layer on the surface of the support is included before the step of mounting the power element on the surface of the support.
The step of obtaining the first sealed body is a step of sealing the power element and the metal wiring layer with a sealing material containing no reinforcing fiber to obtain the first sealed body.
The step of forming an opening for a metal via that reaches the electrode of the power element from the surface of the first encapsulation body is for the metal via that reaches the electrode of the power element from the surface of the first encapsulation. This is a step of forming an opening for a metal via that reaches the metal wiring layer.
The step of forming the first wiring and forming the metal via on the first sealing body forms the first wiring and forms the metal via that reaches the electrode of the power element and the metal via that reaches the metal wiring layer. The method for manufacturing a semiconductor device according to claim 24, which is a step of forming. 前記支持体の表面に予め応力緩和層を形成する工程を含む、請求項２４又は２５に記載の半導体装置の製造方法。 The method for manufacturing a semiconductor device according to claim 24 or 25, which comprises a step of forming a stress relaxation layer on the surface of the support in advance.
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Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11750090B2 (en) 2019-02-01 2023-09-05 Mitsubishi Electric Corporation Semiconductor device and power conversion device
CN111627865B (en) * 2019-02-27 2022-06-14 恒劲科技股份有限公司 Semiconductor packaging structure and manufacturing method thereof
JP7080845B2 (en) 2019-03-20 2022-06-06 株式会社東芝 Semiconductor device
US20220344233A1 (en) * 2021-04-22 2022-10-27 Taiwan Semiconductor Manufacturing Company, Ltd. Stacked semiconductor device including a cooling structure
CN113540017B (en) * 2021-06-30 2024-04-09 佛山市国星光电股份有限公司 IGBT module packaging structure and manufacturing method thereof
WO2023162722A1 (en) * 2022-02-24 2023-08-31 ローム株式会社 Semiconductor device and semiconductor module
WO2023179845A1 (en) * 2022-03-22 2023-09-28 Huawei Digital Power Technologies Co., Ltd. Semiconductor power entity and method for producing such entity by hybrid bonding
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Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011249410A (en) 2010-05-24 2011-12-08 Denso Corp Semiconductor device
JP2012009602A (en) 2010-06-24 2012-01-12 Nec Corp Substrate incorporating integrated circuit element and integrated circuit element to be incorporated therein
JP2013069807A (en) 2011-09-21 2013-04-18 Shinko Electric Ind Co Ltd Semiconductor package and method for manufacturing the same
JP2013197258A5 (en) 2012-03-19 2015-03-05
JP2016039238A (en) 2014-08-07 2016-03-22 パナソニックＩｐマネジメント株式会社 Insulating resin sheet, and circuit board and semiconductor package that use the insulating resin sheet
JP2016058417A (en) 2014-09-05 2016-04-21 日本特殊陶業株式会社 Semiconductor power module manufacturing method
JP2016115711A (en) 2014-12-11 2016-06-23 株式会社ジェイデバイス Semiconductor package and manufacturing method of the same
US20160211221A1 (en) 2015-01-16 2016-07-21 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013197258A (en) * 2012-03-19 2013-09-30 Ngk Spark Plug Co Ltd Circuit board and manufacturing method for semiconductor module

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011249410A (en) 2010-05-24 2011-12-08 Denso Corp Semiconductor device
JP2012009602A (en) 2010-06-24 2012-01-12 Nec Corp Substrate incorporating integrated circuit element and integrated circuit element to be incorporated therein
JP2013069807A (en) 2011-09-21 2013-04-18 Shinko Electric Ind Co Ltd Semiconductor package and method for manufacturing the same
JP2013197258A5 (en) 2012-03-19 2015-03-05
JP2016039238A (en) 2014-08-07 2016-03-22 パナソニックＩｐマネジメント株式会社 Insulating resin sheet, and circuit board and semiconductor package that use the insulating resin sheet
JP2016058417A (en) 2014-09-05 2016-04-21 日本特殊陶業株式会社 Semiconductor power module manufacturing method
JP2016115711A (en) 2014-12-11 2016-06-23 株式会社ジェイデバイス Semiconductor package and manufacturing method of the same
US20160211221A1 (en) 2015-01-16 2016-07-21 Amkor Technology, Inc. Semiconductor device and manufacturing method thereof

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