JP3019899B2 - Manufacturing method of multi-chip module - Google Patents

Manufacturing method of multi-chip module

Info

Publication number
JP3019899B2
JP3019899B2 JP2770893A JP2770893A JP3019899B2 JP 3019899 B2 JP3019899 B2 JP 3019899B2 JP 2770893 A JP2770893 A JP 2770893A JP 2770893 A JP2770893 A JP 2770893A JP 3019899 B2 JP3019899 B2 JP 3019899B2
Authority
JP
Japan
Prior art keywords
circuit board
semiconductor element
film carrier
electrode
conductor wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP2770893A
Other languages
Japanese (ja)
Other versions
JPH06244241A (en
Inventor
博昭 藤本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Panasonic Holdings Corp
Original Assignee
Panasonic Corp
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp, Matsushita Electric Industrial Co Ltd filed Critical Panasonic Corp
Priority to JP2770893A priority Critical patent/JP3019899B2/en
Publication of JPH06244241A publication Critical patent/JPH06244241A/en
Application granted granted Critical
Publication of JP3019899B2 publication Critical patent/JP3019899B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、ワークステーションや
コンピュータなどに用いるマルチチップモジュールの実
装方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for mounting a multichip module used in a workstation, a computer, and the like.

【0002】[0002]

【従来の技術】近年、ワークステーションやコンピュー
タなどに対する小型化の要求はますます強くなってい
る。これらの要求に答えるためLSIの実装においては
LSIを直接実装するマルチチップモジュールの開発が
盛んに行われている。
2. Description of the Related Art In recent years, demands for miniaturization of workstations and computers have been increasing. In order to meet these demands, in the implementation of LSIs, multi-chip modules for directly mounting the LSIs have been actively developed.

【0003】以下図面を参照しながら、従来のマルチチ
ップモジュールの製造方法の一例について述べる。図3
において、21は多層基板、22はLSIチップ接続用
電極、23は絶縁性樹脂、24は外部電極、25はLS
Iチップ、26はバンプ、28は外部リード、29は加
圧ツールである。
Hereinafter, an example of a conventional method for manufacturing a multichip module will be described with reference to the drawings. FIG.
, 21 is a multilayer substrate, 22 is an LSI chip connection electrode, 23 is an insulating resin, 24 is an external electrode, and 25 is LS
I chip, 26 is a bump, 28 is an external lead, and 29 is a pressure tool.

【0004】次に製造方法について説明する。まず最初
に図3(a)に示すように多層基板21の右端部のLS
Iチップを搭載する領域に絶縁性樹脂23を塗布する。
その後、図3(b)に示す様にLSIチップ25のバン
プ26と電極22を位置合わせし、LSIチップ25を
多層基板21に設置し加圧ツール29でLSIチップ2
5を加圧する。この状態で絶縁性樹脂23を加熱あるい
は光照射により硬化させ、LSIチップ25のバンプ2
6と電極22を電気的に接続する。以下同様に複数のL
SIチップを多層基板22上に接続する。次に図3
(c)に示す様に、外部電極24と外部リード28を半
田等により接続する。その後、外部リード28を介して
マルチチップモジュールの電気検査を行うものである。
Next, a manufacturing method will be described. First, as shown in FIG. 3A, the LS at the right end of the multilayer substrate 21 is formed.
An insulating resin 23 is applied to a region where the I chip is to be mounted.
Thereafter, as shown in FIG. 3B, the bumps 26 of the LSI chip 25 and the electrodes 22 are aligned, the LSI chip 25 is set on the multilayer substrate 21, and the LSI chip 2 is
5 is pressurized. In this state, the insulating resin 23 is cured by heating or light irradiation, and the bumps 2 of the LSI chip 25 are cured.
6 and the electrode 22 are electrically connected. Hereinafter, similarly, a plurality of L
The SI chip is connected on the multilayer substrate 22. Next, FIG.
As shown in (c), the external electrode 24 and the external lead 28 are connected by soldering or the like. Thereafter, an electrical inspection of the multi-chip module is performed via the external leads 28.

【0005】[0005]

【発明が解決しようとする課題】しかしながら上記のよ
うな構成では、個片になった多層基板に複数のLSIチ
ップを接続した後に外部リードを接続するため、外部リ
ードの接続時に発生した不良のため廃棄されるモジュー
ルは、高価なLSIチップを含んでおり非常にコストの
高いものとなる。
However, in the above configuration, since the external leads are connected after connecting a plurality of LSI chips to the singulated multi-layer substrate, a defect generated when connecting the external leads is caused. The discarded module includes an expensive LSI chip and is very expensive.

【0006】またLSIチップの実装の前に外部リード
を接続する方法もあるが、この場合は外部リードが電気
的に分離されていないリードフレームをもちいるため、
モジュールの電気検査は外部リードを含んで樹脂モール
ドした後に外部リードを切断して行うものであり、マル
チチップモジュール内に不良のLSIチップが発生して
もLSIチップの交換は不可能であり、非常に歩留りの
低いものである。また多層基板は個片で取り扱うため生
産性の低いものである。
There is also a method of connecting external leads before mounting the LSI chip. In this case, since the external leads use a lead frame which is not electrically separated,
The electrical inspection of the module is performed by cutting the external leads after resin molding including the external leads. Even if a defective LSI chip occurs in the multi-chip module, it is impossible to replace the LSI chip. The yield is low. Further, the multi-layer substrate has low productivity because it is handled individually.

【0007】本発明は、上記問題点に鑑み、低コストな
マルチチップモジュールを提供するものである。
The present invention has been made in view of the above problems, and provides a low-cost multi-chip module.

【0008】[0008]

【課題を解決するための手段】上記問題点を解決するた
めに、本発明のマルチチップモジュールの製造方法は、
回路基板挿入孔及びガイド孔を有した可とう性フィルム
の少なくとも片面に電気的に独立し、その先端が前記回
路基板挿入孔に突出した導体配線を有したフィルムキャ
リアの前記導体配線の先端と回路基板の外部電極を接
続し前記回路基板を前記フィルムキャリアの前記回路
基板挿入孔内に支持する工程、前記回路基板と前記導体
配線の接続部を検査する工程、前記フィルムキャリアに
支持された前記回路基板あるいは半導体素子に絶縁性樹
脂を塗布し前記回路基板の内部電極と前記半導体素子の
突起電極を位置合わせし前記半導体素子を前記回路基板
上に設置する工程、前記半導体素子を加圧し前記半導体
素子の突起電極と前記回路基板の内部電極を接触させる
工程、前記半導体素子を加圧した状態で前記絶縁性樹脂
を硬化し前記半導体素子の突起電極と前記回路基板の内
部電極を電気的に接続することにより前記回路基板の内
部電極に複数の半導体素子を接続する工程、前記フィル
ムキャリアの前記導体配線に電気検査用電極を接触させ
前記回路基板上で構成した回路の電気検査を行う工程、
前記フィルムキャリアから前記導体配線を含み前記回路
基板を打ち抜きマルチチップモジュールを得る工程を備
えたものである。
In order to solve the above problems, a method of manufacturing a multi-chip module according to the present invention comprises:
The flexible film having the circuit board insertion hole and the guide hole is electrically independent on at least one side of the flexible film , and the tip of the flexible film has the circuit hole.
Film carrier with conductor wiring protruding into the circuit board insertion hole
And it connects the external electrodes of the tip and the circuit board of the rear of the conductor wiring the circuit of the film carrier to the circuit board
A step of supporting in a substrate insertion hole, a step of inspecting a connection portion between the circuit board and the conductor wiring, and applying an insulating resin to the circuit board or the semiconductor element supported by the film carrier to form an internal electrode of the circuit board. Positioning the semiconductor element on the circuit board by aligning the projecting electrode of the semiconductor element with the projecting electrode of the semiconductor element; pressing the semiconductor element to contact the projecting electrode of the semiconductor element with the internal electrode of the circuit board; A step of connecting the plurality of semiconductor elements to the internal electrodes of the circuit board by curing the insulating resin in a state where the elements are pressurized and electrically connecting the protruding electrodes of the semiconductor element to the internal electrodes of the circuit board; A step of bringing an electrode for electrical inspection into contact with the conductor wiring of the film carrier and performing an electrical inspection of a circuit formed on the circuit board;
A step of punching the circuit board including the conductor wiring from the film carrier to obtain a multi-chip module.

【0009】[0009]

【作用】本発明は上記した構成によって、多層基板にL
SIチップを接続する前に予め電気的に分離したフィル
ムキャリアのリードを多層基板の外部電極に接続し外部
リードとする構成であるため、外部リード接続時の歩留
まりは、LSIチップには影響せずコストの安いもので
ある。またモジュールの電気検査は、外部リードがフィ
ルムキャリアに支持された状態で行うため生産性が向上
する。
According to the present invention, with the above-described structure, a multi-layer substrate is provided with L
Before connecting the SI chip, the leads of the film carrier, which are electrically separated in advance, are connected to the external electrodes of the multilayer substrate to form the external leads. Therefore, the yield at the time of connecting the external leads does not affect the LSI chip. The cost is low. Further, since the electrical inspection of the module is performed in a state where the external leads are supported by the film carrier, the productivity is improved.

【0010】[0010]

【実施例】以下本発明の一実施例のマルチチップモジュ
ールの製造方法について、図面を参照しながら説明す
る。
DESCRIPTION OF THE PREFERRED EMBODIMENTS A method for manufacturing a multichip module according to one embodiment of the present invention will be described below with reference to the drawings.

【0011】図1は、本発明の一実施例におけるマルチ
チップモジュールの工程別断面図を示すものである。図
1において、1はフィルムキャリア、2は外部リード、
3は多層基板、4は外部電極、5は内部電極、6は絶縁
性樹脂、7はLSIチップ、8はバンプ、9は加圧ツー
ル、10はプローブ、12は光照射を示すものである。
FIG. 1 is a cross-sectional view of a multi-chip module according to an embodiment of the present invention, which is obtained by different processes. In FIG. 1, 1 is a film carrier, 2 is an external lead,
Reference numeral 3 denotes a multilayer substrate, 4 denotes an external electrode, 5 denotes an internal electrode, 6 denotes an insulating resin, 7 denotes an LSI chip, 8 denotes a bump, 9 denotes a pressing tool, 10 denotes a probe , and 12 denotes light irradiation.

【0012】まずはじめに図1(a)に示す様に、多層
基板3の外部電極4とフィルムキャリア1の外部リード
2を接続し、多層基板3をフィルムキャリア1で保持す
る。多層基板3は、ガラス、シリコン、セラミックなど
をベースとする薄膜の多層基板あるいは、ガラスエポキ
シ、セラミックなどの多層基板である。外部電極4の構
成は、薄膜多層基板の場合は、Cr−Cu−Ni−Au
等の多層膜膜である。フィルムキャリア1の外部リード
2は、銅箔をエッチングして形成したものであり、その
厚みは10μm〜100μm程度である。
First, as shown in FIG. 1A, the external electrodes 4 of the multilayer substrate 3 are connected to the external leads 2 of the film carrier 1, and the multilayer substrate 3 is held by the film carrier 1. The multilayer substrate 3 is a multilayer substrate of a thin film based on glass, silicon, ceramic, or the like, or a multilayer substrate of glass epoxy, ceramic, or the like. The configuration of the external electrode 4 is Cr-Cu-Ni-Au in the case of a thin-film multilayer substrate.
And the like. The external leads 2 of the film carrier 1 are formed by etching a copper foil, and have a thickness of about 10 μm to 100 μm.

【0013】外部リード2の表面には、多層基板3の外
部電極4との接合を容易にするためAu、Sn、半田
を形成する。外部電極4と外部リード2の接続の方法
は、パルス加熱による熱圧着あるいは、レーザーによる
加熱接続などにより行う。Pb−Sn半田により半田
する場合は、Pb含有量90%程度の高融点半田を用
い、後にモジュールを搭載するマザーのプリント基板に
半田付けする際の温度に耐えるように構成する。フィル
キャリア1の回路基板挿入孔13に突出した外部リー
ド2に多層基板3を接続した状態の斜視図を図2に示
す。
Au, Sn, solder, etc. are formed on the surface of the external lead 2 to facilitate bonding with the external electrode 4 of the multilayer substrate 3. The connection between the external electrode 4 and the external lead 2 is performed by thermocompression bonding using pulse heating or heating connection using a laser. When soldering with Pb-Sn solder , a high melting point solder having a Pb content of about 90% is used, and is configured to withstand the temperature when soldering to a mother printed board on which a module is mounted later. fill
External Lee projecting the circuit board insertion hole 13 of the beam carrier 1
The de 2 shows a perspective view of a state of connecting the multilayer substrate 3 in FIG.

【0014】次に図1(b)に示す様に、多層基板3の
右端部のLSIチップ搭載する領域に絶縁性樹脂6を塗
布する。絶縁性樹脂6は、アクリル、シリコーン、エポ
キシ等の光硬化型あるいは加熱硬化型の樹脂である。絶
縁性樹脂6の塗布の方法は、ディスペンス、スタンピン
グ、印刷等の方法を用いることができる。
Next, as shown in FIG. 1B, an insulating resin 6 is applied to a region on the right end of the multilayer substrate 3 where the LSI chip is to be mounted. The insulating resin 6 is a photo-curable or heat-curable resin such as acrylic, silicone, or epoxy. As a method of applying the insulating resin 6, a method such as dispensing, stamping, and printing can be used.

【0015】次に図1(c)に示す様にLSIチップ7
のバンプ8と多層基板3の内部電極4と位置合わせし、
LSIチップ7を多層基板3に搭載する。このときLS
Iチップ7は、絶縁性樹脂6の粘性で多層基板3上に仮
固定される。次に、LSIチップ7を加圧ツール9で加
圧する。このときLSIチップ7のバンプ8と多層基板
3の内部電極5間にあった絶縁性樹脂6は、周囲に押し
出されバンプ8と内部電極5は電気的に接触する。次に
LSIチップ7を加圧ツール9で加圧した状態で絶縁性
樹脂6を硬化する。絶縁性樹脂6の硬化の方法は、光硬
化型の場合はLSIチップ7の側面より光照射を行いL
SIチップ7周辺部の絶縁性樹脂6を硬化し、未硬化部
の絶縁性樹脂6は、加圧を解除した後、常温硬化あるい
は加熱硬化により硬化する。また多層基板3が、ガラス
などの透明な場合は多層基板3の裏面より光照射し硬化
する。また絶縁性樹脂6が、加熱硬化型の場合は加圧ツ
ール9に加熱機構を設け加圧ツール9により加熱硬化す
る。
Next, as shown in FIG.
Of the bump 8 and the internal electrode 4 of the multilayer substrate 3,
The LSI chip 7 is mounted on the multilayer substrate 3. At this time, LS
The I chip 7 is temporarily fixed on the multilayer substrate 3 due to the viscosity of the insulating resin 6. Next, the LSI chip 7 is pressed by the pressing tool 9. At this time, the insulating resin 6 existing between the bumps 8 of the LSI chip 7 and the internal electrodes 5 of the multilayer substrate 3 is extruded to the periphery, and the bumps 8 and the internal electrodes 5 come into electrical contact. Next, the insulating resin 6 is cured while the LSI chip 7 is pressed by the pressing tool 9. The method of curing the insulating resin 6 is as follows.
The insulating resin 6 around the SI chip 7 is cured, and the insulating resin 6 in the uncured portion is cured by room temperature curing or heat curing after releasing the pressure. When the multilayer substrate 3 is transparent such as glass, it is irradiated with light from the back surface of the multilayer substrate 3 and cured. When the insulating resin 6 is a heat-curable type, a heating mechanism is provided in the pressurizing tool 9 and the pressurizing tool 9 heats and cures.

【0016】次に図1(d)に示すように加圧ツール9
を解除し、LSIチップ7を多層基板3に接着固定する
とともに、多層基板3の内部電極4とLSIチップ7の
バンプ8を電気的に接続する。次に同様にして複数のL
SIチップ7を多層基板3上に接続する。次に、フィル
ムキャリア1の外部リード2の突出していない部分に特
性検査用のプローブ10を接触させ、複数のLSIチッ
プ7より構成されたマルチチップモジュールの特性検査
を行う。このときフィルムキャリア1の外部リード2は
あらかじめ電気的に分離されているので、特性検査を容
易に行うことができる。また特性検査において不良が発
生した場合はこの段階で不良のLSIチップを交換す
る。LSIチップの交換により歩留まりの向上を図るこ
とができる。
Next, as shown in FIG.
Is released, the LSI chip 7 is bonded and fixed to the multilayer substrate 3, and the internal electrodes 4 of the multilayer substrate 3 and the bumps 8 of the LSI chip 7 are electrically connected. Next, a plurality of L
The SI chip 7 is connected on the multilayer substrate 3. Next, a probe 10 for characteristic inspection is brought into contact with a portion of the film carrier 1 where the external leads 2 do not protrude, and a characteristic inspection of a multi-chip module including a plurality of LSI chips 7 is performed. At this time, since the external leads 2 of the film carrier 1 are electrically separated in advance, the characteristic inspection can be easily performed. If a defect occurs in the characteristic inspection, the defective LSI chip is replaced at this stage. The yield can be improved by replacing the LSI chip.

【0017】次に図1(e)に示す様に外部リード2を
金型で切断、フォーミングしリード付きのマルチチップ
モジュールを得るものである。
Next, as shown in FIG. 1 (e), the external leads 2 are cut and formed by a die to obtain a multi-chip module with leads.

【0018】[0018]

【発明の効果】以上のように、本発明は上記した構成に
よって、多層基板にLSIチップを接続する前に予め電
気的に分離したフィルムキャリアのリードを多層基板の
外部電極に接続し外部リードとする構成であるため、外
部リード接続時に発生する不良による損害は、LSIチ
ップにはおよばず大変コストの安いものである。またモ
ジュールの電気検査は、外部リードがフィルムキャリア
に支持された状態で行うため生産性が向上する。
As described above, according to the present invention, the leads of the film carrier, which are electrically separated in advance before connecting the LSI chip to the multilayer substrate, are connected to the external electrodes of the multilayer substrate by the above-described structure. Therefore, the damage caused by the defect that occurs when the external leads are connected does not reach the LSI chip, and the cost is very low. Further, since the electrical inspection of the module is performed in a state where the external leads are supported by the film carrier, the productivity is improved.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の一実施例を示す工程断面図FIG. 1 is a process sectional view showing an embodiment of the present invention.

【図2】同実施例における一工程を示す斜視図FIG. 2 is a perspective view showing one process in the embodiment.

【図3】従来の製造方法を示す工程断面図FIG. 3 is a process sectional view showing a conventional manufacturing method.

【符号の説明】[Explanation of symbols]

1 フィルムキャリア 2 外部リード 3 多層基板 4 外部電極 5 内部電極 6 絶縁性樹脂 7 LSIチップ 8 バンプ 9 加圧ツール 10 プローブ 12 光照射13 回路基板挿入孔 DESCRIPTION OF SYMBOLS 1 Film carrier 2 External lead 3 Multilayer substrate 4 External electrode 5 Internal electrode 6 Insulating resin 7 LSI chip 8 Bump 9 Pressure tool 10 Probe 12 Light irradiation 13 Circuit board insertion hole

Claims (3)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 回路基板挿入孔及びガイド孔を有した可
とう性フィルムの少なくとも片面に電気的に独立し、そ
の先端が前記回路基板挿入孔に突出した導体配線を有し
たフィルムキャリアの前記導体配線の先端と回路基板
外部電極を接続し前記回路基板を前記フィルムキャ
リアの前記回路基板挿入孔内に支持する工程、前記回路
基板と前記導体配線の接続部を検査する工程、前記フィ
ルムキャリアに支持された前記回路基板の内部電極に複
数の電子部品を接続する工程、前記フィルムキャリアの
前記導体配線に電気検査用電極を接触させ前記回路基板
上で構成した回路の電気検査を行う工程、前記フィルム
キャリアから前記導体配線を含み前記回路基板を打ち抜
きマルチチップモジュールを得る工程よりなることを特
徴とするマルチチップモジュールの製造方法。
1. A electrically independent on at least one surface of the flexible having a circuit board insertion hole and the guide hole film, its
Having a conductor wiring protruding into the circuit board insertion hole.
And the step of supporting said conductive wire tip and the circuit and the circuit board by connecting the external electrodes of the substrate to the circuit board insertion hole of the film carrier of the film carrier, the connecting portion of the conductor wiring and the circuit board Inspecting, connecting a plurality of electronic components to internal electrodes of the circuit board supported by the film carrier, and a circuit formed on the circuit board by contacting an electrode for electrical inspection with the conductor wiring of the film carrier A method for producing a multi-chip module, comprising the steps of: performing an electrical inspection of the above, and punching the circuit board including the conductor wiring from the film carrier to obtain a multi-chip module.
【請求項2】 回路基板がシリコンあるいはガラスより
なり、導体配線が多層であることを特徴とする請求項1
記載のマルチチップモジュールの製造方法。
2. The circuit board according to claim 1, wherein the circuit board is made of silicon or glass, and the conductor wiring is a multilayer.
A method for manufacturing the multichip module according to the above.
【請求項3】 回路基板あるいは半導体素子に絶縁性樹
脂を塗布し前記回路基板の内部電極と前記半導体素子の
突起電極を位置合わせし前記半導体素子を前記回路基板
上に設置する工程、前記半導体素子を加圧し前記半導体
素子の突起電極と前記回路基板の内部電極を接触させる
工程、前記半導体素子を加圧した状態で前記絶縁性樹脂
を硬化し前記半導体素子の突起電極と前記回路基板の内
部電極を電気的に接続することにより前記回路基板の内
部電極に複数の電子部品を接続することを特徴とする請
求項1または2記載のマルチチップモジュールの製造方
法。
3. A step of applying an insulating resin to a circuit board or a semiconductor element, aligning an internal electrode of the circuit board with a projection electrode of the semiconductor element, and placing the semiconductor element on the circuit board. Contacting the protruding electrode of the semiconductor element with the internal electrode of the circuit board, curing the insulating resin in a state where the semiconductor element is pressurized, and projecting the semiconductor element and the internal electrode of the circuit board. 3. The method according to claim 1, wherein a plurality of electronic components are connected to the internal electrodes of the circuit board by electrically connecting the electronic components.
JP2770893A 1993-02-17 1993-02-17 Manufacturing method of multi-chip module Expired - Fee Related JP3019899B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2770893A JP3019899B2 (en) 1993-02-17 1993-02-17 Manufacturing method of multi-chip module

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2770893A JP3019899B2 (en) 1993-02-17 1993-02-17 Manufacturing method of multi-chip module

Publications (2)

Publication Number Publication Date
JPH06244241A JPH06244241A (en) 1994-09-02
JP3019899B2 true JP3019899B2 (en) 2000-03-13

Family

ID=12228501

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2770893A Expired - Fee Related JP3019899B2 (en) 1993-02-17 1993-02-17 Manufacturing method of multi-chip module

Country Status (1)

Country Link
JP (1) JP3019899B2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011018782A (en) * 2009-07-09 2011-01-27 Dainippon Printing Co Ltd Component built-in wiring board and method of manufacturing the same

Also Published As

Publication number Publication date
JPH06244241A (en) 1994-09-02

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