WO2021082898A1 - Cof封装方法 - Google Patents

Cof封装方法 Download PDF

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Publication number
WO2021082898A1
WO2021082898A1 PCT/CN2020/120535 CN2020120535W WO2021082898A1 WO 2021082898 A1 WO2021082898 A1 WO 2021082898A1 CN 2020120535 W CN2020120535 W CN 2020120535W WO 2021082898 A1 WO2021082898 A1 WO 2021082898A1
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WIPO (PCT)
Prior art keywords
flexible circuit
circuit substrate
chip
pin
pins
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PCT/CN2020/120535
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English (en)
French (fr)
Inventor
奚耀鑫
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颀中科技（苏州）有限公司
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Publication date
Application filed by 颀中科技（苏州）有限公司 filed Critical 颀中科技（苏州）有限公司
Priority to JP2021572854A priority Critical patent/JP2022535301A/ja
Priority to US17/615,797 priority patent/US11942432B2/en
Priority to KR1020217039425A priority patent/KR20220003077A/ko
Publication of WO2021082898A1 publication Critical patent/WO2021082898A1/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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Definitions

  • the invention belongs to the field of semiconductor manufacturing, and particularly relates to a COF packaging method.
  • FC FlipChip Interconnect Technology
  • Flip-chip packaging technology is to bond the bardie to the substrate with the surface facing down.
  • the specific process is that bumps are formed on the surface of the chip, and the multiple bumps on the chip are electrically and mechanically connected with the circuit on the circuit substrate through techniques such as thermocompression, and then the circuit substrate can be passed through The internal circuit of the chip realizes the electrical connection between the chip and the external electronic device.
  • the pins of the flexible circuit substrate are upward, the bumps of the chip are downward, and the chip is moved to just above the flexible circuit substrate by adsorption by the thermal compression head. Then, the thermal head heats and applies pressure to the chip, so that the bumps on the chip and the inner pins of the flexible circuit substrate are welded.
  • the purpose of the present invention is to provide a COF packaging method that solves the above technical problems.
  • an embodiment of the present invention provides a COF packaging method, the method includes: S1, providing a flexible circuit substrate to be packaged, and forming a plurality of first pins on the circuit surface of the flexible circuit substrate ; And providing a chip to be packaged, and forming a number of second pins on the packaged chip;
  • step S3 specifically includes:
  • the method further includes: providing a thermal pressing head under the packaged chip, and setting the adsorption surface of the thermal pressing head upward; and adsorbing the packaged chip through the adsorption surface of the thermal pressing head The surface where the second pin is not provided; the thermal pressing head is driven to provide a bottom-up pressure to the packaged chip, and the packaged chip is heated at high temperature.
  • the method further includes: releasing the adsorption force of the adsorption surface, so that the thermal compression head is separated from the packaged chip and removed.
  • the method further includes: providing a base platform above the flexible circuit substrate, and fixing the surface of the flexible circuit substrate without the first pins on the base platform .
  • the base platform is made of a transparent and high-temperature resistant material.
  • the base platform is made of quartz material.
  • the method further includes: providing a CCD imaging device above the base platform.
  • step S2 also includes: seeing through the flexible circuit substrate through a CCD imaging device, monitoring whether the first pin on the flexible circuit substrate is arranged opposite to the second pin on the package chip, if so, continue Proceed to the next operation. If not, adjust the flexible circuit substrate and/or the package chip. When the first pin and the second pin are set relative to each other, proceed to the next step.
  • the method further includes: plastic packaging between the flexible circuit substrate and the packaged chip to form a semi-packaged body; and cutting the semi-packaged body to form a single COF package structure.
  • the COF packaging method of the present invention exchanges the positions of the flexible circuit substrate and the packaged chip and then performs packaging, which can avoid the movement of the device above the flexible circuit substrate during the packaging process. Particles fall on and/or between the pins of the flexible circuit board to improve product yield and stability.
  • FIG. 1 is a schematic flowchart of a COF packaging method provided by an embodiment of the present invention
  • Fig. 2 is a schematic diagram of the COF package according to the present invention.
  • the position term used in this article is the absolute position of space. Up means “up” and “above”, and down means “down” and “below”, and their spatial positions cannot be interchanged.
  • the term for the absolute position in space is the orientation shown in the figure during use or work. In actual applications, the structure cannot be flipped or position interchanged.
  • an embodiment of the present invention provides a COF packaging method, the method includes:
  • the method further includes: plastic packaging between the flexible circuit substrate 10 and the packaged chip 20 to form a semi-packaged body; and cutting the semi-packaged body to form a single COF package structure.
  • the first pin 11 is usually made of Cu (copper), and its surface is tin-plated;
  • the second pin 12 is usually made of Au (gold), so that after they abut against each other and receive high temperature , The gold and tin of the first pin 11 and the second pin 12 are fused to form a eutectic at a high temperature, and then the flexible circuit substrate 10 and the package chip 20 are combined.
  • step S2 on the basis of the prior art, the positions of the flexible circuit substrate 10 and the packaged chip 20 are exchanged and turned over to keep the first pin 11 always facing downward during the packaging process, and the second pin 12 Always set it up.
  • the flexible circuit substrate 10 usually covers the packaged chip 20, when the flexible circuit substrate 10 is above the packaged chip 20, the particles generated during the movement of the device above the packaged chip 20 will not fall into the first pin. On 11 or between the first pins 11, that is, the position and type of the device that drives the two components to move will not affect the packaging result.
  • step S3 specifically includes: keeping the position of the flexible circuit substrate 10 fixed, applying a bottom-up pressure to the packaged chip 20, and heating the packaged chip 20 at a high temperature to make the first pins 11 and The second pin 12 is welded in a fusion eutectic method.
  • a thermal compression head 30 under the packaged chip 20 is provided, and the adsorption surface 31 of the thermal compression head 30 is set upward; the adsorption surface 31 of the thermal compression head 30 is used to adsorb the packaged chip 20.
  • the surface of the second pin 12; the thermal pressing head 30 is driven to move to provide a bottom-up pressure to the packaged chip 20 while heating the packaged chip 20 at a high temperature.
  • the thermal head 30 is a well-known device in the technical field, and its working principle and specific structure will not be further described here. It should be noted that in order to match the position of the packaged chip 20, in this specific embodiment, the thermal The pressing head 30 is arranged under the packaged chip 20, and at the same time, the suction surface 31 of the thermal pressing head 30 needs to be arranged upward to match the suction of the surface of the packaged chip 20 without the second pin 12.
  • the method further includes: releasing the adsorption force of the adsorption surface 31, The thermal compression head 30 is separated from the packaged chip 20 and removed.
  • the method further includes: providing a base platform 40 above the flexible circuit substrate 10, and fixing the surface of the flexible circuit substrate 10 without the first pins 11 on the base platform 40 on.
  • the base platform 40 also fixes the flexible circuit substrate 10 by means of vacuum adsorption, which will not be further described here.
  • the base platform 40 is usually made of metal or ceramic, and the whole is an opaque body. Therefore, it is impossible to monitor the pin offset between the flexible circuit substrate 10 and the packaged chip 20 during the combination process. The situation, correspondingly, requires the two to be pressed together and sent out of the pressing area to check the offset of the hot bonding between the pins through the imaging system. The timeliness lags, and the offset causes the defect rate of short circuits. Promote.
  • the material of the base platform 40 is replaced, and the base platform 40 is formed of a transparent and high-temperature resistant material, such as a quartz material.
  • the method further includes: providing a CCD imaging device 50 above the base platform 40; seeing through the flexible circuit substrate 10 through the CCD imaging device 50, and monitoring whether the first pin 11 on the flexible circuit substrate 10 is connected to the package chip The second pin 12 on the 20 is set relative to each other. If yes, continue to the next step. If not, adjust the flexible circuit substrate 10 and/or the package chip 20. When the first pin 11 and the second pin 12 are set relative to each other, Then proceed to the next step.
  • the packaging is carried out.
  • the particles caused by the movement of the device above the flexible circuit substrate can be avoided.
  • the change of the base platform material can visually monitor the flexible circuit substrate relative to the package chip during the thermal bonding process. Position; Further, by installing a CCD imaging device on the side of the base platform, it is possible to automatically and intuitively monitor whether the flexible circuit substrate is offset relative to the packaged chip during the thermal bonding process, which improves the packaging quality of the product and saves resources.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明揭示了一种COF封装方法，所述方法包括：S1、提供一待封装柔性线路基板，在所述柔性线路基板的线路面上形成若干个第一引脚；以及提供一待封装芯片，并在封装芯片上形成若干个第二引脚；S2、使得并保持柔性线路基板的线路面始终朝下放置，以及使得并保持封装芯片设置有配合第一引脚的第二引脚的面始终朝上放置，并使得柔性线路基板和封装芯片上互相配合的第一引脚和第二引脚相对设置；S3、对柔性线路基板施加一自上至下的压力，和/或对所述封装芯片施加一自下至上的压力，同时高温加热以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。本发明提升产品良率及稳定度。

Description

COF封装方法
本申请要求了申请日为2019年10月29日，申请号为201911038471.0，发明名称为“COF封装方法”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明属于半导体制造领域，尤其涉及一种COF封装方法。
背景技术
随着集成电路密集度的增加，芯片的封装技术也越来越多样化，由于覆晶封装技术(FlipChipInterconnectTechnology，简称FC)具有缩小芯片封装体积及缩短信号传输路径等优点，目前已经广泛应用于芯片封装领域。
覆晶封装技术是将裸晶(bardie)以表面朝下的方式与基板进行接合。具体过程为，在芯片的表面形成凸块(bump)，通过热压合等技术，使芯片上的多个凸块与线路基板上的线路电性连接及机械性连接，之后即可通过线路基板的内部线路实现芯片与外界电子装置的电性连接。
在液晶显示器电路封装领域，目前采用的较多的是卷带式薄膜覆晶封装(Chiponfilm，简称COF)，这种覆晶封装技术是采用柔性线路基板作为封装芯片的载体，即采用柔性线路基板作为上述线路基板，之后通过热压合技术，将芯片上的凸块与柔性线路基板的内引脚接合。
现有技术中，芯片上的凸块与柔性线路基板的内引脚的结合过程中，柔性线路基板引脚向上，芯片的凸块向下，芯片通过热压头吸附移动至柔性线路基板正上方后，热压头对芯片加热并施加压力，以使芯片上的凸块与柔性线路基板的内引脚进行焊接。
该种封装方法进行过程中，由于热压头机构有许多金属传运机构组成，如此，热压头在运动过程中，其金属机构摩擦、线材摩擦会产生许多金属和 非金属的Particle(中文释义，微小的颗粒)，这些Particle有很大机率会落到柔性线路基板引脚上和引脚之间，如此，凸块与引脚焊接后会因为这些Particle造成引脚接触不良或引脚间的短路；导致芯片的电性不良；进一步的，因为有些Particle很细小，一般的电性测试有机率测试不出来，当该产品结合到显示屏后经过一些绕折或环境温湿度的影响，金属的Particle最终造成引脚间的短路，非金属的卤素质Particle最终造成金属迁移而短路，或是引脚上的Particle导致接合强度不足而断路，如此，造成极大的损失。
发明内容
本发明的目的在于提供一种解决上述技术问题的COF封装方法。
为了实现上述发明目的，本发明一实施方式提供一种COF封装方法，所述方法包括：S1、提供一待封装柔性线路基板，在所述柔性线路基板的线路面上形成若干个第一引脚；以及提供一待封装芯片，并在封装芯片上形成若干个第二引脚；
S2、使得并保持柔性线路基板的线路面始终朝下放置，以及使得并保持封装芯片设置有配合第一引脚的第二引脚的面始终朝上放置，并使得柔性线路基板和封装芯片上互相配合的第一引脚和第二引脚相对设置；
S3、对柔性线路基板施加一自上至下的压力，和/或对所述封装芯片施加一自下至上的压力，同时高温加热以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
作为本发明一实施方式的进一步改进，步骤S3具体包括：
保持柔性线路基板位置固定，对所述封装芯片施加一自下至上的压力，同时高温加热封装芯片以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
作为本发明一实施方式的进一步改进，所述方法还包括：提供一处于封装芯片下方的热压头，将所述热压头的吸附面朝上设置；通过热压头的吸附 面吸附封装芯片未设置第二引脚的面；驱动热压头运动，以提供给所述封装芯片一自下至上的压力，同时高温加热封装芯片。
作为本发明一实施方式的进一步改进，步骤S3后，所述方法还包括：解除所述吸附面的吸附力，使热压头脱离所述封装芯片并移除。
作为本发明一实施方式的进一步改进，所述方法还包括：提供一处于柔性线路基板上方的基座平台，将所述柔性线路基板未设置第一引脚的面固定在所述基座平台上。
作为本发明一实施方式的进一步改进，所述基座平台由透明且耐高温的材质构成。
作为本发明一实施方式的进一步改进，所述基座平台由石英材质构成。
作为本发明一实施方式的进一步改进，所述方法还包括：提供一处于基座平台上方的CCD影像装置。
作为本发明一实施方式的进一步改进，步骤S2还包括：通过CCD影像装置透视柔性线路基板，监测柔性线路基板上的第一引脚是否与封装芯片上的第二引脚相对设置，若是，继续进行下一步操作，若否，调整柔性线路基板和/或封装芯片，待第一引脚和第二引脚相对设置时，再进行下一步操作。
作为本发明一实施方式的进一步改进，步骤S3后，所述方法还包括：在柔性线路基板和封装芯片之间进行塑封形成半封装体；对半封装体进行切割形成单体COF封装结构。
与现有技术相比，本发明的COF封装方法，将柔性线路基板和封装芯片进行位置互换并翻转后，再进行封装，可以在封装过程中，避免处于柔性线路基板上方的设备运动产生的Particle落入柔性线路基板的引脚上和/或引脚之间，提升产品良率及稳定度。
附图说明
图1为本发明一实施方式提供的COF封装方法的流程示意图；
图2是本发明涉及的COF封装示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
需要说明的是，本文使用位置名词为空间的绝对位置，上即表示“上”“上方”，下即表示“下”“下方”其空间位置不能互换。空间绝对位置的术语为在使用或工作中如图中所示方位，实际应用中，该结构不能被翻转或位置互换。
结合图1、图2所示，本发明一实施方式提供一种COF封装方法，所述方法包括：
S1、提供一待封装柔性线路基板10，在所述柔性线路基板10的线路面上形成若干个第一引脚11；以及提供一待封装芯片20，并在封装芯片20上形成若干个第二引脚12；
S2、使得并保持柔性线路基板10的线路面始终朝下放置，以及使得并保持封装芯片20设置有配合第一引脚11的第二引脚12的面始终朝上放置，并使得柔性线路基板10和封装芯片20上互相配合的第一引脚11和第二引脚12相对设置；
S3、对柔性线路基板10施加一自上至下的压力，和/或对所述封装芯片20施加一自下至上的压力，同时高温加热以使得第一引脚11和第二引脚12采用融合共晶的方式进行焊接。
进一步的，步骤S3后，所述方法还包括：在柔性线路基板10和封装芯片20之间进行塑封形成半封装体；对半封装体进行切割形成单体COF封装结构。
本发明可实现方式中，第一引脚11通常由Cu(铜)构成，其表面镀锡；第二引脚12通常由Au(金)构成，如此，在其相互抵接，并接受高温后，第一引脚11和第二引脚12的金与锡高温下熔合成共晶，进而结合柔性线路基板10和封装芯片20。
对于步骤S2，在现有技术基础上，将柔性线路基板10和封装芯片20的位置互换，并进行翻转，以保持第一引脚11在封装过程中始终朝下设置，第二引脚12始终朝上设置。
在具体应用过程中，因为柔性线路基板10通常覆盖封装芯片20，如此，当柔性线路基板10处于封装芯片20上方时，处于封装芯片20上方设备运动过程产生的Particle不会落入第一引脚11上或第一引脚11之间，即驱动两个部件运动的设备位置、种类均不会对封装结果产生影响。
本发明一较佳实施方式中，步骤S3具体包括：保持柔性线路基板10位置固定，对所述封装芯片20施加一自下至上的压力，同时高温加热封装芯片20以使得第一引脚11和第二引脚12采用融合共晶的方式进行焊接。
本发明具体实施方式中，提供一处于封装芯片20下方的热压头30，将所述热压头30的吸附面31朝上设置；通过热压头30的吸附面31吸附封装芯片20未设置第二引脚12的面；驱动热压头30运动，以提供给所述封装芯片20一自下至上的压力，同时高温加热封装芯片20。
所述热压头30为本技术领域的公知设备，在此对其工作原理以及具体构成不做进一步的赘述，需要说明的是，为了配合封装芯片20的位置，在该具体实施方式中，热压头30设置于封装芯片20的下方，同时，热压头30的吸附面31需要朝上设置，以配合吸附封装芯片20未设置第二引脚12的面。
进一步的，当采用热压头30转移封装芯片20并对封装芯片20提供压力以及提升封装芯片20的温度时，在步骤S3后，所述方法还包括：解除所述吸附面31的吸附力，使热压头30脱离所述封装芯片20并移除。
如上结构，热压头30运动时，由于其处于封装芯片20的下方，如此，可以进一步的防止热压头30运动过程中产生的Particle落入第一引脚11上或第一引脚11之间。
本发明具体实施方式中，所述方法还包括：提供一处于柔性线路基板10上方的基座平台40，将所述柔性线路基板10未设置第一引脚11的面固定在所述基座平台40上。
本发明具体实施过程中基座平台40同样通过真空吸附的方式固定柔性线路基板10，在此不做进一步的赘述。
较佳的，传统工艺中，基座平台40通常由金属或陶瓷构成，其整体为不透明体，如此，无法在柔性线路基板10和封装芯片20结合过程中，监测其之间的引脚偏移状况，相应的，需要两者压合后，并传出压合区，才能通过影像系统查看引脚之间的热键合的偏移状况，时效性滞后，且导致偏移造成短路的不良率提升。
相应的，本发明较佳实施方式中，对基座平台40的材质进行替换，提供一种由透明且耐高温的材质构成基座平台40，该材质例如：石英材质。
进一步的，所述方法还包括：提供一处于基座平台40上方的CCD影像装置50；通过CCD影像装置50透视柔性线路基板10，监测柔性线路基板10上的第一引脚11是否与封装芯片20上的第二引脚12相对设置，若是，继续进行下一步操作，若否，调整柔性线路基板10和/或封装芯片20，待第一引脚11和第二引脚12相对设置时，再进行下一步操作。
综上所述，本发明的COF封装方法，将柔性线路基板和封装芯片进行位置互换并翻转后，再进行封装，可以在封装过程中，避免处于柔性线路基板上方的设备运动产生的Particle落入柔性线路基板的引脚上和/或引脚之间，提升产品良率及稳定度；另外，基座平台材质的更改，可以在热键合过程中，直观监测柔性线路基板相对封装芯片的位置；进一步的，通过在基座平台侧加装CCD影像装置，可以在热键合过程中，自动且直观的监测柔性线路基板相对封装芯片是否偏移，提升产品的封装品质，且节约资源。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神 所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (10)

  1. 一种COF封装方法，其特征在于，所述方法包括：
    S1、提供一待封装柔性线路基板，在所述柔性线路基板的线路面上形成若干个第一引脚；以及提供一待封装芯片，并在封装芯片上形成若干个第二引脚；
    S2、使得并保持柔性线路基板的线路面始终朝下放置，以及使得并保持封装芯片设置有配合第一引脚的第二引脚的面始终朝上放置，并使得柔性线路基板和封装芯片上互相配合的第一引脚和第二引脚相对设置；
    S3、对柔性线路基板施加一自上至下的压力，和/或对所述封装芯片施加一自下至上的压力，同时高温加热以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
  2. 根据权利要求1所述的COF封装方法，其特征在于，步骤S3具体包括：
    保持柔性线路基板位置固定，对所述封装芯片施加一自下至上的压力，同时高温加热封装芯片以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
  3. 根据权利要求2所述的COF封装方法，其特征在于，所述方法还包括：
    提供一处于封装芯片下方的热压头，将所述热压头的吸附面朝上设置；
    通过热压头的吸附面吸附封装芯片未设置第二引脚的面；
    驱动热压头运动，以提供给所述封装芯片一自下至上的压力，同时高温加热封装芯片。
  4. 据权利要求3所述的COF封装方法，其特征在于，步骤S3后，所述方法还包括：解除所述吸附面的吸附力，使热压头脱离所述封装芯片并移除。
  5. 据权利要求1所述的COF封装方法，其特征在于，所述方法还包括：提供一处于柔性线路基板上方的基座平台，将所述柔性线路基板未设置第一引脚的面固定在所述基座平台上。
  6. 据权利要求5所述的COF封装方法，其特征在于，所述基座平台由透明且耐高温的材质构成。
  7. 据权利要求6所述的COF封装方法，其特征在于，所述基座平台由石英材质构成。
  8. 据权利要求5所述的COF封装方法，其特征在于，所述方法还包括：提供一处于基座平台上方的CCD影像装置。
  9. 据权利要求8所述的COF封装方法，其特征在于，步骤S2还包括：通过CCD影像装置透视柔性线路基板，监测柔性线路基板上的第一引脚是否与封装芯片上的第二引脚相对设置，若是，继续进行下一步操作，若否，调整柔性线路基板和/或封装芯片，待第一引脚和第二引脚相对设置时，再进行下一步操作。
  10. 权利要求1所述的COF封装方法，其特征在于，步骤S3后，所述方法还包括：在柔性线路基板和封装芯片之间进行塑封形成半封装体；对半封装体进行切割形成单体COF封装结构。
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