CN110739238A - Cof封装方法 - Google Patents

Cof封装方法 Download PDF

Info

Publication number
CN110739238A
CN110739238A CN201911038471.0A CN201911038471A CN110739238A CN 110739238 A CN110739238 A CN 110739238A CN 201911038471 A CN201911038471 A CN 201911038471A CN 110739238 A CN110739238 A CN 110739238A
Authority
CN
China
Prior art keywords
flexible circuit
circuit substrate
pin
packaged
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201911038471.0A
Other languages
English (en)
Other versions
CN110739238B (zh
Inventor
奚耀鑫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hefei Qizhong Technology Co Ltd
Chipmore Technology Corp Ltd
Original Assignee
Jiaozhong Science And Technology (suzhou) Co Ltd
Beijing Eswin Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Jiaozhong Science And Technology (suzhou) Co Ltd, Beijing Eswin Technology Co Ltd filed Critical Jiaozhong Science And Technology (suzhou) Co Ltd
Priority to CN201911038471.0A priority Critical patent/CN110739238B/zh
Publication of CN110739238A publication Critical patent/CN110739238A/zh
Priority to US17/615,797 priority patent/US11942432B2/en
Priority to PCT/CN2020/120535 priority patent/WO2021082898A1/zh
Priority to JP2021572854A priority patent/JP2022535301A/ja
Priority to KR1020217039425A priority patent/KR20220003077A/ko
Application granted granted Critical
Publication of CN110739238B publication Critical patent/CN110739238B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5387—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/4985—Flexible insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75743—Suction holding means
    • H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757—Means for aligning
    • H01L2224/75753—Means for optical alignment, e.g. sensors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81122—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors by detecting inherent features of, or outside, the semiconductor or solid-state body
    • H01L2224/81125—Bonding areas on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/81122—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors by detecting inherent features of, or outside, the semiconductor or solid-state body
    • H01L2224/81127—Bonding areas outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81148—Aligning involving movement of a part of the bonding apparatus
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399—Material
    • H01L2224/814—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81401—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81411—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81805—Soldering or alloying involving forming a eutectic alloy at the bonding interface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明揭示了一种COF封装方法，所述方法包括：S1、提供一待封装柔性线路基板，在所述柔性线路基板的线路面上形成若干个第一引脚；以及提供一待封装芯片，并在封装芯片上形成若干个第二引脚；S2、使得并保持柔性线路基板的线路面始终朝下放置，以及使得并保持封装芯片设置有配合第一引脚的第二引脚的面始终朝上放置，并使得柔性线路基板和封装芯片上互相配合的第一引脚和第二引脚相对设置；S3、对柔性线路基板施加一自上至下的压力，和/或对所述封装芯片施加一自下至上的压力，同时高温加热以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。本发明提升产品良率及稳定度。

Description

COF封装方法
技术领域
本发明属于半导体制造领域，尤其涉及一种COF封装方法。
背景技术
随着集成电路密集度的增加，芯片的封装技术也越来越多样化，由于覆晶封装技术(FlipChipInterconnectTechnology，简称FC)具有缩小芯片封装体积及缩短信号传输路径等优点，目前已经广泛应用于芯片封装领域。
覆晶封装技术是将裸晶(bardie)以表面朝下的方式与基板进行接合。具体过程为，在芯片的表面形成凸块(bump)，通过热压合等技术，使芯片上的多个凸块与线路基板上的线路电性连接及机械性连接，之后即可通过线路基板的内部线路实现芯片与外界电子装置的电性连接。
在液晶显示器电路封装领域，目前采用的较多的是卷带式薄膜覆晶封装(Chiponfilm，简称COF)，这种覆晶封装技术是采用柔性线路基板作为封装芯片的载体，即采用柔性线路基板作为上述线路基板，之后通过热压合技术，将芯片上的凸块与柔性线路基板的内引脚接合。
现有技术中，芯片上的凸块与柔性线路基板的内引脚的结合过程中，柔性线路基板引脚向上，芯片的凸块向下，芯片通过热压头吸附移动至柔性线路基板正上方后，热压头对芯片加热并施加压力，以使芯片上的凸块与柔性线路基板的内引脚进行焊接。
该种封装方法进行过程中，由于热压头机构有许多金属传运机构组成，如此，热压头在运动过程中，其金属机构摩擦、线材摩擦会产生许多金属和非金属的Particle(中文释义，微小的颗粒)，这些Particle有很大机率会落到柔性线路基板引脚上和引脚之间，如此，凸块与引脚焊接后会因为这些Particle造成引脚接触不良或引脚间的短路；导致芯片的电性不良；进一步的，因为有些Particle很细小，一般的电性测试有机率测试不出来，当该产品结合到显示屏后经过一些绕折或环境温湿度的影响，金属的Particle最终造成引脚间的短路，非金属的卤素质Particle最终造成金属迁移而短路，或是引脚上的Particle导致接合强度不足而断路，如此，造成极大的损失。
发明内容
本发明的目的在于提供一种解决上述技术问题的COF封装方法。
为了实现上述发明目的，本发明一实施方式提供一种COF封装方法，所述方法包括：S1、提供一待封装柔性线路基板，在所述柔性线路基板的线路面上形成若干个第一引脚；以及提供一待封装芯片，并在封装芯片上形成若干个第二引脚；
S2、使得并保持柔性线路基板的线路面始终朝下放置，以及使得并保持封装芯片设置有配合第一引脚的第二引脚的面始终朝上放置，并使得柔性线路基板和封装芯片上互相配合的第一引脚和第二引脚相对设置；
S3、对柔性线路基板施加一自上至下的压力，和/或对所述封装芯片施加一自下至上的压力，同时高温加热以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
作为本发明一实施方式的进一步改进，步骤S3具体包括：
保持柔性线路基板位置固定，对所述封装芯片施加一自下至上的压力，同时高温加热封装芯片以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
作为本发明一实施方式的进一步改进，所述方法还包括：提供一处于封装芯片下方的热压头，将所述热压头的吸附面朝上设置；通过热压头的吸附面吸附封装芯片未设置第二引脚的面；驱动热压头运动，以提供给所述封装芯片一自下至上的压力，同时高温加热封装芯片。
作为本发明一实施方式的进一步改进，步骤S3后，所述方法还包括：解除所述吸附面的吸附力，使热压头脱离所述封装芯片并移除。
作为本发明一实施方式的进一步改进，所述方法还包括：提供一处于柔性线路基板上方的基座平台，将所述柔性线路基板未设置第一引脚的面固定在所述基座平台上。
作为本发明一实施方式的进一步改进，所述基座平台由透明且耐高温的材质构成。
作为本发明一实施方式的进一步改进，所述基座平台由石英材质构成。
作为本发明一实施方式的进一步改进，所述方法还包括：提供一处于基座平台上方的CCD影像装置。
作为本发明一实施方式的进一步改进，步骤S2还包括：通过CCD影像装置透视柔性线路基板，监测柔性线路基板上的第一引脚是否与封装芯片上的第二引脚相对设置，若是，继续进行下一步操作，若否，调整柔性线路基板和/或封装芯片，待第一引脚和第二引脚相对设置时，再进行下一步操作。
作为本发明一实施方式的进一步改进，步骤S3后，所述方法还包括：在柔性线路基板和封装芯片之间进行塑封形成半封装体；对半封装体进行切割形成单体COF封装结构。
与现有技术相比，本发明的COF封装方法，将柔性线路基板和封装芯片进行位置互换并翻转后，再进行封装，可以在封装过程中，避免处于柔性线路基板上方的设备运动产生的Particle落入柔性线路基板的引脚上和/或引脚之间，提升产品良率及稳定度。
附图说明
图1为本发明一实施方式提供的COF封装方法的流程示意图；
图2是本发明涉及的COF封装示意图。
具体实施方式
以下将结合附图所示的具体实施方式对本发明进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
需要说明的是，本文使用位置名词为空间的绝对位置，上即表示“上”“上方”，下即表示“下”“下方”其空间位置不能互换。空间绝对位置的术语为在使用或工作中如图中所示方位，实际应用中，该结构不能被翻转或位置互换。
结合图1、图2所示，本发明一实施方式提供一种COF封装方法，所述方法包括：
S1、提供一待封装柔性线路基板10，在所述柔性线路基板10的线路面上形成若干个第一引脚11；以及提供一待封装芯片20，并在封装芯片20上形成若干个第二引脚12；
S2、使得并保持柔性线路基板10的线路面始终朝下放置，以及使得并保持封装芯片20设置有配合第一引脚11的第二引脚12的面始终朝上放置，并使得柔性线路基板10和封装芯片20上互相配合的第一引脚11和第二引脚12相对设置；
S3、对柔性线路基板10施加一自上至下的压力，和/或对所述封装芯片20施加一自下至上的压力，同时高温加热以使得第一引脚11和第二引脚12采用融合共晶的方式进行焊接。
进一步的，步骤S3后，所述方法还包括：在柔性线路基板10和封装芯片20之间进行塑封形成半封装体；对半封装体进行切割形成单体COF封装结构。
本发明可实现方式中，第一引脚11通常由Cu(铜)构成，其表面镀锡；第二引脚12通常由Au(金)构成，如此，在其相互抵接，并接受高温后，第一引脚11和第二引脚12的金与锡高温下熔合成共晶，进而结合柔性线路基板10和封装芯片20。
对于步骤S2，在现有技术基础上，将柔性线路基板10和封装芯片20的位置互换，并进行翻转，以保持第一引脚11在封装过程中始终朝下设置，第二引脚12始终朝上设置。
在具体应用过程中，因为柔性线路基板10通常覆盖封装芯片20，如此，当柔性线路基板10处于封装芯片20上方时，处于封装芯片20上方设备运动过程产生的Particle不会落入第一引脚11上或第一引脚11之间，即驱动两个部件运动的设备位置、种类均不会对封装结果产生影响。
本发明一较佳实施方式中，步骤S3具体包括：保持柔性线路基板10位置固定，对所述封装芯片20施加一自下至上的压力，同时高温加热封装芯片20以使得第一引脚11和第二引脚12采用融合共晶的方式进行焊接。
本发明具体实施方式中，提供一处于封装芯片20下方的热压头30，将所述热压头30的吸附面31朝上设置；通过热压头30的吸附面31吸附封装芯片20未设置第二引脚12的面；驱动热压头30运动，以提供给所述封装芯片20一自下至上的压力，同时高温加热封装芯片20。
所述热压头30为本技术领域的公知设备，在此对其工作原理以及具体构成不做进一步的赘述，需要说明的是，为了配合封装芯片20的位置，在该具体实施方式中，热压头30设置于封装芯片20的下方，同时，热压头30的吸附面31需要朝上设置，以配合吸附封装芯片20未设置第二引脚12的面。
进一步的，当采用热压头30转移封装芯片20并对封装芯片20提供压力以及提升封装芯片20的温度时，在步骤S3后，所述方法还包括：解除所述吸附面31的吸附力，使热压头30脱离所述封装芯片20并移除。
如上结构，热压头30运动时，由于其处于封装芯片20的下方，如此，可以进一步的防止热压头30运动过程中产生的Particle落入第一引脚11上或第一引脚11之间。
本发明具体实施方式中，所述方法还包括：提供一处于柔性线路基板10上方的基座平台40，将所述柔性线路基板10未设置第一引脚11的面固定在所述基座平台40上。
本发明具体实施过程中基座平台40同样通过真空吸附的方式固定柔性线路基板10，在此不做进一步的赘述。
较佳的，传统工艺中，基座平台40通常由金属或陶瓷构成，其整体为不透明体，如此，无法在柔性线路基板10和封装芯片20结合过程中，监测其之间的引脚偏移状况，相应的，需要两者压合后，并传出压合区，才能通过影像系统查看引脚之间的热键合的偏移状况，时效性滞后，且导致偏移造成短路的不良率提升。
相应的，本发明较佳实施方式中，对基座平台40的材质进行替换，提供一种由透明且耐高温的材质构成基座平台40，该材质例如：石英材质。
进一步的，所述方法还包括：提供一处于基座平台40上方的CCD影像装置50；通过CCD影像装置50透视柔性线路基板10，监测柔性线路基板10上的第一引脚11是否与封装芯片20上的第二引脚12相对设置，若是，继续进行下一步操作，若否，调整柔性线路基板10和/或封装芯片20，待第一引脚11和第二引脚12相对设置时，再进行下一步操作。
综上所述，本发明的COF封装方法，将柔性线路基板和封装芯片进行位置互换并翻转后，再进行封装，可以在封装过程中，避免处于柔性线路基板上方的设备运动产生的Particle落入柔性线路基板的引脚上和/或引脚之间，提升产品良率及稳定度；另外，基座平台材质的更改，可以在热键合过程中，直观监测柔性线路基板相对封装芯片的位置；进一步的，通过在基座平台侧加装CCD影像装置，可以在热键合过程中，自动且直观的监测柔性线路基板相对封装芯片是否偏移，提升产品的封装品质，且节约资源。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (10)

1.一种COF封装方法，其特征在于，所述方法包括：
S1、提供一待封装柔性线路基板，在所述柔性线路基板的线路面上形成若干个第一引脚；以及提供一待封装芯片，并在封装芯片上形成若干个第二引脚；
S2、使得并保持柔性线路基板的线路面始终朝下放置，以及使得并保持封装芯片设置有配合第一引脚的第二引脚的面始终朝上放置，并使得柔性线路基板和封装芯片上互相配合的第一引脚和第二引脚相对设置；
S3、对柔性线路基板施加一自上至下的压力，和/或对所述封装芯片施加一自下至上的压力，同时高温加热以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
2.根据权利要求1所述的COF封装方法，其特征在于，步骤S3具体包括：
保持柔性线路基板位置固定，对所述封装芯片施加一自下至上的压力，同时高温加热封装芯片以使得第一引脚和第二引脚采用融合共晶的方式进行焊接。
3.根据权利要求2所述的COF封装方法，其特征在于，所述方法还包括：
提供一处于封装芯片下方的热压头，将所述热压头的吸附面朝上设置；
通过热压头的吸附面吸附封装芯片未设置第二引脚的面；
驱动热压头运动，以提供给所述封装芯片一自下至上的压力，同时高温加热封装芯片。
4.据权利要求3所述的COF封装方法，其特征在于，步骤S3后，所述方法还包括：解除所述吸附面的吸附力，使热压头脱离所述封装芯片并移除。
5.据权利要求1所述的COF封装方法，其特征在于，所述方法还包括：提供一处于柔性线路基板上方的基座平台，将所述柔性线路基板未设置第一引脚的面固定在所述基座平台上。
6.据权利要求5所述的COF封装方法，其特征在于，所述基座平台由透明且耐高温的材质构成。
7.据权利要求6所述的COF封装方法，其特征在于，所述基座平台由石英材质构成。
8.据权利要求5所述的COF封装方法，其特征在于，所述方法还包括：提供一处于基座平台上方的CCD影像装置。
9.据权利要求8所述的COF封装方法，其特征在于，步骤S2还包括：通过CCD影像装置透视柔性线路基板，监测柔性线路基板上的第一引脚是否与封装芯片上的第二引脚相对设置，若是，继续进行下一步操作，若否，调整柔性线路基板和/或封装芯片，待第一引脚和第二引脚相对设置时，再进行下一步操作。
10.权利要求1所述的COF封装方法，其特征在于，步骤S3后，所述方法还包括：在柔性线路基板和封装芯片之间进行塑封形成半封装体；对半封装体进行切割形成单体COF封装结构。
CN201911038471.0A 2019-10-29 2019-10-29 Cof封装方法 Active CN110739238B (zh)

Priority Applications (5)

Application Number Priority Date Filing Date Title
CN201911038471.0A CN110739238B (zh) 2019-10-29 2019-10-29 Cof封装方法
US17/615,797 US11942432B2 (en) 2019-10-29 2020-10-13 Method for packaging COF
PCT/CN2020/120535 WO2021082898A1 (zh) 2019-10-29 2020-10-13 Cof封装方法
JP2021572854A JP2022535301A (ja) 2019-10-29 2020-10-13 Ｃｏｆパッケージ方法
KR1020217039425A KR20220003077A (ko) 2019-10-29 2020-10-13 Cof 패키징 방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911038471.0A CN110739238B (zh) 2019-10-29 2019-10-29 Cof封装方法

Publications (2)

Publication Number Publication Date
CN110739238A true CN110739238A (zh) 2020-01-31
CN110739238B CN110739238B (zh) 2021-03-19

Family

ID=69270295

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911038471.0A Active CN110739238B (zh) 2019-10-29 2019-10-29 Cof封装方法

Country Status (5)

Country Link
US (1) US11942432B2 (zh)
JP (1) JP2022535301A (zh)
KR (1) KR20220003077A (zh)
CN (1) CN110739238B (zh)
WO (1) WO2021082898A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021082898A1 (zh) * 2019-10-29 2021-05-06 颀中科技（苏州）有限公司 Cof封装方法

Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313521B1 (en) * 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
CN1674282A (zh) * 2004-03-24 2005-09-28 罗姆股份有限公司 半导体装置制造方法、半导体装置和半导体芯片
JP2006324580A (ja) * 2005-05-20 2006-11-30 Athlete Fa Kk 接合ヘッドの清掃装置および電子部品の接合装置
CN101088161A (zh) * 2004-12-28 2007-12-12 松下电器产业株式会社 半导体芯片的安装结构体和其制造方法
CN101231979A (zh) * 2007-01-26 2008-07-30 百慕达南茂科技股份有限公司 内引脚接合封装
CN104517924A (zh) * 2013-09-30 2015-04-15 南茂科技股份有限公司 多芯片堆叠封装结构及其制造方法
CN105940486A (zh) * 2014-02-07 2016-09-14 迪睿合株式会社 对准方法、电子部件的连接方法、连接体的制造方法、连接体、各向异性导电膜
CN107170769A (zh) * 2017-07-06 2017-09-15 苏州晶方半导体科技股份有限公司 一种影像传感芯片的封装结构及其封装方法
US20180153510A1 (en) * 2016-12-04 2018-06-07 Exo Imaging Inc. Low voltage, low power mems transducer with direct interconnect capability
CN110323201A (zh) * 2019-05-10 2019-10-11 颀中科技（苏州）有限公司 柔性线路板与覆晶薄膜封装结构
CN110351460A (zh) * 2019-06-22 2019-10-18 王之奇 一种摄像头封装模组及其封装方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002009112A (ja) * 2000-06-21 2002-01-11 Matsushita Electric Ind Co Ltd 半導体素子の位置決め方法
JP4601844B2 (ja) * 2001-01-23 2010-12-22 芝浦メカトロニクス株式会社 ボンディング装置及びボンディンク方法
JP3861604B2 (ja) * 2001-02-07 2006-12-20 セイコーエプソン株式会社 電気光学装置の製造方法、電気光学装置、電子機器、および圧着装置
JP2004039802A (ja) * 2002-07-02 2004-02-05 Renesas Technology Corp 半導体装置の製造方法および半導体製造装置
JP4146826B2 (ja) * 2004-09-14 2008-09-10 カシオマイクロニクス株式会社 配線基板及び半導体装置
CN1921100A (zh) 2005-08-26 2007-02-28 南茂科技股份有限公司 薄膜覆晶封装的卷带及其构造以及制造方法
JP2009277987A (ja) 2008-05-16 2009-11-26 Mitsui Mining & Smelting Co Ltd 電子部品実装用フィルムキャリアテープ、その製造方法、および、半導体装置
TWI685074B (zh) 2016-10-25 2020-02-11 矽創電子股份有限公司 晶片封裝結構及相關引腳接合方法
CN107424966B (zh) 2017-06-30 2019-07-12 永道无线射频标签(扬州)有限公司 一种覆晶芯片与软性基板封装的结构及方法
CN110739238B (zh) 2019-10-29 2021-03-19 颀中科技（苏州）有限公司 Cof封装方法

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6313521B1 (en) * 1998-11-04 2001-11-06 Nec Corporation Semiconductor device and method of manufacturing the same
CN1674282A (zh) * 2004-03-24 2005-09-28 罗姆股份有限公司 半导体装置制造方法、半导体装置和半导体芯片
CN101088161A (zh) * 2004-12-28 2007-12-12 松下电器产业株式会社 半导体芯片的安装结构体和其制造方法
JP2006324580A (ja) * 2005-05-20 2006-11-30 Athlete Fa Kk 接合ヘッドの清掃装置および電子部品の接合装置
CN101231979A (zh) * 2007-01-26 2008-07-30 百慕达南茂科技股份有限公司 内引脚接合封装
CN104517924A (zh) * 2013-09-30 2015-04-15 南茂科技股份有限公司 多芯片堆叠封装结构及其制造方法
CN105940486A (zh) * 2014-02-07 2016-09-14 迪睿合株式会社 对准方法、电子部件的连接方法、连接体的制造方法、连接体、各向异性导电膜
US20180153510A1 (en) * 2016-12-04 2018-06-07 Exo Imaging Inc. Low voltage, low power mems transducer with direct interconnect capability
CN107170769A (zh) * 2017-07-06 2017-09-15 苏州晶方半导体科技股份有限公司 一种影像传感芯片的封装结构及其封装方法
CN110323201A (zh) * 2019-05-10 2019-10-11 颀中科技（苏州）有限公司 柔性线路板与覆晶薄膜封装结构
CN110351460A (zh) * 2019-06-22 2019-10-18 王之奇 一种摄像头封装模组及其封装方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2021082898A1 (zh) * 2019-10-29 2021-05-06 颀中科技（苏州）有限公司 Cof封装方法
US11942432B2 (en) 2019-10-29 2024-03-26 Chipmore Technology Corporation Limited Method for packaging COF

Also Published As

Publication number Publication date
US20220319997A1 (en) 2022-10-06
WO2021082898A1 (zh) 2021-05-06
KR20220003077A (ko) 2022-01-07
CN110739238B (zh) 2021-03-19
JP2022535301A (ja) 2022-08-05
US11942432B2 (en) 2024-03-26

Similar Documents

Publication Publication Date Title
TWI467681B (zh) 半導體裝置之製造方法
US5297333A (en) Packaging method for flip-chip type semiconductor device
CN109103117B (zh) 结合半导体芯片的设备和结合半导体芯片的方法
KR100662820B1 (ko) 플립칩 본더
JP2005093838A (ja) 半導体集積回路装置の製造方法
TWI682512B (zh) 熱壓結合器及其操作方法，以及用於細間距覆晶組裝的互連方法
JP5732356B2 (ja) 半導体装置の製造方法
CN110739238B (zh) Cof封装方法
JP2001024085A (ja) 半導体装置
US8936968B2 (en) Flip chip package manufacturing method
JPH10284535A (ja) 半導体装置の製造方法及び半導体部品
KR102372519B1 (ko) 실장 장치
JPH06163634A (ja) フリップチップ型半導体装置の実装方法
KR20190116235A (ko) 반도체 칩 본딩 장치 및 반도체 칩 본딩 방법
KR100936781B1 (ko) 플립칩 본딩장치 및 이를 이용한 플립칩 본딩방법
KR101300573B1 (ko) 반도체 패키지 제조용 칩 이송 장치
JP5098939B2 (ja) ボンディング装置及びボンディング方法
JPH06310563A (ja) 半導体装置および半導体装置の製造方法
WO2014125536A1 (ja) 半導体モジュールおよび半導体チップ実装方法
JPH10223687A (ja) フリップチップ実装モジュール及び製造方法、製造装置
KR102284943B1 (ko) 본딩 장치 및 본딩 방법
KR101081735B1 (ko) 엘. 오. 씨(ｌｏｃ) 다이접착 장비를 이용한 플립 칩 패키지 제조방법 및 이에 의한 플립 칩 패키지
JP2000332052A (ja) 半導体装置の製造方法および半導体装置
KR20230042480A (ko) 기판 홀더 및, 본딩 시스템 및 본딩 방법
JP2000232113A (ja) ダイボンダ

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
CB02 Change of applicant information
CB02 Change of applicant information

Address after: No. 166 Fengli Street, Suzhou Industrial Park, Jiangsu Province

Applicant after: CHIPMORE TECHNOLOGY Corp.,Ltd.

Applicant after: Xi'an yisiwei Material Technology Co., Ltd

Address before: No. 166 Fengli Street, Suzhou Industrial Park, Jiangsu Province

Applicant before: CHIPMORE TECHNOLOGY Corp.,Ltd.

Applicant before: Beijing yisiwei Technology Co.,Ltd.

GR01 Patent grant
GR01 Patent grant
TR01 Transfer of patent right
TR01 Transfer of patent right

Effective date of registration: 20210616

Address after: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province

Patentee after: CHIPMORE TECHNOLOGY Corp.,Ltd.

Patentee after: Hefei Qizhong Sealing Technology Co.,Ltd.

Address before: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province

Patentee before: CHIPMORE TECHNOLOGY Corp.,Ltd.

Patentee before: Xi'an yisiwei Material Technology Co., Ltd

CP01 Change in the name or title of a patent holder
CP01 Change in the name or title of a patent holder

Address after: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province

Patentee after: CHIPMORE TECHNOLOGY Corp.,Ltd.

Patentee after: Hefei Qizhong Technology Co., Ltd

Address before: 215000 No.166, Fengli street, Suzhou Industrial Park, Jiangsu Province

Patentee before: CHIPMORE TECHNOLOGY Corp.,Ltd.

Patentee before: Hefei Qizhong sealing and Testing Technology Co., Ltd