JP2005093838A - 半導体集積回路装置の製造方法 - Google Patents
半導体集積回路装置の製造方法 Download PDFInfo
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- JP2005093838A JP2005093838A JP2003327046A JP2003327046A JP2005093838A JP 2005093838 A JP2005093838 A JP 2005093838A JP 2003327046 A JP2003327046 A JP 2003327046A JP 2003327046 A JP2003327046 A JP 2003327046A JP 2005093838 A JP2005093838 A JP 2005093838A
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Abstract
【解決手段】 多数個取り基板3gを準備した後、第1の加熱ステージ9b上に半導体チップを配置し、その後、第1の加熱ステージ9b上において前記半導体チップの上方に多数個取り基板3gを配置し、続いて、前記半導体チップを第1の加熱ステージ9bによって直接加熱しながら前記半導体チップと多数個取り基板3gとを熱圧着によって仮接合し、前記仮接合の後、第1の加熱ステージ9bに隣接して設けられた第2の加熱ステージ10b上に、前記仮接合した多数個取り基板3gを配置し、その後、第2の加熱ステージ10b上において前記半導体チップを第2の加熱ステージ10bによって直接加熱しながら、前記半導体チップを加圧して前記半導体チップと多数個取り基板3gとを熱圧着によって本接合する。
【選択図】 図10
Description
1.以下の工程を含む半導体集積回路装置の製造方法:
(a)基板を準備する工程;
(b)複数の半導体チップを各々の主面を上方に向けてステージ上に配置する工程;
(c)前記複数の半導体チップの上方に前記基板を配置する工程;
(d)前記複数の半導体チップを一括して前記基板と熱圧着(加熱を伴った圧着、接合、接着などを言う)によって接合する工程。
(a)基板を準備する工程;
(b)複数の半導体チップを加熱ステージ上に配置する工程;
(c)前記複数の半導体チップの上方に前記基板を配置する工程;
(d)前記加熱ステージによって前記複数の半導体チップを直接加熱しながら、前記複数の半導体チップに対応してそれぞれ独立可動自在に支持された複数の加圧ブロックにより各々に対応する前記半導体チップを加圧することにより、前記複数の半導体チップを一括して前記基板と熱圧着によって接合する工程。
(a)基板を準備する工程;
(b)第1の加熱ステージ上に半導体チップを配置する工程;
(c)前記第1の加熱ステージ上において前記半導体チップの上方に前記基板を配置し、その後、前記半導体チップを前記第1の加熱ステージによって直接加熱しながら前記半導体チップと前記基板とを熱圧着によって仮接合する工程;
(d)前記(c)工程の後、前記第1の加熱ステージに隣接して設けられた第2の加熱ステージ上に、前記仮接合した前記半導体チップと前記基板とを配置する工程;
(e)前記第2の加熱ステージ上において前記半導体チップを前記第2の加熱ステージによって直接加熱しながら、前記第1の加熱ステージでの加圧より長い時間前記半導体チップを加圧して前記半導体チップと前記基板とを熱圧着によって本接合する工程。
(a)基板を準備する工程;
(b)半導体チップを加熱ステージ上に配置する工程;
(c)前記半導体チップの上方に前記基板を配置する工程;
(d)前記半導体チップを前記加熱ステージによって加熱し、前記基板をこれより上方に配置された加熱手段によって加熱し、前記基板側より前記半導体チップ側を高い温度で加熱して前記半導体チップと前記基板とを熱圧着によって接合する工程。
1.以下の工程を含む半導体集積回路装置の製造方法:
(a)前記半導体集積回路装置の領域であるデバイス領域がマトリクス配置で複数形成された多数個取り基板を準備する工程;
(b)複数の半導体チップそれぞれを各々の主面を上方に向けてステージ上に配置する工程;
(c)前記複数の半導体チップの上方に前記多数個取り基板を配置する工程;
(d)前記多数個取り基板のマトリクス配置の前記デバイス領域の幅方向の1列もしくは複数列ごとに前記複数の半導体チップを一括して前記多数個取り基板と熱圧着で接合する工程。
2.以下の工程を含む半導体集積回路装置の製造方法:
(a)前記半導体集積回路装置の領域であるデバイス領域がマトリクス配置で複数形成された多数個取り基板を準備する工程;
(b)複数の半導体チップを加熱ステージ上に配置する工程;
(c)前記複数の半導体チップの上方に前記多数個取り基板を配置する工程;
(d)前記加熱ステージによって前記複数の半導体チップを直接加熱しながら、前記複数の半導体チップに対応してそれぞれ独立可動自在に支持された複数の加圧ブロックにより各々に対応する前記半導体チップを加圧することにより、前記多数個取り基板のマトリクス配置の前記デバイス領域の幅方向の1列もしくは複数列ごとに前記複数の半導体チップを一括して前記多数個取り基板と熱圧着で接合する工程。
3.以下の構成を有する半導体製造装置:
(a)複数の半導体チップを配置可能な加熱ステージ;
(b)前記複数の半導体チップに対応してそれぞれ独立可動自在に支持された複数の加圧ブロックを備えており、前記複数の加圧ブロックを加圧するためのエアーを供給する空間部を有した支持ブロック部;
(c)前記支持ブロック部の前記空間部にエアーを取り込むエアー取り込み部;
(d)前記支持ブロック部と連結して設けられており、荷重の変化点を検出する荷重変化検出手段。
4.以下の構成を有する半導体製造装置:
(a)複数の半導体チップを配置可能な加熱ステージ;
(b)前記複数の半導体チップに対応してそれぞれ独立可動自在に支持された複数の加圧ブロックを備え、前記複数の加圧ブロックを加圧するためのエアーを供給する空間部を有しており、さらに本体部に着脱自在に設けられた支持ブロック部;
(c)前記支持ブロック部の前記空間部にエアーを取り込むエアー取り込み部;
(d)前記支持ブロック部と連結して設けられており、荷重の変化点を検出する荷重変化検出手段。
5.以下の構成を有する半導体製造装置:
(a)それぞれに半導体チップを配置可能であり、前記半導体チップの裏面より小さな複数の小型ステージが設けられた加熱ステージ;
(b)前記複数の半導体チップに対応してそれぞれ独立可動自在に支持された複数の加圧ブロックを備えており、前記複数の加圧ブロックを加圧するためのエアーを供給する空間部を有した支持ブロック部;
(c)前記支持ブロック部の前記空間部にエアーを取り込むエアー取り込み部;
(d)前記支持ブロック部と連結して設けられており、荷重の変化点を検出する荷重変化検出手段。
6.以下の構成を有する半導体製造装置:
(a)複数の半導体チップを配置可能な加熱ステージ;
(b)前記複数の半導体チップに対応してそれぞれ独立可動自在に支持された複数の加圧ブロックを備えており、前記複数の加圧ブロックを加圧するためのエアーを供給する空間部を有した支持ブロック部;
(c)前記支持ブロック部内に配置され、前記複数の加圧ブロックに密着するシート状の弾性膜;
(d)前記支持ブロック部の前記空間部にエアーを取り込むエアー取り込み部;
(e)前記支持ブロック部と連結して設けられており、荷重の変化点を検出する荷重変化検出手段。
図1は本発明の実施の形態の半導体集積回路装置の外部端子側の構造の一例を示す斜視図、図2は図1に示す半導体集積回路装置のチップ側の内部の構造の一例を封止体を透過して示す斜視図、図3は図1に示す半導体集積回路装置の構造の一例を示す断面図、図4は図1に示す半導体集積回路装置の組み立て手順の一例を示す製造プロセスフロー図、図5は図4に示す組み立てにおける配線基板の表面側の構造の一例を示す平面図、図6は図4に示す組み立てにおける配線基板の裏面側の構造の一例を示す平面図、図7は図4に示す組み立てのダイボンディング後の配線基板の裏面側の構造の一例を示す平面図、図8は本発明の実施の形態の半導体製造装置の概略構造の一例を示す平面図、図9は図8に示す半導体製造装置の主要部の構造の一例を示す断面図、図10は図8に示す半導体製造装置の主要部の構造の一例を示す斜視図、図11は図10に示す主要部の第2の加熱ステージ側の構造の一例を示す断面図、図12は図11に示す主要部の低荷重着地時の動作フローの一例を示す断面図、図13は図11に示す主要部の変形例の低荷重着地時の動作フローを示す断面図、図14は図11に示す主要部の着地検出時の構造の一例を示す断面図、図15は図11に示す主要部の荷重設定時の構造の一例を示す断面図、図16は図11に示す主要部の品種切り替え時の構造の一例を示す断面図、図17は図11に示す主要部における弾性体密着状態の一例を示す断面図、図18は図11に示す主要部における異物吸引状態の一例を示す断面図、図19は図11に示す主要部における支持ブロック部取り付け状態の構造の一例を示す斜視図、図20は図19に示す支持ブロック部の取り付け方法の一例を示す斜視図、図21は図20に示す支持ブロック部の内部部品の構成の一例を示す斜視図、図22は図20に示す支持ブロック部の構造の一例を示す断面図、図23は図22に示す支持ブロック部の種々の変形例の構造を示す断面図、図24は本発明の実施の形態の変形例の半導体集積回路装置の構造を示す断面図である。
1a パッド
1b 主面
1c 裏面
2 ダイボンドテープ
3 有機基板(基板)
3a 表面
3b 裏面
3c ボンディング電極
3d 配線
3e 開口部
3f バンプランド
3g 多数個取り基板(基板)
3h デバイス領域
4 ワイヤ
5 はんだボール
6 封止体
7 BOC(半導体集積回路装置)
8 チップマウンタ
9 第1の圧着部
9a 第1のヘッド
9b 第1の加熱ステージ
9c ヒータ(加熱手段)
9d ブロック本体部(本体部)
9e 傾き調整機構部
9f 支持ブロック部
9g 加圧ブロック
9h XYステージ
10 第2の圧着部
10a 第2のヘッド
10b 第2の加熱ステージ
10c ヒータ(加熱手段)
10d ブロック本体部(本体部)
10e ロードセル(荷重変化検出手段)
10f 高さ制御プレート
10g モータ
10h ロードセル支持部
10i 傾き調整機構部
10j 小型ステージ
10k 吸引系
10m 支持ブロック部
10n 加圧ブロック
10p 空間部
10q エアー供給系
10r 金属スペーサ
10s 弾性体スペーサ
10t 弾性膜
10u 中継管(エアー取り込み部)
10v ホース
10w 固定ネジ
10x 貫通孔
11 ストッカー
12 ガイドレール
13 ハンドラ
14 プリベーク部
15 ロードポート
16 搬出ロボット
17 ウェハステージ
18 ピックアップ部
19 製品アンローダ
20 LOC(半導体集積回路装置)
20a インナリード
20b アウタリード
20c バスバーリード
Claims (20)
- 以下の工程を含む半導体集積回路装置の製造方法:
(a)基板を準備する工程;
(b)複数の半導体チップを各々の主面を上方に向けてステージ上に配置する工程;
(c)前記複数の半導体チップの上方に前記基板を配置する工程;
(d)前記複数の半導体チップを一括して前記基板と熱圧着によって接合する工程。 - 請求項1記載の半導体集積回路装置の製造方法において、前記基板として有機配線基板を用いることを特徴とする半導体集積回路装置の製造方法。
- 以下の工程を含む半導体集積回路装置の製造方法:
(a)基板を準備する工程;
(b)複数の半導体チップをステージ上に配置する工程;
(c)前記複数の半導体チップの第1の主面側に前記基板を配置する工程;
(d)前記ステージによって前記複数の半導体チップを前記半導体チップの第2の主面側から加熱しながら、前記複数の半導体チップに対応してそれぞれ独立して可動するように支持された複数の加圧ブロックにより各々に対応する前記半導体チップを加圧することにより、前記複数の半導体チップを一括して前記基板と熱圧着によって接合する工程。 - 請求項3記載の半導体集積回路装置の製造方法において、前記(d)工程における加熱は前記第1の主面側からも行われることを特徴とする半導体集積回路装置の製造方法。
- 請求項3記載の半導体集積回路装置の製造方法において、前記半導体チップの前記第2の主面側からの加熱は前記基板を介在することなく直接行われることを特徴とする半導体集積回路装置の製造方法。
- 請求項3記載の半導体集積回路装置の製造方法において、前記基板は有機配線基板であることを特徴とする半導体集積回路装置の製造方法。
- 請求項6記載の半導体集積回路装置の製造方法において、前記半導体チップの前記第2の主面側からの加熱温度は前記有機配線基板を構成する主要有機樹脂部材のガラス転移温度より低いことを特徴とする半導体集積回路装置の製造方法。
- 以下の工程を含む半導体集積回路装置の製造方法:
(a)基板を準備する工程;
(b)第1のステージ上に半導体チップを配置する工程;
(c)前記第1のステージ上において前記半導体チップの第1の主面側に前記基板を配置し、前記半導体チップを前記第1のステージ上において前記半導体チップの第2の主面側から加熱しながら前記半導体チップと前記基板とを熱圧着によって仮接合する工程;
(d)前記(c)工程の後、前記第1のステージに隣接して設けられた第2のステージ上に、前記仮接合した前記半導体チップと前記基板とを配置する工程;
(e)前記第2のステージ上において前記半導体チップを前記半導体チップの第2の主面側から加熱しながら、前記第1のステージでの加圧より長い時間前記半導体チップを加圧して前記半導体チップと前記基板とを熱圧着によって本接合する工程。 - 請求項8記載の半導体集積回路装置の製造方法において、前記第2のステージ上に複数の半導体チップを配置し、前記第2のステージによって前記複数の半導体チップを直接加熱しながら前記複数の半導体チップを一括して前記基板と熱圧着によって本接合することを特徴とする半導体集積回路装置の製造方法。
- 請求項8記載の半導体集積回路装置の製造方法において、前記基板は有機配線基板であることを特徴とする半導体集積回路装置の製造方法。
- 請求項10記載の半導体集積回路装置の製造方法において、前記有機配線基板は多層配線基板であることを特徴とする半導体集積回路装置の製造方法。
- 請求項11記載の半導体集積回路装置の製造方法において、前記第2のステージ上における前記半導体チップの前記第2の主面側からの加熱温度は前記有機配線基板を構成する主要有機樹脂部材のガラス転移温度より低いことを特徴とする半導体集積回路装置の製造方法。
- 請求項10記載の半導体集積回路装置の製造方法において、前記第2のステージ上における前記半導体チップの前記第2の主面側からの加熱は前記有機配線基板を介在することなく直接行われることを特徴とする半導体集積回路装置の製造方法。
- 請求項10記載の半導体集積回路装置の製造方法において、前記半導体チップと前記基板の接合は、前記基板の主要部を構成する有機樹脂部材よりも剛性率が低い有機層を介して行われることを特徴とする半導体集積回路装置の製造方法。
- 以下の工程を含む半導体集積回路装置の製造方法:
(a)基板を準備する工程;
(b)半導体チップをステージ上に配置する工程;
(c)前記半導体チップの上方に前記基板を配置する工程;
(d)前記半導体チップを前記ステージ側から加熱し、前記基板を前記基板を挟んで前記ステージと反対側から加熱し、前記基板側より前記半導体チップ側を高い温度で加熱して前記半導体チップと前記基板とを熱圧着によって接合する工程。 - 請求項15記載の半導体集積回路装置の製造方法において、前記基板側を150℃以下で加熱することを特徴とする半導体集積回路装置の製造方法。
- 請求項15記載の半導体集積回路装置の製造方法において、前記基板側を100℃以下で加熱することを特徴とする半導体集積回路装置の製造方法。
- 請求項15記載の半導体集積回路装置の製造方法において、前記基板側を50℃以下で加熱することを特徴とする半導体集積回路装置の製造方法。
- 請求項15記載の半導体集積回路装置の製造方法において、前記基板側を常温で加熱することを特徴とする半導体集積回路装置の製造方法。
- 請求項15記載の半導体集積回路装置の製造方法において、前記基板として有機配線基板を用いることを特徴とする半導体集積回路装置の製造方法。
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JP2003327046A JP4206320B2 (ja) | 2003-09-19 | 2003-09-19 | 半導体集積回路装置の製造方法 |
CNA2008101690418A CN101431036A (zh) | 2003-09-19 | 2004-07-28 | 半导体集成电路器件的制造方法 |
CNB2004100586828A CN100435301C (zh) | 2003-09-19 | 2004-07-28 | 半导体集成电路器件的制造方法 |
KR1020040059614A KR20050029110A (ko) | 2003-09-19 | 2004-07-29 | 반도체 집적 회로 장치의 제조 방법 |
US10/901,999 US7270258B2 (en) | 2003-09-19 | 2004-07-30 | Method of fabrication of semiconductor integrated circuit device |
US11/837,168 US7757930B2 (en) | 2003-09-19 | 2007-08-10 | Fabrication method of semiconductor integrated circuit device |
US12/836,432 US7861912B2 (en) | 2003-09-19 | 2010-07-14 | Fabrication method of semiconductor integrated circuit device |
US12/956,524 US8074868B2 (en) | 2003-09-19 | 2010-11-30 | Fabrication method of semiconductor integrated circuit device |
US13/295,336 US8292159B2 (en) | 2003-09-19 | 2011-11-14 | Fabrication method of semiconductor integrated circuit device |
US13/607,864 US8640943B2 (en) | 2003-09-19 | 2012-09-10 | Fabrication method of semiconductor integrated circuit device |
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2004
- 2004-07-28 CN CNA2008101690418A patent/CN101431036A/zh active Pending
- 2004-07-28 CN CNB2004100586828A patent/CN100435301C/zh not_active Expired - Fee Related
- 2004-07-29 KR KR1020040059614A patent/KR20050029110A/ko not_active Application Discontinuation
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- 2011-11-14 US US13/295,336 patent/US8292159B2/en not_active Expired - Fee Related
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- 2012-09-10 US US13/607,864 patent/US8640943B2/en active Active
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JP2019208069A (ja) * | 2013-12-13 | 2019-12-05 | 日亜化学工業株式会社 | 発光装置 |
JP2021530120A (ja) * | 2018-07-02 | 2021-11-04 | エイエムエックス − オートマトリックス・ソチエタ・ア・レスポンサビリタ・リミタータAmx − Automatrix S.R.L. | 基板上の電子部品を焼結する焼結プレスのためのプレスグループ |
JP7442208B2 (ja) | 2018-07-02 | 2024-03-04 | エイエムエックス - オートマトリックス・ソチエタ・ア・レスポンサビリタ・リミタータ | 基板上の電子部品を焼結する焼結プレスのためのプレスグループ |
CN111816614A (zh) * | 2020-02-28 | 2020-10-23 | 浙江集迈科微电子有限公司 | 一种芯片贴装方式 |
Also Published As
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US20120058603A1 (en) | 2012-03-08 |
US8640943B2 (en) | 2014-02-04 |
US8074868B2 (en) | 2011-12-13 |
US7270258B2 (en) | 2007-09-18 |
JP4206320B2 (ja) | 2009-01-07 |
US7861912B2 (en) | 2011-01-04 |
US20050061856A1 (en) | 2005-03-24 |
US7757930B2 (en) | 2010-07-20 |
CN100435301C (zh) | 2008-11-19 |
US20100279464A1 (en) | 2010-11-04 |
US20110070696A1 (en) | 2011-03-24 |
US20070287262A1 (en) | 2007-12-13 |
CN101431036A (zh) | 2009-05-13 |
US8292159B2 (en) | 2012-10-23 |
KR20050029110A (ko) | 2005-03-24 |
US20120329211A1 (en) | 2012-12-27 |
CN1599047A (zh) | 2005-03-23 |
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