TWI673805B - 安裝裝置以及安裝系統 - Google Patents
安裝裝置以及安裝系統 Download PDFInfo
- Publication number
- TWI673805B TWI673805B TW107103097A TW107103097A TWI673805B TW I673805 B TWI673805 B TW I673805B TW 107103097 A TW107103097 A TW 107103097A TW 107103097 A TW107103097 A TW 107103097A TW I673805 B TWI673805 B TW I673805B
- Authority
- TW
- Taiwan
- Prior art keywords
- crimping
- laminated body
- tool
- temporary
- heat dissipating
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13075—Plural core members
- H01L2224/1308—Plural core members being stacked
- H01L2224/13082—Two-layer arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
- H01L2224/171—Disposition
- H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/17181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/731—Location prior to the connecting process
- H01L2224/73101—Location prior to the connecting process on the same surface
- H01L2224/73103—Bump and layer connectors
- H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
- H01L2224/75301—Bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/755—Cooling means
- H01L2224/75502—Cooling means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7565—Means for transporting the components to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75701—Means for aligning in the lower part of the bonding apparatus, e.g. in the apparatus chuck
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75702—Means for aligning in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75743—Suction holding means
- H01L2224/75745—Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/757—Means for aligning
- H01L2224/75753—Means for optical alignment, e.g. sensors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/758—Means for moving parts
- H01L2224/75801—Lower part of the bonding apparatus, e.g. XY table
- H01L2224/75804—Translational mechanism
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/758—Means for moving parts
- H01L2224/75821—Upper part of the bonding apparatus, i.e. bonding head
- H01L2224/75822—Rotational mechanism
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/759—Means for monitoring the connection process
- H01L2224/75901—Means for monitoring the connection process using a computer, e.g. fully- or semi-automatic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7598—Apparatus for connecting with bump connectors or layer connectors specially adapted for batch processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/818—Bonding techniques
- H01L2224/81801—Soldering or alloying
- H01L2224/81815—Reflow soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
- H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8313—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83862—Heat curing
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83905—Combinations of bonding methods provided for in at least two different groups from H01L2224/838 - H01L2224/83904
- H01L2224/83907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
- H01L2224/9221—Parallel connecting processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
Abstract
本發明提供一種在基板上的多個部位積層並安裝兩個以上的半導體晶片的安裝裝置,包括:第一安裝頭,在基板上的多個部位,形成以暫時壓接狀態將兩個以上的半導體晶片積層的暫時積層體;以及第二安裝頭,將形成於多個部位的暫時積層體依序正式壓接而形成晶片積層體。第二安裝頭包括:壓接工具,藉由將對象的暫時積層體的上表面一邊加熱一邊加壓,而一次性地將構成暫時積層體的兩個以上的半導體晶片正式壓接;以及一個以上的散熱工具,具有散熱體,散熱體藉由與位於對象的暫時積層體的周邊的其他積層體的上表面接觸而使其他積層體散熱。
Description
本發明是有關於一種在基板上的多個部位積層並安裝兩個以上的半導體晶片的安裝裝置以及安裝系統。
以前,要求半導體裝置的進一步的高功能化、小型化。因此,一部分提出積層並安裝多個半導體晶片。通常,在半導體晶片的單面設置著凸塊(bump)、及覆蓋該凸塊的非導電性膜(Non-conductive Film)(以下稱作「NCF」)。NCF包含熱硬化性樹脂,若小於規定的硬化開始溫度,則伴隨溫度上升而可逆地軟化,但若超過硬化開始溫度,則伴隨溫度上升而不可逆地硬化。提出有為了將該半導體晶片積層安裝,將多個半導體晶片一邊暫時壓接一邊積層,然後,對該暫時壓接狀態的積層體進行加熱加壓而進行正式壓接。另外,以下,將暫時壓接狀態的積層體稱作「暫時積層體」,正式壓接後的積層體稱作「晶片積層體」。而且,在無須區分暫時積層體及晶片積層體的情況下,可簡稱作「積層體」。根據此種技術,能夠以小面積安裝更多個半導體晶片,因此能夠實現進一步的高功能化、小型化。
[非專利文獻1]Noboru Asahi (朝日升)及另一名,“Heat Transfer Analysis in the Thermal compression Bonding for CoW Process(對於晶圓上晶片熱加壓接合的熱傳遞分析)”,ICEP 2016 Proceedings,p.640-643
且說,一般而言,在一個基板上安裝著多個晶片積層體。一部分提出如下技術,在安裝多個晶片積層體的情況下,在形成了多個暫時積層體後,將該多個暫時積層體依序正式壓接。根據該技術,與一個積層體的暫時壓接及正式壓接完成後進行下一個積層體的暫時壓接及正式壓接的情況相比,可減少暫時壓接處理與正式壓接處理的切換次數,因此能夠實現安裝步驟的進一步的簡易化、縮短化。
另一方面,在形成了多個暫時積層體後進行正式壓接的技術的情況下,為了正式壓接,附加至一個暫時積層體的熱有時亦會傳遞至周邊的其他暫時積層體。尤其在基板的導熱率高的情況下,附加至一個暫時積層體的正式壓接用的熱會高效率地傳遞至周邊的其他暫時積層體,而導致其他暫時積層體的溫度上升。該情況下,有在其他暫時積層體中產生NCF的不可逆的硬化之虞。若在正式壓接之前產生NCF的硬化,則會妨礙該半導體晶片與基板的適當的接合。
此處,非專利文獻1中提出如下技術:在對一個半導體
晶片正式壓接時,向其周邊的其他半導體晶片吹送冷卻風,藉此防止該其他半導體晶片的溫度上升,進而,防止NCF的硬化。然而,在利用冷卻風進行冷卻的情況下,存在不僅冷卻效率差,亦難以限制冷卻範圍的問題。結果,冷卻風的一部分不僅吹到冷卻對象的其他半導體晶片,亦吹到位於其附近的正在進行正式壓接的半導體晶片,從而有該正在進行正式壓接的半導體晶片的溫度降低,而導致安裝不良之虞。
因此,本發明的目的在於提供如下的安裝裝置以及安裝系統,即,在形成多個暫時的晶片積層體後在將這些暫時的晶片積層體依序正式壓接的情況下,可更適當地安裝各半導體晶片。
本發明的安裝裝置在基板上的多個部位積層並安裝兩個以上的半導體晶片,其特徵在於包括:暫時壓接頭,在所述基板上的多個部位,形成以暫時壓接狀態將兩個以上的半導體晶片積層的暫時積層體;以及正式壓接頭,將形成於所述多個部位的所述暫時積層體依序正式壓接而形成晶片積層體,所述正式壓接頭包括:壓接工具,藉由將對象的暫時積層體的上表面一邊加熱一邊加壓,而一次性地將構成該暫時積層體的兩個以上的半導體晶片正式壓接;以及一個以上的散熱工具,具有散熱體,所述散熱體藉由與位於所述對象的暫時積層體的周邊的其他積層體的上表面接觸而使所述其他積層體散熱。
根據所述構成,正式壓接時,可利用針點(pin point)
將位於其周邊的其他積層體冷卻,因此可防止正式壓接的積層體的溫度降低,且可防止正式壓接前的積層體中的NCF的硬化。
而且,所述正式壓接頭可進而包括供所述壓接工具及所述散熱工具安裝的基部,藉由所述基部升降,所述壓接工具及散熱工具聯動地升降。
根據所述構成,因可一體地控制壓接工具與散熱工具的升降,故可使控制簡化。
而且,該情況下,所述散熱工具亦可經由彈性體而安裝於所述基部,可在所述彈性體的彈性變形量的範圍內相對於所述基部升降。
藉由設為該構成,因可利用彈性體吸收積層體的高度的不均,故可使一個以上的散熱工具確實地與積層體接觸。
而且,該情況下,無負載狀態下的所述散熱工具的底面高度可低於所述壓接工具的底面高度。
若設為所述構成,則藉由降低可吸收積層體的高度的不均的散熱工具,而可使散熱工具及壓接工具的雙方確實地與積層體接觸。
而且,所述散熱體可藉由冷媒而冷卻。
藉由設為該構成,可更有效果地將位於周邊的其他積層體冷卻。
而且,所述正式壓接頭可具有一個所述壓接工具、及8個所述散熱工具,所述壓接工具與所述散熱工具以所述正式壓接
頭為中心配設成3列3行。
藉由設為該構成,可將正式壓接的積層體的整個周圍的積層體冷卻。
本發明的安裝系統在基板上的多個部位積層並安裝兩個以上的半導體晶片,其特徵在於包括:暫時壓接裝置,在所述基板上的多個部位,形成以暫時壓接狀態將兩個以上的半導體晶片積層的暫時積層體;以及正式壓接裝置,藉由所述暫時壓接裝置將形成於所述多個部位的所述暫時積層體依序正式壓接而形成晶片積層體,所述正式壓接裝置包括:壓接工具,藉由將對象的暫時積層體的上表面一邊加熱一邊加壓,而一次性地將構成該暫時積層體的兩個以上的半導體晶片正式壓接;以及一個以上的散熱工具,具有散熱體,所述散熱體藉由與位於所述對象的暫時積層體的周邊的其他積層體的上表面接觸而使所述其他積層體散熱。
根據本發明,在進行正式壓接時,可利用針點將位於其周邊的其他積層體冷卻,因此可防止正式壓接的積層體的溫度降低,且可防止正式壓接前的積層體中的NCF的硬化。
10‧‧‧半導體晶片
14、16‧‧‧電極端子
18‧‧‧凸塊
20‧‧‧非導電性膜(NCF)
30‧‧‧基板
32‧‧‧電極
34‧‧‧配置區域
100‧‧‧安裝裝置
102‧‧‧晶片供給單元
104‧‧‧晶片搬送單元
106‧‧‧接合單元
110‧‧‧突起部
114‧‧‧晶粒撿取器
116‧‧‧移送頭
118‧‧‧旋轉台
120‧‧‧載台
124‧‧‧第一安裝頭
126‧‧‧第二安裝頭
128‧‧‧控制單元
130‧‧‧壓接工具
131‧‧‧加熱器
132‧‧‧散熱工具
134‧‧‧散熱體
136‧‧‧柱體
138‧‧‧彈性體
139d、139u‧‧‧凸緣
140‧‧‧基部
A’‧‧‧箭頭
A~C‧‧‧區域
P、Q‧‧‧配置間距
Ra、Rb‧‧‧旋轉軸
ST‧‧‧積層體
STc‧‧‧晶片積層體
STt‧‧‧暫時積層體
T2‧‧‧第二溫度
TC1~TC3‧‧‧溫度
TE‧‧‧切割膠帶
圖1是表示作為本發明的實施形態的安裝裝置的構成的圖。
圖2是表示基板的一例的圖。
圖3是表示半導體晶片的構成的圖。
圖4是表示半導體裝置的構成的圖。
圖5是表示現有技術中的正式壓接的情況的圖。
圖6是表示第二安裝頭的構成的圖。
圖7是表示自底面側觀察第二安裝頭的圖。
圖8是表示本實施形態中的正式壓接的情況的圖。
圖9是表示實驗條件的圖。
圖10是表示條件1、條件2中的測定結果的圖。
圖11是表示條件3、條件4中的測定結果的圖。
圖12是表示正式壓接的進行順序的一例的圖。
圖13是表示另一第二安裝頭的一例的圖。
以下,參照圖式對本發明的實施形態進行說明。圖1是作為本發明的實施形態的安裝裝置100的概略構成圖。該安裝裝置100是在基板30之上安裝半導體晶片10的裝置。該安裝裝置100設為尤其適合於積層並安裝多個半導體晶片10的情況的構成。另外,以下的說明中,將積層多個半導體晶片10而成者稱作「積層體ST」,進而將該「積層體ST」中的多個半導體晶片10為暫時壓接狀態者稱作「暫時積層體STt」,將多個半導體晶片10為正式壓接狀態者稱作「晶片積層體STc」而加以區分。
安裝裝置100具備晶片供給單元102、晶片搬送單元104、接合單元106及控制該些的驅動的控制單元128。晶片供給
單元102是自晶片供給源取出半導體晶片10並供給至晶片搬送單元104的部位。該晶片供給單元102具備突起部110及晶粒撿取器(die picker)114及移送頭116。
晶片供給單元102中,多個半導體晶片10載置於切割膠帶(dicing tape)TE上。此時半導體晶片10將凸塊18以朝向上側的面朝上(face up)狀態載置。突起部110僅使該多個半導體晶片10中的一個半導體晶片10保持面朝上狀態而向上方突起。晶粒撿取器114利用其下端對因突起部110而突起的半導體晶片10進行抽吸保持並接收。已接收半導體晶片10的晶粒撿取器114以該半導體晶片10的凸塊18朝向下方的方式,亦即,以半導體晶片10為面朝下(face down)的狀態的方式,當場旋轉180度。若成為該狀態,則移送頭116自晶粒撿取器114接收半導體晶片10。
移送頭116能夠於上下方向及水平方向上移動,可利用其下端吸附保持半導體晶片10。若晶粒撿取器114旋轉180度,半導體晶片10成為面朝下狀態,則移送頭116利用其下端吸附保持該半導體晶片10。然後,移送頭116於水平方向及上下方向上移動,向晶片搬送單元104移動。
晶片搬送單元104具有以鉛垂的旋轉軸Ra為中心而旋轉的旋轉台118。移送頭116將半導體晶片10載置於旋轉台118的規定位置。藉由載置半導體晶片10的旋轉台118以旋轉軸Ra為中心旋轉,而該半導體晶片10被搬送至位於晶片供給單元102
的相反側的接合單元106。
接合單元106具備對支持基板30的載台120或半導體晶片10進行暫時壓接的第一安裝頭124(暫時壓接頭)、及對半導體晶片10進行正式壓接的第二安裝頭126(正式壓接頭)等。載台120能夠於水平方向上移動,對所載置的基板30與安裝頭124、安裝頭126的相對位置關係進行調整。而且,該載台120中內置加熱器,可自下側加熱半導體晶片10。
第一安裝頭124可於其下端保持半導體晶片10,而且,能夠進行繞鉛垂的旋轉軸Rb的旋轉、及升降。而且,第一安裝頭124中內置加熱器(未圖示),被加熱至規定的第一溫度T1。第一安裝頭124作為將半導體晶片10暫時壓接至基板或其他半導體晶片10之上的暫時壓接頭發揮功能。
第二安裝頭126能夠升降。而且,第二安裝頭126中內置加熱器(未圖示),被加熱至高於第一溫度T1的第二溫度T2。第二安裝頭126作為正式壓接頭發揮功能,該正式壓接頭藉由將經暫時壓接的半導體晶片10以第二溫度T2一邊加熱一邊加壓,而將該些半導體晶片10正式壓接。此處,本實施形態的第二安裝頭126除具有與對象的半導體晶片10(更準確地說暫時積層體STt)接觸而進行加熱、加壓的一個壓接工具130之外,進而具有配置於該壓接工具130的周圍的多個散熱工具132。關於該壓接工具130或散熱工具132的具體構成將於以後進行詳細說明。
在第一安裝頭124、第二安裝頭126的附近設置著相機
(未圖示)。對基板30及半導體晶片10分別附上成為定位基準的對準標記。相機對基板30及半導體晶片10進行攝像以使得該對準標記映出。控制單元128基於該攝像所獲得的圖像資料,而掌握基板30及半導體晶片10的相對位置關係,且視需要對第一安裝頭124的繞軸Rb的旋轉角度及載台120的水平位置進行調整。控制單元128控制各單元的驅動,例如具備進行各種運算的中央處理單元(Central Processing Unit,CPU)、記憶各種資料或程式的記憶部。
接下來,對利用該安裝裝置100製造的半導體裝置進行說明。本實施形態中,使用半導體晶圓作為基板30,在該半導體晶圓(基板30)之上積層安裝多個半導體晶片10。因此,本實施形態的安裝製程是在半導體晶圓的電路形成面,積層安裝半導體晶片10的「晶圓上晶片(chip on wafer)製程」。圖2是本實施形態中使用的基板30(半導體晶圓)的概略概念圖。作為半導體晶圓的基板30主要包含矽,與包含樹脂或玻璃的普通的電路基板相比,熱傳遞係數高。如圖2所示,在基板30設定著呈格子狀並列的多個配置區域34。各配置區域34積層安裝著多個半導體晶片10。配置區域34以規定的配置間距P配設。該配置間距P的值可根據安裝對象的半導體晶片10的尺寸等而適當設定。而且,本實施形態中,將配置區域34設為大致正方形,但亦可適當地設為其他形狀,例如大致長方形。
接下來,對半導體晶片10的構成進行簡單說明。圖3
是表示所安裝的半導體晶片10的概略構成的圖。在半導體晶片10的上下表面形成著電極端子14、電極端子16。而且,在半導體晶片10的單面,與電極端子14相連而形成著凸塊18。凸塊18包含導電性金屬,以規定的熔融溫度Tm而熔融。
而且,在半導體晶片10的單面,以覆蓋凸塊18的方式貼附著非導電性膜(以下稱作「NCF」)20。NCF 20作為將半導體晶片10與基板30或其他半導體晶片10黏接的黏接劑而發揮功能,包含非導電性的熱硬化性樹脂,例如聚醯亞胺樹脂、環氧樹脂、丙烯酸系樹脂、苯氧樹脂、聚醚碸樹脂等。該NCF 20的厚度大於凸塊18的平均高度,凸塊18由該NCF 20大致完全覆蓋。NCF 20在常溫下為固體的膜,但若超過規定的軟化開始溫度Ts,則會逐漸可逆地軟化而發揮流動性,若超過規定的硬化開始溫度Tt,則會不可逆地開始硬化。
此處,軟化開始溫度Ts低於凸塊18的熔融溫度Tm及硬化開始溫度Tt。暫時壓接用的第一溫度T1高於該軟化開始溫度Ts,且低於熔融溫度Tm及硬化開始溫度Tt。而且,正式壓接用的第二溫度T2高於熔融溫度Tm及硬化開始溫度Tt。亦即,Ts<T1<(Tm、Tt)<T2。
在將半導體晶片10暫時壓接至基板30或下側的半導體晶片10(以下稱作「下層的晶片等」)時,將第一安裝頭124加熱至第一溫度T1後將半導體晶片10壓抵至下層的晶片等而進行加壓。此時,半導體晶片10的NCF 20藉由利用來自第一安裝頭124
的傳熱被加熱至軟化開始溫度Ts以上而軟化,從而具有流動性。而且,藉此,NCF 20流入至半導體晶片10與下層的晶片等的間隙,從而可確實地填埋該間隙。
在將半導體晶片10正式壓接時,將第二安裝頭126加熱至第二溫度T2後,對半導體晶片10進行加壓。此時,半導體晶片10的凸塊18及NCF 20利用來自第二安裝頭126的傳熱而被加熱至硬化開始溫度Tt及熔融溫度Tm以上。藉此,凸塊18熔融,可熔接至對向的下層的晶片等。而且,利用該加熱,NCF 20以填埋半導體晶片10與下層的晶片等的間隙的狀態硬化,因此將半導體晶片10與下層牢固地固定。
圖4是表示在基板30上的電極32積層安裝多個半導體晶片10的半導體裝置的構成的圖。半導體裝置在多個配置區域34(圖示例中為區域A~區域C)分別配置著積層安裝有目標積層數的半導體晶片10的晶片積層體STc。本實施形態中,將目標積層數設為「4」,在一個配置區域34安裝著包含4個半導體晶片10的晶片積層體STc。
此種半導體裝置按照如下的順序製造。首先,使用第一安裝頭124,形成多個一邊暫時壓接半導體晶片10一邊積層而成的暫時積層體STt。圖4的例中,只要可在區域A形成暫時積層體STt,則繼而在區域B形成暫時積層體STt,進而,然後在區域C形成暫時積層體STt。
只要可在全部的配置區域34形成暫時積層體STt,則接
下來將該暫時積層體STt依序正式壓接。亦即,使用已加熱至第二溫度T2的第二安裝頭126,將對象的暫時積層體STt的上表面一邊加熱一邊加壓,一次性地對構成該對象的暫時積層體STt的多個(本例中4個)半導體晶片10進行正式壓接。藉此,暫時積層體STt變為將構成其的半導體晶片10正式壓接而成的晶片積層體STc。只要可正式壓接一個暫時積層體STt(只要變為晶片積層體STc),則繼而會對下一個暫時積層體STt進行正式壓接。然後,只要可將全部的暫時積層體STt正式壓接,則製造製程結束。
如此,在形成了多個暫時積層體STt後進行正式壓接的方法的情況下,與形成一個暫時積層體STt後進行正式壓接的方法相比,可減少安裝頭的切換次數等,因此可減少安裝處理整體的處理時間。另一方面,在形成了多個暫時積層體STt後進行正式壓接的方法的情況下,存在如下問題,即,在成為正式壓接的對象的暫時積層體STt以外的暫時積層體STt中,NCF 20不可逆地硬化。關於該情況將參照圖5進行說明。圖5是表示現有技術中的正式壓接的情況的概念圖。
如已述般,在將一個暫時積層體STt正式壓接而變為晶片積層體STc的情況下,利用正式壓接用的安裝頭對該暫時積層體STt的上表面一邊加熱一邊加壓。現有的安裝裝置中,如圖5所示,正式壓接用的安裝頭僅具有對暫時積層體STt一邊加熱一邊加壓的壓接工具130,而不具有使周邊的暫時積層體STt散熱的散熱工具132。
考慮如下情況:使用此種現有的安裝裝置在區域A、區域B、區域C中形成了暫時積層體STt後,對正中的區域B的暫時積層體STt進行正式壓接。該情況下,使用壓接工具130對區域B的暫時積層體STt一邊加熱一邊加壓。此時,關於壓接工具130的溫度即第二溫度T2,被設定為最下層的半導體晶片10要高於NCF 20的硬化開始溫度Tt及凸塊18的熔融溫度Tm。而且,藉由以該第二溫度T2加熱,對象的暫時積層體STt(圖5中的區域B的暫時積層體STt)的凸塊18熔融,而且,NCF 20不可逆地開始硬化。
此處,自壓接工具130賦予的熱如圖5中粗線箭頭所示般,不僅傳遞至作為正式壓接對象的區域B的暫時積層體STt,亦經由基板30傳遞至鄰接的區域A或區域C的暫時積層體STt。尤其,在如基板30為半導體晶圓般導熱性高的情況下,在鄰接的暫時積層體STt中,熱被高效率地傳遞。結果,並非為正式壓接對象的鄰接的暫時積層體STt亦會被加熱至NCF 20的硬化開始溫度Tt以上,從而有在正式壓接前該些區域A、區域C的暫時積層體STt的NCF 20不可逆地硬化之虞。若正式壓接前NCF 20硬化,則會導致半導體晶片10的安裝不良。而且,亦充分考慮在未加熱至硬化開始溫度Tt以上的情況下,NCF 20所含的硬化劑的反應亦會開始,該情況下,難以獲得NCF 20本來的特性。
因此,本實施形態中,為了防止正式壓接對象的暫時積層體STt以外的其他暫時積層體STt的NCF 20的硬化,在第二安
裝頭126不僅設置壓接工具130,亦設置散熱工具132。關於該情況將參照圖6、圖7進行說明。圖6是表示第二安裝頭126的概略構成的圖。而且,圖7是自底側觀察第二安裝頭126的圖。
第二安裝頭126具備基部140、及安裝於該基部140的壓接工具130及散熱工具132。基部140安裝於未圖示的升降機構,根據來自控制單元128的指示而升降。
壓接工具130壓抵至正式壓接對象的暫時積層體STt的上表面,藉此,對該暫時積層體STt一邊加壓一邊加熱。該壓接工具130在內部設置著加熱器131,加熱至規定的第二溫度T2。壓接工具130的上端固接於基部140,從而壓接工具130對基部140的位置不變。
以壓接工具130為中心而向其周圍的八個方向設置著散熱工具132。圖7中,中空的四邊形表示散熱工具132,附影線的四邊形表示壓接工具130。如該圖7所示,第二安裝頭126具有一個壓接工具130及八個散熱工具132,該些工具以一個壓接工具130為中心而呈3列3行排列。壓接工具130及散熱工具132的配置間距Q與積層體ST的配置間距P相同。因此,壓接工具130與一個積層體ST接觸時,與該壓接工具130鄰接的散熱工具132會與和一個積層體ST鄰接的其他積層體ST接觸。
散熱工具132使正式壓接對象以外的其他積層體ST散熱而冷卻。該散熱工具132的下端設置著散熱體134。散熱體134是導熱率高的材料,例如是包含銅或鋁等的塊狀構件。該散熱體
134作為散熱器(heat sink)發揮功能,該散熱器與位於作為正式壓接對象的暫時積層體STt的周圍的其他積層體ST的上表面接觸,使該其他積層體ST的熱釋放。自其他積層體ST傳遞至散熱體134的熱向外部氣體或後述的柱體136等放出。
另外,圖6中,是將散熱體134設為單純的長方體形狀,但散熱體134的形狀亦可適當變更。例如,為了提高散熱體134的散熱效率,亦可在該散熱體134的上表面或側面設置多個翼片(fin)或肋(rib)、突起。而且,為了提高散熱體134的冷卻性能,亦可使用冷媒將該散熱體134冷卻。亦即,亦可設置與散熱體134的內外連通的冷媒路徑,使液體或氣體的冷媒在該冷媒路徑循環。而且,作為其他形態,亦可使用熱管等將散熱體134的熱移送至散熱體的外部。而且,作為另一形態,亦可使用帕耳帖(Peltier)元件等將散熱體134冷卻。任一情況下,散熱體134的底面,亦即,與積層體ST的接觸面理想的是平面,以能夠與積層體ST的整個上表面接觸。另外,為了防止壓接工具130的溫度降低,理想的是在壓接工具130與散熱工具132之間設置某些隔熱構件(未圖示)。
散熱體134經由彈性體138而安裝於基部140,可在該彈性體138的彈性變形量的範圍內,相對於基部140升降。關於經由該彈性體138的安裝方法可考慮各種方法,本實施形態中,如圖6所示,向貫通基部140的貫通孔中插通柱體136,並且在該柱體136中的隔著基部140的兩側設置著直徑比貫通孔大的凸緣
139u、凸緣139d。而且,在基部140的底面與下側的凸緣139d之間配置作為彈性體138的壓縮彈簧。壓縮彈簧在無負載狀態下,將下側的凸緣139d,進而將散熱體134向下方施壓。另一方面,在散熱體134受到向上的力作為該散熱體134按壓積層體ST時的反作用力的情況下,壓縮彈簧壓縮變形,藉此散熱體134向靠近基部140的方向移位。
如此,散熱工具132經由彈性體138安裝於基部140,藉此可吸收每個積層體ST的高度之差,八個散熱體134可全部密接於對應的積層體ST的上表面。另外,為了使散熱體134確實地密接於對應的積層體ST,無負載狀態(無彈性體的變形的狀態)下的散熱體134的底面高度理想的是低於壓接工具130的底面高度(離開基部140)。而且,彈性體138理想的是其彈簧常數被調整,以使得在作為暫時壓接用的荷重的第一荷重F1以下能夠彈性變形。
接下來,參照圖8對使用此種第二安裝頭126的正式壓接進行說明。圖8是表示使用本實施形態的第二安裝頭126進行正式壓接的情況的概念圖。圖8的例中,在區域A~區域C形成暫時積層體STt後,將正中的區域B的暫時積層體STt正式壓接。該情況下,使壓接工具130下降,壓抵至作為正式壓接對象的區域B的暫時積層體STt的上表面。藉此,區域B的暫時積層體STt一邊被加熱一邊被加壓。若為了使壓接工具130下降,而使基部140下降,則當然安裝於該基部140的散熱工具132亦與基部140
及壓接工具130聯動地下降。而且,藉此,散熱工具132與和正式壓接對象的暫時積層體STt鄰接的區域A、區域C的暫時積層體STt的上表面接觸。
因此,通常,在多個暫時積層體STt產生若干的高度的不均。例如,圖8的例中,區域A的暫時積層體STt高於其他暫時積層體STt。該情況下,在散熱工具132對基部140的位置不變的情況下,亦即,未設置彈性體138的情況下,存在如下問題:在區域A,散熱工具132與暫時積層體STt接觸後,區域B、區域C中,壓接工具130、散熱工具132無法與對應的暫時積層體STt接觸。本實施形態中,各散熱工具132經由彈性體138而安裝於基部140,能夠相對於基部140移位。因此,一個散熱工具132與暫時積層體STt接觸後,若使基部140繼續下降,該一個散熱工具132的彈性體138變形,容許其他散熱工具132、壓接工具130的進一步的下降。結果,散熱工具132及多個壓接工具130可確實地與對應的積層體ST接觸。另外,此時,若彈性體138的彈簧常數大,則彈性體138變形時過大的力施加至區域A的暫時積層體STt。因此,彈性體138的彈簧常數以其變形所需的荷重為用以暫時壓接的荷重F1以下的方式調整。
如此,本實施形態中,在對區域B的暫時積層體STt進行正式壓接時,使散熱工具132與和該區域B鄰接的區域A、區域C的暫時積層體STt接觸。該情況下,壓接工具130的熱如圖8中粗線箭頭所示,經由區域B的暫時積層體STt及基板30而傳
遞至區域A、區域C的暫時積層體STt。然而,本實施形態中,傳熱性優異的散熱體134與該區域A、區域C的暫時積層體STt的上表面接觸。已傳遞至區域A、區域C的暫時積層體STt的熱在向該散熱體134放出後,向外部放出。結果,作為非正式壓接對象的區域A、區域C的暫時積層體STt的溫度上升得以有效率地抑制。而且,藉此,可防止區域A、區域C的暫時積層體STt的NCF 20在正式壓接前硬化,從而可有效果地防止半導體晶片10的安裝不良。
此處,作為積層體ST的冷卻方法,如本實施形態般,除使高傳熱性的固體(散熱體134)接觸的方法之外,亦考慮使冷風或液體等流體直接吹到積層體ST的方法。然而,此種流體難以限制其適用範圍,從而有甚至會將本來不欲冷卻的正式壓接對象的暫時積層體STt冷卻之虞。若正式壓接對象的暫時積層體STt被冷卻,則NCF 20會硬化不充分,或凸塊18會熔融不充分,仍然有導致安裝不良之虞。另一方面,根據使散熱體134接觸而散熱的本實施形態的技術,可確實地僅將欲冷卻的積層體ST冷卻,可抑制欲加熱的暫時積層體STt的溫度降低。結果,根據本實施形態,可有效果地防止溫度不足引起的安裝不良或正式壓接前的NCF 20硬化引起的安裝不良。
接下來,對關於散熱體134達成的冷卻效果的實驗結果進行說明。圖9是表示實驗條件的圖。而且,圖10、圖11是表示實驗結果的圖。實驗中,使用壓接工具130對一個半導體晶片10
進行加熱加壓。然後,測定此時的半導體晶片10的底面的溫度TC1、及與該一個半導體晶片10鄰接設置的積層體ST的最下層的底面溫度TC2及最上層的底面溫度TC3。條件1及條件2在使用樹脂基板作為基板30的方面共通,但條件1中未使用散熱工具132,與此相對,條件2中,使用散熱工具132將積層體ST冷卻,就該方面而言不同。條件3及條件4在使用玻璃基板作為基板30的方面共通,但條件3中,未使用散熱工具132,與此相對,條件4中,使用散熱工具132將積層體ST冷卻,就該方面而言不同。
圖10中的中空條表示條件1中的各測定溫度TC1~TC3,塗黑條表示條件2中的各測定溫度TC1~TC3。而且,圖11中的中空條表示條件3中的各測定溫度TC1~TC3,塗黑條表示條件4中的各測定溫度TC1~TC3。如根據圖10、圖11可知,利用壓接工具130加熱的半導體晶片10的溫度TC1在條件1、條件3(中空條)及條件2、條件4(塗黑條)中無較大差異,即便有散熱工具132,對正式壓接的不良影響亦少。另一方面,在使用散熱工具132的條件2、條件4(塗黑條)中,與未使用散熱工具132的條件1、條件3(中空條)相比,鄰接的積層體ST的溫度TC2、溫度TC3降低。即,根據使用散熱工具132的本實施形態,可知能夠抑制與正式壓接對象的積層體ST鄰接的積層體ST的溫度上升,該鄰接的積層體ST即便在正式壓接前,亦可有效果地防止NCF 20的硬化等。另一方面,即便使用散熱工具132,亦可防止正式壓接對象的半導體晶片10的溫度降低,因此可確實地將各半
導體晶片10正式壓接。
另外,至此說明的構成為一例,只要正式壓接用的安裝頭(第二安裝頭126)具備將暫時積層體STt加熱加壓的壓接工具130、及使與該暫時積層體STt鄰接的其他積層體ST散熱的散熱工具132,則其他構成亦可適當變更。例如,本實施形態中,設為壓接工具130與散熱工具132一體地升降的構成,但壓接工具130與散熱工具132亦可彼此獨立地升降。
而且,本實施形態中,將散熱工具132設置於壓接工具130的周圍八個方向,但不必設置於八個方向。例如,使暫時積層體STt的正式壓接如圖12的箭頭A’所示,考慮針對各列交替重複地進行向右方向依序前進的步驟與向左方向依序前進的步驟的情況。該情況下,在較正式壓接的暫時積層體STt靠圖式下側處無積屬體ST,或者,即便有積層體ST,正式壓接已完成。該情況下,在較壓接工具130靠圖式下側處不需要散熱工具132。因此,該情況下,如圖13所示,亦可僅在壓接工具130的左右兩側及圖式上側的三個部位的合計五處設置散熱工具132。
而且,壓接工具130與散熱工具132的配設間隔亦可根據配置區域的配置間距P而適當變更。而且,本實施形態中,分別設置著暫時壓接用的安裝頭(第一安裝頭124)與正式壓接用的安裝頭(第二安裝頭126),也可利用一個安裝頭進行暫時壓接及正式壓接。亦即,亦可無第一安裝頭124,利用第二安裝頭126進行暫時壓接及正式壓接。此處,暫時壓接時,不需要散熱工具
132,因此執行暫時壓接時,亦可自第二安裝頭126卸除散熱工具132。
而且,至此為止的說明中,是在單個裝置內設置暫時壓接用的安裝頭(第一安裝頭124)及正式壓接用的安裝頭(第二安裝頭126),但該些亦可分別設置於不同的裝置。亦即,本申請案中揭示的技術可應用於如下安裝系統中,即,包括具備暫時壓接用的安裝頭的暫時壓接裝置、及具備正式壓接用的安裝頭的正式壓接裝置。
Claims (8)
- 一種安裝裝置,在基板上的多個部位積層並安裝兩個以上的半導體晶片,其特徵在於包括:暫時壓接頭,在所述基板上的多個部位,形成以暫時壓接狀態將所述兩個以上的半導體晶片積層的暫時積層體;以及正式壓接頭,將形成於所述多個部位的所述暫時積層體依序正式壓接而形成晶片積層體;並且所述正式壓接頭包括:壓接工具,藉由將對象的所述暫時積層體的上表面一邊加熱一邊加壓,而一次性地將構成所述暫時積層體的所述兩個以上的半導體晶片正式壓接;以及一個以上的散熱工具,具有散熱體,所述散熱體藉由與位於所述對象的所述暫時積層體的周邊的其他積層體的上表面接觸而使所述其他積層體散熱。
- 如申請專利範圍第1項所述的安裝裝置,其中所述正式壓接頭進而包括供所述壓接工具及所述散熱工具安裝的基部,藉由所述基部升降,所述壓接工具及所述散熱工具聯動地升降。
- 如申請專利範圍第2項所述的安裝裝置,其中所述散熱工具經由彈性體而安裝於所述基部,可在所述彈性體的彈性變形量的範圍內相對於所述基部升降。
- 如申請專利範圍第3項所述的安裝裝置,其中無負載狀態下的所述散熱工具的底面高度低於所述壓接工具的底面高度。
- 如申請專利範圍第1項至第4項中任一項所述的安裝裝置,其中所述散熱體藉由冷媒而冷卻。
- 如申請專利範圍第1項至第4項中任一項所述的安裝裝置,其中所述正式壓接頭具有一個所述壓接工具、及8個所述散熱工具,所述壓接工具與所述散熱工具以所述正式壓接頭為中心配設成3列3行。
- 如申請專利範圍第5項所述的安裝裝置,其中所述正式壓接頭具有一個所述壓接工具、及8個所述散熱工具,所述壓接工具與所述散熱工具以所述正式壓接頭為中心配設成3列3行。
- 一種安裝系統,在基板上的多個部位積層並安裝兩個以上的半導體晶片,其特徵在於包括:暫時壓接裝置,在所述基板上的多個部位,形成以暫時壓接狀態將所述兩個以上的半導體晶片積層的暫時積層體;以及正式壓接裝置,藉由所述暫時壓接裝置將形成於所述多個部 位的所述暫時積層體依序正式壓接而形成晶片積層體;並且所述正式壓接裝置包括:壓接工具,藉由將對象的所述暫時積層體的上表面一邊加熱一邊加壓,而一次性地將構成所述暫時積層體的所述兩個以上的半導體晶片正式壓接;以及一個以上的散熱工具,具有散熱體,所述散熱體藉由與位於所述對象的所述暫時積層體的周邊的其他積層體的上表面接觸而使所述其他積層體散熱。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2017014756 | 2017-01-30 | ||
JP2017-014756 | 2017-01-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201841272A TW201841272A (zh) | 2018-11-16 |
TWI673805B true TWI673805B (zh) | 2019-10-01 |
Family
ID=62978469
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW107103097A TWI673805B (zh) | 2017-01-30 | 2018-01-29 | 安裝裝置以及安裝系統 |
Country Status (6)
Country | Link |
---|---|
US (1) | US11545462B2 (zh) |
JP (1) | JP6732262B2 (zh) |
KR (1) | KR102210623B1 (zh) |
CN (1) | CN110476236B (zh) |
TW (1) | TWI673805B (zh) |
WO (1) | WO2018139670A1 (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI822377B (zh) * | 2022-07-26 | 2023-11-11 | 日商山葉發動機股份有限公司 | 表面安裝機及表面安裝方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6349539B2 (ja) * | 2016-09-30 | 2018-07-04 | 株式会社新川 | 半導体装置の製造方法および実装装置 |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006049739A (ja) * | 2004-08-09 | 2006-02-16 | Sony Chem Corp | 電気素子の接続方法及び加熱ヘッド |
US20110065239A1 (en) * | 2009-09-11 | 2011-03-17 | Kabushiki Kaisha Toshiba | Method of fabricating a semiconductor device and semiconductor production equipment |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3393562B2 (ja) * | 1994-05-13 | 2003-04-07 | ソニー株式会社 | 熱圧着装置 |
JPH11121921A (ja) * | 1997-10-09 | 1999-04-30 | Fuji Electric Co Ltd | 電子部品のはんだ付け方法および装置 |
US6821381B1 (en) * | 1999-03-16 | 2004-11-23 | Toray Engineering Co., Ltd. | Tool for thermo-compression-bonding chips, and chip packaging device having the same |
JP4425609B2 (ja) * | 2003-02-19 | 2010-03-03 | キヤノンマシナリー株式会社 | チップマウント方法および装置 |
JP4233905B2 (ja) | 2003-03-26 | 2009-03-04 | Juki株式会社 | 部品装着装置 |
JP2004343042A (ja) | 2003-04-25 | 2004-12-02 | Nippon Steel Chem Co Ltd | 電子装置の製造方法 |
JP4206320B2 (ja) * | 2003-09-19 | 2009-01-07 | 株式会社ルネサステクノロジ | 半導体集積回路装置の製造方法 |
CH698844B1 (de) * | 2007-06-22 | 2009-11-13 | Oerlikon Assembly Equipment Ag | Vorrichtung zum Anpressen von auf einem Substrat angeordneten Halbleiterchips. |
US8278142B2 (en) * | 2008-05-22 | 2012-10-02 | Texas Instruments Incorporated | Combined metallic bonding and molding for electronic assemblies including void-reduced underfill |
JP2010245412A (ja) * | 2009-04-09 | 2010-10-28 | Renesas Electronics Corp | 半導体集積回路装置の製造方法 |
JP2010267771A (ja) | 2009-05-14 | 2010-11-25 | Canon Machinery Inc | 電子部品実装装置及び電子部品実装方法 |
JP2011009357A (ja) * | 2009-06-24 | 2011-01-13 | Fujitsu Ltd | 実装装置 |
JP2011109046A (ja) | 2009-11-20 | 2011-06-02 | Sony Chemical & Information Device Corp | 実装装置および電子モジュールの製造方法 |
JP5608545B2 (ja) * | 2010-12-24 | 2014-10-15 | デクセリアルズ株式会社 | 熱圧着ヘッド、実装装置及び実装方法 |
US20130032270A1 (en) * | 2011-08-01 | 2013-02-07 | Texas Instruments Incorporated | Thermal compression bonding with separate bond heads |
JP2014007328A (ja) * | 2012-06-26 | 2014-01-16 | Shibuya Kogyo Co Ltd | ボンディング装置 |
JP6064388B2 (ja) * | 2012-06-28 | 2017-01-25 | 澁谷工業株式会社 | ボンディングヘッド |
CH707480B1 (de) * | 2013-01-21 | 2016-08-31 | Besi Switzerland Ag | Bondkopf mit einem heiz- und kühlbaren Saugorgan. |
US9093549B2 (en) * | 2013-07-02 | 2015-07-28 | Kulicke And Soffa Industries, Inc. | Bond heads for thermocompression bonders, thermocompression bonders, and methods of operating the same |
JP6234277B2 (ja) * | 2014-03-05 | 2017-11-22 | 東レエンジニアリング株式会社 | 圧着ヘッド、それを用いた実装装置および実装方法 |
KR20170076652A (ko) * | 2014-08-25 | 2017-07-04 | 토레이 엔지니어링 컴퍼니, 리미티드 | 실장용 헤드 및 그것을 사용한 실장 장치 |
KR102429619B1 (ko) * | 2015-11-18 | 2022-08-04 | 삼성전자주식회사 | 본딩 스테이지와 이를 포함하는 본딩 장치 |
JP6349540B2 (ja) * | 2016-10-06 | 2018-07-04 | 株式会社新川 | 半導体チップの実装装置、および、半導体装置の製造方法 |
-
2018
- 2018-01-29 TW TW107103097A patent/TWI673805B/zh active
- 2018-01-30 WO PCT/JP2018/002950 patent/WO2018139670A1/ja active Application Filing
- 2018-01-30 US US16/486,155 patent/US11545462B2/en active Active
- 2018-01-30 CN CN201880020250.8A patent/CN110476236B/zh active Active
- 2018-01-30 KR KR1020197025082A patent/KR102210623B1/ko active IP Right Grant
- 2018-01-30 JP JP2018564706A patent/JP6732262B2/ja active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006049739A (ja) * | 2004-08-09 | 2006-02-16 | Sony Chem Corp | 電気素子の接続方法及び加熱ヘッド |
US20110065239A1 (en) * | 2009-09-11 | 2011-03-17 | Kabushiki Kaisha Toshiba | Method of fabricating a semiconductor device and semiconductor production equipment |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI822377B (zh) * | 2022-07-26 | 2023-11-11 | 日商山葉發動機股份有限公司 | 表面安裝機及表面安裝方法 |
Also Published As
Publication number | Publication date |
---|---|
KR20190109501A (ko) | 2019-09-25 |
CN110476236B (zh) | 2023-08-25 |
JP6732262B2 (ja) | 2020-07-29 |
WO2018139670A1 (ja) | 2018-08-02 |
JPWO2018139670A1 (ja) | 2019-12-26 |
US11545462B2 (en) | 2023-01-03 |
TW201841272A (zh) | 2018-11-16 |
KR102210623B1 (ko) | 2021-02-02 |
CN110476236A (zh) | 2019-11-19 |
US20200235070A1 (en) | 2020-07-23 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI652743B (zh) | 半導體晶片的封裝裝置以及半導體裝置的製造方法 | |
US9460983B2 (en) | Joining structure using thermal interface material | |
US8377745B2 (en) | Method of forming a semiconductor device | |
TWI670776B (zh) | 半導體裝置的製造方法以及封裝裝置 | |
TWI662671B (zh) | 接合裝置 | |
US9449949B2 (en) | Method for manufacturing semiconductor device and semiconductor device | |
US8811031B2 (en) | Multichip module and method for manufacturing the same | |
TW201802975A (zh) | 安裝裝置及安裝方法 | |
TWI673805B (zh) | 安裝裝置以及安裝系統 | |
TWI748106B (zh) | 熱壓接合尖端及相關裝置與方法 | |
TWI659479B (zh) | 半導體裝置的製造方法以及封裝裝置 | |
TWI607516B (zh) | Semiconductor device manufacturing method and manufacturing apparatus | |
US11848301B2 (en) | Method of manufacturing a semiconductor package | |
TWI283465B (en) | Structure of flip chip package | |
JPH11340619A (ja) | フリップチップ実装装置及びその製造方法 |