TWI670776B - 半導體裝置的製造方法以及封裝裝置 - Google Patents
半導體裝置的製造方法以及封裝裝置 Download PDFInfo
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- TWI670776B TWI670776B TW106133089A TW106133089A TWI670776B TW I670776 B TWI670776 B TW I670776B TW 106133089 A TW106133089 A TW 106133089A TW 106133089 A TW106133089 A TW 106133089A TW I670776 B TWI670776 B TW I670776B
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- wafer
- semiconductor
- crimping
- semiconductor wafers
- semiconductor wafer
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Abstract
本發明提供一種封裝方法。封裝方法包含:第一積層步驟,一面將一個以上的半導體晶片依序暫時壓接於基板上,一面進行積層,藉此來形成第一晶片積層體;第一正式壓接步驟,從上側對第一晶片積層體進行加熱且進行加壓,藉此,一併對一個以上的半導體晶片進行正式壓接;第二積層步驟,一面將2個以上的半導體晶片依序暫時壓接於經過正式壓接的半導體晶片上,一面進行積層,藉此來形成第二晶片積層體;以及第二正式壓接步驟,從上側對第二晶片積層體進行加熱且進行加壓,藉此,一併對2個以上的半導體晶片進行正式壓接。
Description
本發明是有關於一種積層多個半導體晶片而製造半導體裝置的製造方法以及半導體晶片的封裝裝置。
一直以來,需要使半導體裝置的功能更高、更小型。因此,已部分地提出了積層多個半導體晶片而進行封裝。例如於專利文獻1中,揭示有對多個半導體晶片進行積層封裝的技術。於該專利文獻1中,預先將熱固性黏接劑膜積層於半導體晶片中的凸塊(bump)形成面。於進行積層封裝時,一面將多個半導體晶片依序暫時壓接於基板或其他半導體晶片上,一面進行積層,形成多段暫時壓接積層體。其次,實行正式壓接步驟,即,從上側對該多段暫時壓接積層體進行加壓且進行加熱,藉此,使凸塊熔融,並且使熱固性黏接劑膜固化。根據此種技術,能夠於小面積中封裝更多的半導體晶片,因此能夠使功能更高、更小型。
[現有技術文獻]
[專利文獻]
[專利文獻1]日本專利特開2014-60241號公報
此處,當然為了使功能更高、更小型,只要增加最終獲得的
半導體晶片的積層數(以下稱為「目標層數」)即可。然而,在如專利文獻1般,積層目標層數的半導體晶片之後,一併對該目標層數的半導體晶片進行正式壓接的技術的情況下,若目標層數增加,則有可能無法適當地對下層側的半導體晶片進行封裝。即,於正式壓接中,藉由將加熱後的加熱工具(heat tool)按壓於多段暫時壓接積層體的最上表面,對該多段暫時壓接積層體進行加熱。藉由熱傳導而從上部向下部產生溫度梯度。若積層數增加,與加熱工具相隔的距離變得過長,則有時下層側的半導體晶片不會充分地被加熱。於該情況下,該下層側的半導體晶片的凸塊未充分熔融,或熱固性黏接劑膜未充分固化,因此,下層側的半導體晶片不會適當地被封裝。
因此,本發明的目的在於提供如下半導體裝置的製造方法以及封裝裝置,即,於對半導體晶片進行積層封裝時,即使積層數多,亦能夠適當地封裝各半導體晶片。
本發明的封裝方法是將規定的目標積層數的半導體晶片積層於基板上而製造半導體裝置的製造方法,其特徵在於包括:第一積層步驟,一面將一個以上的半導體晶片依序暫時壓接於所述基板上,一面進行積層,藉此來形成第一晶片積層體;第一正式壓接步驟,從上側對所述第一晶片積層體進行加熱且進行加壓,藉此,一併對所述一個以上的半導體晶片進行正式壓接;第二積層步驟,一面將2個以上的半導體晶片依序暫時壓接於經
過正式壓接的半導體晶片上,一面進行積層,藉此來形成第二晶片積層體;以及第二正式壓接步驟,從上側對所述第二晶片積層體進行加熱且進行加壓,藉此,一併對所述2個以上的半導體晶片進行正式壓接。
在較佳形態中,於實行所述第一積層步驟及所述第一正式壓接步驟之後,反覆進行所述第二積層步驟及所述第二正式壓接步驟,直至所述半導體晶片的總積層數達到所述目標積層數為止。
在其他較佳形態中,於所述基板設定有多個配置區域,於所述第一積層步驟及第一正式壓接步驟中,對一個半導體晶片進行暫時壓接及正式壓接,在2個以上的全部的所述配置區域中實行所述第一正式壓接步驟之後,實行所述第二積層步驟。
其他的本發明即封裝裝置是將規定的目標積層數的半導體晶片積層於基板上而進行封裝的封裝裝置,其特徵在於包括:暫時壓接機構,從上側,以第一溫度對配置於所述基板或下層的半導體晶片上的所述半導體晶片進行加熱,且以第一負載進行加壓,藉此,進行暫時壓接;正式壓接機構,從上側,以高於第一溫度的第二溫度對為一個以上的半導體晶片的積層體的晶片積層體進行加熱,且以第二負載進行加壓,藉此,一併對構成所述晶片積層體的一個以上的半導體晶片進行正式壓接;以及控制部,對所述暫時壓接機構及正式壓接機構進行控制,所述控制部使所述暫時壓接機構及正式壓接機構實行第一積層處理、第一正
式壓接處理、第二積層處理及第二正式壓接處理,所述第一積層處理是指藉由所述暫時壓接機構,將一個以上的半導體晶片依序暫時壓接於所述基板上,藉此來形成第一晶片積層體,所述第一正式壓接處理是指藉由所述正式壓接機構,一併對構成所述第一晶片積層體的所述一個以上的半導體晶片進行正式壓接,所述第二積層處理是指一面藉由所述暫時壓接機構,將2個以上的半導體晶片依序暫時壓接於經過正式壓接的半導體晶片上,一面進行積層,藉此來形成第二晶片積層體,所述第二正式壓接處理是指藉由所述正式壓接機構,一併對構成所述第二晶片積層體的所述2個以上的半導體晶片進行正式壓接。
其他的本發明即封裝裝置是將規定的目標積層數的半導體晶片積層於基板上而進行封裝的封裝裝置,其特徵在於包括:接合部,從上側,以第一溫度對配置於所述基板或下層的半導體晶片上的所述半導體晶片進行加熱,且以第一負載進行加壓,藉此,進行暫時壓接,並且從上側,以高於第一溫度的第二溫度對為一個以上的半導體晶片的積層體的晶片積層體進行加熱,且以第二負載進行加壓,藉此,一併對構成所述晶片積層體的一個以上的半導體晶片進行正式壓接;以及控制部,對所述接合部進行控制,所述控制部包括:第一積層處理部,藉由所述接合部,將一個以上的半導體晶片依序暫時壓接於所述基板上,藉此來形成第一晶片積層體;第一正式壓接處理部,藉由所述接合部,一併對構成所述第一晶片積層體的所述一個以上的半導體晶
片進行正式壓接;第二積層處理部,一面藉由所述接合部,將2個以上的半導體晶片依序暫時壓接於經過正式壓接的半導體晶片上,一面進行積層,藉此來形成第二晶片積層體;以及第二正式壓接處理部,藉由所述接合部,一併對構成所述第二晶片積層體的所述2個以上的半導體晶片進行正式壓接。
根據本發明,於積層規定的目標積層數的半導體晶片時,將積層步驟與正式壓接步驟反覆進行至少2次。因此,無需一併對目標積層數的半導體晶片進行正式壓接,亦能夠確實地對下層側的半導體晶片進行加熱。結果是於對半導體晶片進行積層封裝時,即使積層數多,亦能夠適當地封裝各半導體晶片。
10‧‧‧半導體晶片
14、16、32‧‧‧電極端子
18‧‧‧凸塊
20‧‧‧NCF
30‧‧‧基板
34‧‧‧配置區域
100‧‧‧封裝裝置
102‧‧‧晶片供給部
104‧‧‧晶片搬送部
106‧‧‧接合部
110‧‧‧頂起部
114‧‧‧晶片拾取器
116‧‧‧移送頭
118‧‧‧旋轉台
120‧‧‧平台
122‧‧‧封裝頭
130‧‧‧控制部
132‧‧‧第一積層處理部
134‧‧‧第一正式壓接處理部
135‧‧‧第二積層處理部
136‧‧‧第二正式壓接處理部
138‧‧‧記憶部
A、B、C‧‧‧區域
H‧‧‧距離
Ra、Rb‧‧‧旋轉軸
ST0‧‧‧完成積層體
ST1‧‧‧第一晶片積層體
ST2‧‧‧第二晶片積層體
T1‧‧‧第一溫度
T2‧‧‧第二溫度
Ta‧‧‧下層溫度
TE‧‧‧切割膠帶
圖1是表示本發明的實施形態即封裝裝置的構成的圖。
圖2是作為基板而發揮功能的半導體晶圓的概略立體圖。
圖3是表示被封裝的半導體晶片的構成的圖。
圖4是表示半導體裝置的構成的圖。
圖5(a)~圖5(c)是表示積層多個半導體晶片而進行封裝的流程的圖。
圖6(a)~圖6(c)是表示積層多個半導體晶片而進行封裝的流程的圖。
圖7(a)~圖7(b)是表示積層多個半導體晶片而進行封裝
的流程的圖。
圖8(a)~圖8(c)是表示積層多個半導體晶片而進行封裝的其他例子的流程的圖。
以下,參照圖式來對本發明的實施形態進行說明。圖1是本發明的實施形態即封裝裝置100的概略構成圖。該封裝裝置100為將半導體晶片10封裝於基板30上的裝置。該封裝裝置100的構成尤其適合於積層多個半導體晶片10而進行封裝的情況。
封裝裝置100包括晶片供給部102、晶片搬送部104、接合部106及對這些部分的驅動進行控制的控制部(未圖示)。晶片供給部102為從晶片供給源取出半導體晶片10,將該半導體晶片10供給至晶片搬送部104的部位。該晶片供給部102包括頂起部110、晶片拾取器(die picker)114、移送頭116及對封裝裝置的各部分進行控制的控制部130。
於晶片供給部102中,多個半導體晶片10載置於切割膠帶(dicing tape)TE上。此時,半導體晶片10是以凸塊18朝向上側的面朝上狀態被載置。頂起部110從所述多個半導體晶片10中,僅將一個半導體晶片10以面朝上狀態向上方頂起。晶片拾取器114接受由頂起部110頂起的半導體晶片10。接受了半導體晶片10的晶片拾取器114以使該半導體晶片10的凸塊18朝向下方的方式,即以使半導體晶片10成為面朝下狀態的方式,當場旋轉180度。若成為該狀態,則移送頭116會從晶片拾取器114接
受半導體晶片10。
移送頭116能夠沿著上下方向及水平方向移動,且能夠利用其下端來吸附保持半導體晶片10。若晶片拾取器114旋轉180度,半導體晶片10成為面朝下狀態,則移送頭116會利用其下端來吸附保持該半導體晶片10。然後,移送頭116沿著水平方向及上下方向移動,向晶片搬送部104移動。
晶片搬送部104具有以鉛垂的旋轉軸Ra為中心而旋轉的旋轉台118。移送頭116將半導體晶片10載置於旋轉台118的規定位置。載置有半導體晶片10的旋轉台118以旋轉軸Ra為中心而旋轉,藉此,將該半導體晶片10搬送至位於晶片供給部102的相反側的接合部106。
接合部106包括對基板30進行支持的平台120或保持半導體晶片10而將其安裝於基板30的封裝頭122等。該接合部106作為對半導體晶片10進行暫時壓接的暫時壓接機構而發揮功能,並且亦作為對半導體晶片10進行正式壓接的正式壓接機構而發揮功能。平台120能夠沿著水平方向移動,對所載置的基板30與封裝頭122之間的相對位置關係進行調整。而且,亦可於該平台120中內置加熱器。
封裝頭122能夠於其下端保持半導體晶片10,而且,能夠圍繞鉛垂的旋轉軸Rb旋轉與升降。該封裝頭122將半導體晶片10壓接於平台120所載置的基板30或其他半導體晶片10上。具體而言,封裝頭122下降,以將所保持的半導體晶片10按壓至基
板30等,藉此,對半導體晶片10進行暫時壓接或正式壓接。該封裝頭122中內置有溫度可變的加熱器,封裝頭122於實行暫時壓接時,被加熱至後述的第一溫度T1,於實行正式壓接時,被加熱至較第一溫度T1更高的第二溫度T2。而且,封裝頭122於實行暫時壓接時,將第一負載Ft1附加至半導體晶片10,於實行正式壓接時,將第二負載Ft2附加至半導體晶片10。
於封裝頭122的附近設置有相機(camera)(未圖示)。於基板30及半導體晶片10分別標識有作為定位基準的對準標記(alignment mark)。相機是以映出該對準標記的方式來拍攝基板30及半導體晶片10。控制部130基於藉由該拍攝而獲得的圖像資料來掌握基板30及半導體晶片10的相對位置關係,且根據需要,對封裝頭122的圍繞旋轉軸Rb的旋轉角度及平台120的水平位置進行調整。
控制部130對各部分的驅動進行控制,例如包括進行各種運算的中央處理單元(Central Processing Unit,CPU)、與記憶各種資料或程式的記憶部138。該控制部130從記憶部138讀取程式,藉此,作為第一積層處理部132、第一正式壓接處理部134、第二積層處理部135及第二正式壓接處理部136而發揮功能。第一積層處理部132藉由接合部106,將一個以上的半導體晶片10依序暫時壓接於基板30上,藉此,形成第一晶片積層體。第一正式壓接處理部134藉由接合部106,一併對構成第一晶片積層體的一個以上的半導體晶片10進行正式壓接。第二積層處理部135藉
由接合部106,一面將2個以上的半導體晶片10依序暫時壓接於經過正式壓接的半導體晶片10上,一面進行積層,藉此,形成第二晶片積層體。第二正式壓接處理部136藉由接合部106,一併對構成第二晶片積層體的2個以上的半導體晶片10進行正式壓接。
再者,此處所說明的封裝裝置100的構成為一例,亦可適當變更。例如,於本實施形態中,利用一個封裝頭122來進行暫時壓接及正式壓接該兩者,但亦可設置暫時壓接用的加壓頭、與正式壓接用的加壓頭。而且,於本實施形態中,採用了由平台120進行水平移動的構成,但亦可採用如下構成,即,代替平台120,或除了平台120之外,封裝頭122亦進行水平移動。而且,晶片供給部102或晶片搬送部104等的構成亦可適當變更。
其次,說明該封裝裝置100對於半導體晶片10的封裝。於本實施形態中,使用半導體晶圓作為基板30,將多個半導體晶片10積層封裝於該半導體晶圓(基板30)上。因此,本實施形態的封裝製程為將半導體晶片10積層封裝於半導體晶圓的電路形成面的晶圓上晶片製程(chip on wafer process)。圖2是本實施形態中所使用的基板30(半導體晶圓)的概略概念圖。如圖2所示,於基板30設置有呈格子狀排列的多個配置區域34。於各配置區域34積層封裝多個半導體晶片10。
其次,簡單說明半導體晶片10的構成。圖3是表示被封裝的半導體晶片10的概略構成的圖。於半導體晶片10的上下表面形成有電極端子14、16。而且,於半導體晶片10的單面,與
電極端子14相連地形成有凸塊18。凸塊18包含導電性金屬,且會因規定的熔融溫度Tm而熔融。
而且,於半導體晶片10的單面,以覆蓋凸塊18的方式貼附有非導電性膜(以下稱為「NCF」)20。NCF 20作為對半導體晶片10與基板30或其他半導體晶片10進行黏接的黏接劑而發揮功能,且包含非導電性的熱固性樹脂例如聚醯亞胺樹脂、環氧樹脂、丙烯酸樹脂、苯氧基樹脂、聚醚碸樹脂等。該NCF 20的厚度大於凸塊18的平均高度,藉由該NCF 20大致完全覆蓋凸塊18。NCF 20於常溫下為固體膜,但若超過規定的軟化開始溫度Ts,則會逐步軟化而顯現出流動性,若超過規定的固化開始溫度Tt,則會不可逆地開始固化。
此處,軟化開始溫度Ts低於凸塊18的熔融溫度Tm及固化開始溫度Tt。暫時壓接用的第一溫度T1高於該軟化開始溫度Ts,且低於熔融溫度Tm及固化開始溫度Tt。而且,正式壓接用的第二溫度T2高於熔融溫度Tm及固化開始溫度Tt。即,Ts<T1<(Tm、Tt)<T2。
當將半導體晶片10暫時壓接於基板30或下側的半導體晶片10(以下稱為「被壓接體」)時,在將封裝頭122加熱至第一溫度T1之後,對半導體晶片10加壓。此時,半導體晶片10的NCF 20藉由來自封裝頭122的導熱而被加熱至第一溫度T1附近,軟化且具有流動性。於是,藉此,NCF 20流入至半導體晶片10與被壓接體之間的間隙,從而能夠確實地填埋該間隙。
當將半導體晶片10正式壓接於被壓接體時,在將封裝頭122加熱至第二溫度T2之後,對半導體晶片10加壓。此時,半導體晶片10的凸塊18及NCF 20藉由來自封裝頭122的導熱而被加熱至第二溫度T2附近。藉此,凸塊18熔融,能夠熔接於相對向的被壓接體。而且,藉由該加熱,NCF 20於填埋半導體晶片10與被壓接體之間的間隙的狀態下固化,因此,半導體晶片10與被壓接體牢固地被固定。
其次,說明對半導體晶片10進行積層封裝而製造的半導體裝置。圖4是表示將多個半導體晶片10積層封裝於基板30而成的半導體裝置的構成的圖。將目標積層數的半導體晶片10分別積層封裝於多個配置區域34而構成半導體裝置。於本實施形態中,將目標積層數設為「8」,將8個半導體晶片10積層封裝於一個配置區域34。以下,將積層封裝有8個半導體晶片10的積層體稱為「完成積層體ST0」。
於本實施形態中,將完成積層體ST0分為多個晶片積層體,具體而言,分為第一晶片積層體ST1與第二晶片積層體ST2而進行處理。第一晶片積層體ST1為包含積層於基板30上的4個半導體晶片10的積層體。而且,第二晶片積層體ST2為包含積層於第一晶片積層體ST1上的4個半導體晶片10的積層體。於本實施形態中,在為了形成第一晶片積層體ST1而實行第一積層步驟及第一正式壓接步驟之後,實行用以形成第二晶片積層體ST2的第二積層步驟及第二正式壓接步驟。如此,將一個完成積層體ST0
分割為2個以上的晶片積層體ST1、ST2進行處理的目的在於良好地對全部的半導體晶片10進行封裝,該情況將後述。
其次,參照圖5(a)~圖5(c)~圖7(a)~圖7(b)來對半導體晶片10的封裝流程進行說明。圖5(a)~圖5(c)~圖7(a)~圖7(b)是表示半導體晶片10的封裝流程的概念圖。於圖5(a)~圖5(c)~圖7(a)~圖7(b)中,圖示有三個配置區域34,但為了便於說明,將這些配置區域34從左側依序稱為區域A、區域B、區域C。而且,以下所說明的封裝流程可於常壓下進行,亦可為了防止氣泡的夾雜等而於真空中實施。
於本實施形態中,如上所述,首先在封裝第一晶片積層體ST1之後,進而將第二晶片積層體ST2封裝於該第一晶片積層體ST1上,最終形成8層的完成積層體ST0。藉由實行積層步驟與正式壓接步驟來封裝各晶片積層體ST1、ST2,該積層步驟是指一面依序對4個半導體晶片10進行暫時壓接,一面進行積層,形成暫時壓接狀態的晶片積層體ST1、ST2,該正式壓接步驟是指從該晶片積層體ST1、ST2的上方,以第二溫度T2進行加熱加壓,藉此,一併對4個半導體晶片10進行正式壓接。
若具體地進行說明,則首先,最初如圖5(a)所示,使用封裝頭122將半導體晶片10配置於基板30上的區域A。此時,以使半導體晶片10的凸塊18與基板30上的電極端子32相向的方式,相對於半導體晶片10對基板30進行定位。而且,此時,封裝頭122已被加熱至暫時壓接用的溫度即第一溫度T1。其次,
如圖5(b)所示,利用封裝頭122,以規定的第一負載Ft1對半導體晶片10加壓,將半導體晶片10暫時壓接於基板30。此時,藉由來自封裝頭122的導熱,NCF 20被加熱至軟化開始溫度Ts以上而顯現出適度的流動性。藉此,NCF 20無間隙地填埋半導體晶片10與基板30之間的間隙。再者,第一負載Ft1只要為使凸塊18能夠推開已軟化的NCF 20而與基板30的電極端子32接觸,且凸塊18為不會大幅度變形的程度的大小,則並無特別限定。
對第一層的半導體晶片10完成了暫時壓接之後,接著,進而將第二層的半導體晶片10暫時壓接於該經過暫時壓接的第一層的半導體晶片10上。當對第二層的半導體晶片10進行暫時壓接時,與第一層的情況同樣地,使用封裝頭122,以使第二層的半導體晶片10的凸塊18與第一層的半導體晶片10的電極端子16相向的方式,將第二層的半導體晶片10配置於第一層的半導體晶片10上。接著,於該狀態下,以第一溫度T1對第二層的半導體晶片10進行加熱,且以第一負載Ft1進行加壓,將該第二層的半導體晶片10暫時壓接於第一層的半導體晶片10。
以後,同樣地,逐步將第三層的半導體晶片10暫時壓接於第二層的半導體晶片10上,將第四層的半導體晶片10暫時壓接於第三層的半導體晶片10上。圖5(c)表示在區域A中,一面對4層的半導體晶片10進行暫時壓接,一面進行積層的情況。積層該4個半導體晶片10的步驟為第一積層步驟,所形成的積層體成為暫時壓接狀態的第一晶片積層體ST1。
於區域A中形成了暫時壓接狀態的第一晶片積層體ST1之後,依照同樣的流程,亦於區域B、區域C等其他配置區域34中形成暫時壓接狀態的第一晶片積層體ST1。圖6(a)表示在全部的配置區域34中,一面對4個半導體晶片10進行暫時壓接,一面進行積層,形成暫時壓接狀態的第一晶片積層體ST1的情況。
於全部的配置區域34中形成了暫時壓接狀態的第一晶片積層體ST1之後,接著,實行對第一晶片積層體ST1進行正式壓接的第一正式壓接步驟。具體而言,首先,將封裝頭122加熱至正式壓接用的溫度即第二溫度T2。接著,如圖6(b)所示,使用已加熱至第二溫度T2的封裝頭122,以第二負載Ft2對暫時壓接狀態的第一晶片積層體ST1加壓,一併對四個半導體晶片10進行正式壓接。再者,第二負載Ft2只要適當確保對於凸塊18的推壓量,則並無特別限定。
因受到已加熱至第二溫度T2的封裝頭122按壓,構成第一晶片積層體ST1的四個半導體晶片10亦被加熱。然而,加熱溫度會隨著遠離封裝頭122而逐步下降。具體而言,最上層(第四層)的半導體晶片10會被加熱至與第二溫度T2大致相同的溫度,但最下層(第一層)的半導體晶片10是以從第二溫度T2下降了△T的下層溫度Ta=T2-△T被加熱。以使該下層溫度Ta大於熔融溫度Tm及固化開始溫度Tt的方式來設定第二溫度T2。即,於正式壓接時,構成第一晶片積層體ST1的4個半導體晶片10均被加熱至較熔融溫度Tm及固化開始溫度Tt更高的溫度。
因各半導體晶片10超過固化開始溫度Tt地被加熱,半導體晶片10的NCF 20逐步固化。接著,因NCF 20固化,半導體晶片10與被壓接體(基板30或下側的半導體晶片10)機械性牢固地被固定。而且,因超過熔融溫度Tm地被加熱,凸塊18熔融,且能夠密著於相對向的電極端子32、16。於是,藉此,四個半導體晶片10及基板30成為彼此電性接合的封裝狀態。接著,一併對構成該第一晶片積層體ST1的四個半導體晶片10進行正式壓接的步驟成為第一正式壓接步驟。
對一個第一晶片積層體ST1完成了正式壓接之後,接著,亦對其他第一晶片積層體ST1進行正式壓接。即,於區域B、區域C等2個以上的全部的配置區域34中實行第一正式壓接步驟。圖6(c)表示在全部的配置區域34中實行第一正式壓接步驟的情況。
於全部的配置區域34中實行了第一正式壓接步驟之後,接著,實行在第一晶片積層體ST1上形成暫時壓接狀態的第二晶片積層體ST2的第二積層步驟。具體而言,使封裝頭122的溫度下降至暫時壓接用的溫度即第一溫度T1。然後,如圖7(a)、圖7(b)所示,重新一面將四個半導體晶片10依序暫時壓接於經過正式壓接的第一晶片積層體ST1上,一面進行積層。藉此,所形成的積層體為第二晶片積層體ST2,形成該第二晶片積層體ST2的步驟為第二積層步驟。亦於2個以上的全部的配置區域34中實行第二積層步驟。於全部的配置區域34中形成了暫時壓接狀態的
第二晶片積層體ST2之後,最後實行第二正式壓接步驟,對全部的第二晶片積層體ST2進行正式壓接。接著,對全部的第二晶片積層體ST2進行了正式壓接之後,封裝步驟完成。
如以上的說明所述,於本實施形態中,將一個完成積層體ST0分割為多個(於本例中為兩個)晶片積層體ST1、ST2,對各晶片積層體ST1、ST2實行積層步驟與正式壓接步驟。與現有技術相比較,對設為該處理流程的理由進行說明。
一直以來,積層多個半導體晶片10而進行封裝的技術已為人所知。然而,現有的封裝技術是在積層全部的目標積層數的半導體晶片10之後,實行正式壓接。即,於圖4的例子中,在一面對8個半導體晶片10進行暫時壓接,一面進行積層之後,以第二溫度T2,從第八層的半導體晶片10的上側進行加熱且進行加壓。於設為該流程的情況下,封裝頭122的加熱溫度的切換(第一溫度T1-第二溫度T2之間的切換)僅為一次,因此,能夠減少封裝頭122的升降溫所需的時間,從而能夠縮短封裝處理整體的時間。然而,於此種現有技術的情況下,無法適當地對下層的半導體晶片10進行加熱,NCF 20的固化或凸塊18的熔融有可能不充分。
即,於現有技術中,在對8個半導體晶片10進行積層封裝的情況下,將已加熱的封裝頭122按壓於最上層(第八層)的半導體晶片10,一併對8個半導體晶片10進行正式壓接。然而,於該情況下,若積層數多,則從封裝頭122至下層的半導體晶片
10為止的距離H變長。若從作為熱源的封裝頭122算起的距離H變長,則加熱溫度亦會相應地下降。結果是下層的半導體晶片10無法充分地被加熱,NCF 20的固化或凸塊18的熔融有可能不充分。
此處,當然只要使封裝頭122的溫度升高,則可確保下層的半導體晶片10的溫度為高溫。然而,考慮到所述的上層晶片、下層晶片之間的溫度梯度,溫度需要高於第一溫度。藉此,由於上層晶片的凸塊18熔融,隨之產生合金反應,進而導致NCF 20固化、劣化,故而會顯著影響可靠性。因此,無法過度地將封裝頭122加熱至高溫。
因此,於本實施形態中,如上所述,將包含目標積層數的半導體晶片的完成積層體ST0分割為多個晶片積層體ST1、ST2,對各晶片積層體ST1、ST2進行積層步驟與正式壓接步驟。藉由設為該處理流程,於進行正式壓接時,能夠縮短從封裝頭122至下層的半導體晶片10為止的距離。因此,即使不過度地提高正式壓接用的溫度即第二溫度T2,亦能夠適當地加熱至晶片積層體ST1、ST2的下層。結果是在對半導體晶片10進行積層封裝時,即使積層數多,亦能夠適當地封裝各半導體晶片10。
其次,參照圖8來對其他實施形態進行說明。圖8是表示其他封裝流程的概念圖。該實施形態與第一實施形態的不同點在於:第一晶片積層體ST1包含一個半導體晶片10。而且,於本實施形態中,在形成一個第一晶片積層體ST1之後,形成下一個
第一晶片積層體ST1。若具體地進行說明,則於本實施形態中,首先,利用已加熱至第一溫度T1的封裝頭122,將一個半導體晶片10配置於一個配置區域34(區域A)。接著,於該狀態下,附加第一負載Ft1,對半導體晶片10進行暫時壓接。然後,在將封裝頭122升溫至第二溫度之後,以第二負載Ft2對半導體晶片10加壓。即,連續實行第一積層步驟與第一正式壓接步驟。於該步驟中,經過正式壓接的一個半導體晶片10成為第一晶片積層體ST1。於區域A中形成了第一晶片積層體ST1之後,接著,亦於剩餘的配置區域34即區域B、區域C中依序形成第一晶片積層體ST1。圖8(a)表示在全部的配置區域34中形成第一晶片積層體ST1的情況。
成為該狀態之後,接著形成第二晶片積層體ST2。該第二晶片積層體ST2的形成流程與第一實施形態相同。即,一面利用已加熱至第一溫度T1的封裝頭122,將多個(於圖示例中為3個)半導體晶片10依序暫時壓接於第一晶片積層體ST1上,一面進行積層,形成暫時壓接狀態的第二晶片積層體ST2。形成了一個第二晶片積層體ST2之後,亦於其他配置區域34中,同樣形成第二晶片積層體ST2。即,於2個以上的全部的配置區域34中實行第二積層步驟。圖8(b)是表示形成有暫時壓接狀態的第二晶片積層體ST2的情況的圖。接著,於已將封裝頭122加熱至正式壓接用的第二溫度T2的狀態下,對第二晶片積層體ST2加壓,且逐步一併對4個半導體晶片10進行正式壓接。圖8(c)是表示第
二正式壓接步驟的情況的圖。於一個配置區域34中完成了第二正式壓接步驟之後,亦於剩餘的配置區域34中,同樣實施第二正式壓接步驟。以後,反覆進行第二積層步驟與第二正式壓接步驟,直至半導體晶片10的總積層數達到目標積層數為止。例如,於目標積層數為「8」的情況下,成為圖8(c)的狀態之後,接著,只要實施第二次的第二積層步驟及第二正式壓接步驟即可,該第二次的第二積層步驟及第二正式壓接步驟是指一面進而將4層的半導體晶片10暫時壓接於各第二晶片積層體ST2上,一面進行積層,然後進行正式壓接。進而,於目標積層數為「10」的情況下,只要在所述第二次的第二積層步驟及第二正式壓接步驟之後,進而實施第三次的第二積層步驟及第二正式壓接步驟即可,該第三次的第二積層步驟及第二正式壓接步驟是指一面對2層的半導體晶片10進行暫時壓接,一面進行積層,然後進行正式壓接。
而且,如以上的說明所述,於本實施形態中,將第一晶片積層體ST1的晶片積層數設為一個。換言之,於2個以上的全部的配置區域34中,對第一層的半導體晶片10進行正式壓接之後,積層第二層以後的半導體晶片。根據如下理由而設為該構成。
本實施形態中的基板30為包含矽等的半導體晶圓。該半導體晶圓與通常的樹脂基板等相比較,熱傳導率高。因此,因正式壓接而對區域A的晶片積層體附加的熱有時會傳遞至鄰接的區域B的晶片積層體。此時,如圖6(b)所示,於對區域A的晶片積層體進行正式壓接時,在鄰接於區域A的區域B中,第一層
的半導體晶片10為暫時壓接狀態。於該情況下,經由區域A的晶片積層體及基板30而傳遞的熱亦會傳遞至區域B的第一層的半導體晶片10。於是存在如下情況,即,區域B的第一層的半導體晶片10的NCF 20因該傳遞的熱而開始固化。如此,若NCF 20於正式壓接之前固化,則半導體晶片10於基板30的固定變得不充分。
因此,於本實施形態中,為了防止NCF 20意外地固化,在對第一層的半導體晶片10完全進行正式壓接之後,積層第二層以後的半導體晶片10。於設為該構成的情況下,如圖8(c)所示,於區域A中對第二層以後的半導體晶片10進行正式壓接時的熱亦會經由區域A的晶片積層體、基板,傳遞至區域B的第一層的半導體晶片10。然而,該區域B的第一層的半導體晶片10已經過正式壓接,因此,即使導熱,亦不會產生問題。而且,熱亦經由該區域B的第一層的半導體晶片10而傳遞至區域B的第二層以後的半導體晶片10。然而,對於該區域B的第二層以後的半導體晶片10而言,由於從熱源(封裝頭122)算起的熱路徑變長,故而導熱量小,NCF 20不易固化。進而,正式壓接後的半導體晶片10介於從熱源至區域B的第二層以後的半導體晶片10為止的熱路徑途中。該正式壓接後的半導體晶片10的NCF 20已完全固化,但已固化的NCF 20會作為阻礙導熱的屏蔽材而發揮功能。由於該正式壓接完成後的半導體晶片10的介入,能夠大幅度地減少向區域B的第二層以後的半導體晶片10傳遞的導熱量。
即,預先於全部的配置區域34中,對第一層的半導體
晶片10進行正式壓接,藉此,能夠有效果地防止第二層以後的半導體晶片10的NCF 20意外地固化。而且,根據本實施形態,即使將封裝頭122的溫度設定得稍高,鄰接區域中的NCF 20亦不會意外地固化。結果是能夠提高封裝頭122的溫度,因此,能夠提高封裝頭122的溫度設定的自由度。
再者,至此為止所說明的構成為一例,若每當形成一個完成積層體ST0時,將積層步驟與正式壓接步驟反覆進行2次以上,則亦可適當變更其他構成。例如,亦可適當變更暫時壓接與正式壓接的實行順序。
例如,於本實施形態中,在全部的多個配置區域34中結束了積層步驟之後,實行正式壓接步驟,但亦可於各配置區域34中串列地實行積層步驟及正式壓接步驟。即,亦可於區域A中連續實行第一積層步驟、第一正式壓接步驟、第二積層步驟、第二正式壓接步驟之後,於區域B中進行第一積層步驟、第一正式壓接步驟、第二積層步驟、第二正式壓接步驟。於設為該構成的情況下,封裝頭122的溫度的切換次數增加,但於實行正式壓接的積層體附近不存在暫時壓接狀態的積層體。結果是能夠防止NCF 20意外地固化。
而且,於對各晶片積層體ST1、ST2的最上層的半導體晶片10進行暫時壓接時,亦可連續進行正式壓接。具體而言,於第一實施形態中,當形成第一晶片積層體ST1時,於各區域A~區域C中,一面對半導體晶片10進行暫時壓接,一面進行積層直
至第三層為止。然後,於區域A中,利用已加熱至第一溫度T1的封裝頭122,對第四層的半導體晶片10加壓而進行暫時壓接。對第四層的半導體晶片10加壓完成之後,於利用封裝頭122對第四層的半導體晶片10加壓的狀態下,使封裝頭122的溫度上升至第二溫度T2而實行正式壓接。於該情況下,若區域A的第四層的半導體晶片10的正式壓接已完成,則在將封裝頭122降溫至第一溫度T1之後,對區域B的第四層的半導體晶片10進行暫時壓接,然後,升溫至第二溫度T2而進行正式壓接。於設為該構成的情況下,封裝頭122的溫度的切換次數增加,但能夠減小封裝頭122的移動量。
而且,於至此為止的說明中,利用封裝頭122來實行暫時壓接及正式壓接該兩者,但亦可單獨設置暫時壓接用的封裝頭、與正式壓接用的封裝頭。於該情況下,只要預先總是將暫時壓接專用的封裝頭加熱至第一溫度T1,且總是將正式壓接專用的封裝頭加熱至第二溫度T2即可。藉由設為該構成,無需對封裝頭的溫度進行切換,因此,能夠消除封裝頭升降溫所需的時間,從而能夠進一步縮短封裝時間。而且,此時,正式壓接用的封裝頭亦可設為能夠同時對2個以上的晶片積層體進行加熱、加壓(正式壓接)的尺寸。
而且,只要第一晶片積層體的積層數為1以上,則並無特別限定。而且,只要第二晶片積層體的積層數為2以上,則並無特別限定。然而,於一個晶片積層體的積層數過多的情況下,
對最上表面賦予的正式壓接的熱無法充分地傳遞至最下層,會產生封裝不良。因此,晶片積層體的積層數設為能夠使正式壓接的熱適當傳遞至最下層的個數以下。適當導熱的個數根據半導體晶片10的材質或構成而有所不同,但於使用一般的半導體晶片10的情況下,一個晶片積層體的積層數較佳為4以下。而且,於本實施形態中,使用半導體晶圓作為基板30,但基板30不限於半導體晶圓,亦可為其他種類的基板。
Claims (5)
- 一種半導體裝置的製造方法,其是將規定的目標積層數的半導體晶片積層於基板上而製造半導體裝置的製造方法,其特徵在於包括:第一積層步驟,一面將一個以上的半導體晶片依序暫時壓接於所述基板上,一面進行積層,藉此來形成第一晶片積層體;第一正式壓接步驟,從上側對所述第一晶片積層體進行加熱且進行加壓,藉此,一併對所述一個以上的半導體晶片進行正式壓接,將所述半導體晶片接合於所述基板並且經暫時壓接的所述第一晶片積層體的所述半導體晶片彼此進行接合;第二積層步驟,一面將2個以上的半導體晶片依序暫時壓接於經過正式壓接的半導體晶片上,一面進行積層,藉此來形成第二晶片積層體;以及第二正式壓接步驟,從上側對所述第二晶片積層體進行加熱且進行加壓,藉此,一併對所述2個以上的半導體晶片進行正式壓接,將經暫時壓接的所述第二晶片積層體的所述半導體晶片彼此進行接合。
- 如申請專利範圍第1項所述的半導體裝置的製造方法,其中於實行所述第一積層步驟及所述第一正式壓接步驟之後,反覆進行所述第二積層步驟及所述第二正式壓接步驟,直至所述半導體晶片的總積層數達到所述目標積層數為止。
- 如申請專利範圍第1項或第2項所述的半導體裝置的製造方法,其中於所述基板設定有多個配置區域,於所述第一積層步驟及所述第一正式壓接步驟中,對一個半導體晶片進行暫時壓接及正式壓接,在2個以上的全部的所述配置區域中實行所述第一正式壓接步驟之後,實行所述第二積層步驟。
- 一種封裝裝置,其是將規定的目標積層數的半導體晶片積層於基板上而進行封裝的封裝裝置,其特徵在於包括:暫時壓接機構,從上側,以第一溫度對配置於所述基板或下層的半導體晶片上的所述半導體晶片進行加熱,且以第一負載進行加壓,藉此,進行暫時壓接;正式壓接機構,從上側,以高於第一溫度的第二溫度對為一個以上的半導體晶片的積層體的晶片積層體進行加熱,且以第二負載進行加壓,藉此,一併對構成所述晶片積層體的一個以上的半導體晶片進行正式壓接;以及控制部,對所述暫時壓接機構及所述正式壓接機構進行控制,所述控制部使所述暫時壓接機構及所述正式壓接機構實行第一積層處理、第一正式壓接處理、第二積層處理及第二正式壓接處理,所述第一積層處理是指藉由所述暫時壓接機構,將一個以上的半導體晶片依序暫時壓接於所述基板上,藉此來形成第一晶片積層體,所述第一正式壓接處理是指藉由所述正式壓接機構,一併對構成所述第一晶片積層體的所述一個以上的半導體晶片進行正式壓接,所述第二積層處理是指一面藉由所述暫時壓接機構,將2個以上的半導體晶片依序暫時壓接於經過正式壓接的半導體晶片上,一面進行積層,藉此來形成第二晶片積層體,所述第二正式壓接處理是指藉由所述正式壓接機構,一併對構成所述第二晶片積層體的所述2個以上的半導體晶片進行正式壓接。
- 一種封裝裝置,其是將規定的目標積層數的半導體晶片積層於基板上而進行封裝的封裝裝置,其特徵在於包括:接合部,從上側,以第一溫度對配置於所述基板或下層的半導體晶片上的所述半導體晶片進行加熱,且以第一負載進行加壓,藉此,進行暫時壓接,並且從上側,以高於第一溫度的第二溫度對為一個以上的半導體晶片的積層體的晶片積層體進行加熱,且以第二負載進行加壓,藉此,一併對構成所述晶片積層體的一個以上的半導體晶片進行正式壓接;以及控制部,對所述接合部進行控制,所述控制部包括:第一積層處理部,藉由所述接合部,將一個以上的半導體晶片依序暫時壓接於所述基板上,藉此來形成第一晶片積層體;第一正式壓接處理部,藉由所述接合部,一併對構成所述第一晶片積層體的所述一個以上的半導體晶片進行正式壓接;第二積層處理部,一面藉由所述接合部,將2個以上的半導體晶片依序暫時壓接於經過正式壓接的半導體晶片上,一面進行積層,藉此來形成第二晶片積層體;以及第二正式壓接處理部,藉由所述接合部,一併對構成所述第二晶片積層體的所述2個以上的半導體晶片進行正式壓接。
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TW201426969A (zh) * | 2012-12-28 | 2014-07-01 | Helio Optoelectronics Corp | 高壓覆晶led結構及其製造方法 |
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