TWI659479B - 半導體裝置的製造方法以及封裝裝置 - Google Patents
半導體裝置的製造方法以及封裝裝置 Download PDFInfo
- Publication number
- TWI659479B TWI659479B TW106133433A TW106133433A TWI659479B TW I659479 B TWI659479 B TW I659479B TW 106133433 A TW106133433 A TW 106133433A TW 106133433 A TW106133433 A TW 106133433A TW I659479 B TWI659479 B TW I659479B
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- crimping
- temporary
- temperature
- substrate
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 184
- 238000004806 packaging method and process Methods 0.000 title claims abstract description 46
- 238000004519 manufacturing process Methods 0.000 title claims description 19
- 238000002788 crimping Methods 0.000 claims abstract description 168
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000000926 separation method Methods 0.000 claims abstract description 46
- 238000000034 method Methods 0.000 claims abstract description 38
- 238000010438 heat treatment Methods 0.000 claims abstract description 16
- 230000006835 compression Effects 0.000 claims abstract description 14
- 238000007906 compression Methods 0.000 claims abstract description 14
- 235000012431 wafers Nutrition 0.000 claims description 353
- 230000015572 biosynthetic process Effects 0.000 claims description 11
- 238000003475 lamination Methods 0.000 claims description 11
- 238000009826 distribution Methods 0.000 claims description 10
- 238000010030 laminating Methods 0.000 claims description 10
- 239000011347 resin Substances 0.000 claims description 8
- 229920005989 resin Polymers 0.000 claims description 8
- 229920001187 thermosetting polymer Polymers 0.000 claims description 8
- 238000002844 melting Methods 0.000 description 19
- 230000008018 melting Effects 0.000 description 19
- 238000010586 diagram Methods 0.000 description 18
- 239000000463 material Substances 0.000 description 12
- 238000012858 packaging process Methods 0.000 description 4
- 230000002411 adverse Effects 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 238000003860 storage Methods 0.000 description 3
- 239000002313 adhesive film Substances 0.000 description 2
- 238000007306 functionalization reaction Methods 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- 239000004721 Polyphenylene oxide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005538 encapsulation Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000013034 phenoxy resin Substances 0.000 description 1
- 229920006287 phenoxy resin Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920000570 polyether Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/52—Mounting semiconductor bodies in containers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67248—Temperature monitoring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
- H01L24/92—Specific sequence of method steps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/94—Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
- H01L2224/29001—Core members of the layer connector
- H01L2224/29099—Material
- H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
- H01L2224/331—Disposition
- H01L2224/3318—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/33181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75251—Means for applying energy, e.g. heating means in the lower part of the bonding apparatus, e.g. in the apparatus chuck
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7525—Means for applying energy, e.g. heating means
- H01L2224/75252—Means for applying energy, e.g. heating means in the upper part of the bonding apparatus, e.g. in the bonding head
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7555—Mechanical means, e.g. for planarising, pressing, stamping
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/7565—Means for transporting the components to be connected
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
- H01L2224/75—Apparatus for connecting with bump connectors or layer connectors
- H01L2224/759—Means for monitoring the connection process
- H01L2224/75901—Means for monitoring the connection process using a computer, e.g. fully- or semi-automatic bonding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8112—Aligning
- H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/81132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/8119—Arrangement of the bump connectors prior to mounting
- H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/812—Applying energy for connecting
- H01L2224/81201—Compression bonding
- H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
- H01L2224/81986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/8313—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8312—Aligning
- H01L2224/83121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
- H01L2224/83132—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed outside the semiconductor or solid-state body, i.e. "off-chip"
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83191—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/832—Applying energy for connecting
- H01L2224/83201—Compression bonding
- H01L2224/83203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/838—Bonding techniques
- H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
- H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
- H01L2224/83856—Pre-cured adhesive, i.e. B-stage adhesive
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/83986—Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
- H01L2224/92—Specific sequence of method steps
- H01L2224/921—Connecting a surface with connectors of different types
- H01L2224/9212—Sequential connecting processes
- H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
- H01L2224/92143—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
- H01L2225/06565—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having the same size and there being no auxiliary carrier between the devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
- H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/33—Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Wire Bonding (AREA)
Abstract
本發明提供一種可防止經正式壓接的晶片積層體的周邊的晶片積層體中的不期望的熱變化的封裝方法。封裝方法具備臨時壓接步驟,一面將半導體晶片臨時壓接於基板上,一面積層,而形成臨時壓接狀態的晶片積層體;以及正式壓接步驟,對臨時壓接狀態的晶片積層體的上表面加熱加壓並正式壓接,進而具備確定步驟,於臨時壓接步驟之前,確定自正式壓接中的晶片積層體起至藉由用於正式壓接的加熱而升溫的基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離,於臨時壓接步驟中,使臨時壓接狀態的晶片積層體彼此隔開間隔距離以上而形成。
Description
本發明是有關於一種將一個以上的半導體晶片積層於基板上的多個部位並進行封裝的半導體裝置的製造方法以及將半導體晶片封裝於基板的封裝裝置。
一直以來要求半導體裝置的進一步的高功能化、小型化。因此,已部分地提出了積層多個半導體晶片並進行封裝。通常,於半導體晶片的單面設置有凸塊、及覆蓋該凸塊的非導電性膜(以下稱為「NCF」)。NCF包含熱硬化性樹脂,若不足規定的硬化開始溫度,則伴隨溫度上升而可逆地軟化,但若超過硬化開始溫度,則伴隨溫度上升而不可逆地硬化。為了對所述半導體晶片進行積層封裝,提出了一面對多個半導體晶片進行臨時壓接,一面進行積層,從而形成臨時壓接狀態的晶片積層體,之後對該臨時壓接狀態的晶片積層體進行加熱加壓並進行正式壓接。再者,臨時壓接中,以NCF軟化的溫度對半導體晶片進行加熱加壓。另外,正式壓接中,以構成晶片積層體的全部多個半導體晶片的凸塊熔融且NCF硬化的溫度對晶片積層體進行加熱加壓。
此種積層技術例如於專利文獻1中有所揭示。於該專利文獻1中,預先將熱硬化性接著劑膜層壓於半導體晶片中的凸塊(bump)形成面。當進行積層封裝時,首先一面將多個半導體晶
片依次臨時壓接於基板或其他半導體晶片之上,一面進行積層,從而形成多段臨時壓接積層體。其次,執行正式壓接步驟,即自上側對該多段臨時壓接積層體進行加壓且進行加熱,藉此使凸塊熔融,並且使熱硬化性接著劑膜硬化。根據此種技術,可於小面積中封裝更多的半導體晶片,因此能夠實現進一步的高功能化、小型化。
[現有技術文獻]
[專利文獻]
[專利文獻1]日本專利特開2014-60241號公報
而且,一般而言,將多個晶片積層體封裝於一個基板上。已部分地提出了如下技術:於封裝多個晶片積層體的情況下,於形成多個臨時壓接狀態的晶片積層體之後,對所述多個臨時壓接狀態的晶片積層體進行正式壓接。該情況下,與一個晶片積層體的臨時壓接及正式壓接結束後執行下一個晶片積層體的臨時壓接及正式壓接的情況相比,可減少臨時壓接處理與正式壓接處理的切換次數,因此能夠實現封裝步驟的進一步簡易化、縮短化。
另一方面,於為形成多個臨時壓接狀態的晶片積層體之後進行正式壓接的技術的情況下,為了進行正式壓接,對一個晶片積層體附加的熱有時亦傳遞至周邊的臨時壓接狀態的其他晶片積層體。尤其,於基板的熱傳導率高的情況下,對一個晶片積層
體附加的正式壓接用的熱可高效率地傳遞至周邊的臨時壓接狀態的其他晶片積層體。該情況下,有於位於周邊的晶片積層體的下層的半導體晶片中,發生NCF的硬化或凸塊的熔融等不期望的熱變化之虞。若於正式壓接之前發生NCF的硬化或凸塊的熔融,則該半導體晶片與基板的適當接合受到阻礙。
為了防止此種違背意願的熱變化,亦考慮到將正式壓接中的加熱溫度設定得稍低。但是,於將加熱溫度設定得稍低的情況下,有無法充分加熱至晶片積層體的下層,從而仍然產生接合不良之虞。
因此,本發明中,目的在於提供一種如下的半導體裝置的製造方法及封裝裝置,即,於形成兩個以上的臨時壓接狀態的晶片積層體之後進行正式壓接的情況下,可防止經正式壓接的晶片積層體的周邊的晶片積層體中的不期望的熱變化。
本發明的半導體裝置的製造方法是將一個以上的半導體晶片積層於基板上的多個部位並進行封裝的半導體裝置的製造方法,且所述半導體裝置的製造方法的特徵在於具備:臨時壓接步驟,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體;以及正式壓接步驟,對所形成的全部所述臨時壓接狀態的晶片積層體的上表面依序加熱加壓,藉此一併對構成各晶片積層體的一個以上的半導體晶片進行正式壓接,將所述臨時
壓接步驟及正式壓接步驟重覆進行兩次以上,直至所述晶片積層體達到所需的個數,進而,具備確定步驟,即於所述臨時壓接步驟之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離,於所述臨時壓接步驟中,使所述臨時壓接狀態的晶片積層體彼此隔開所述間隔距離以上而形成,且於所述正式壓接步驟中,對隔開所述間隔距離以上而形成的所述臨時壓接狀態的晶片積層體進行正式壓接。
於較佳的態樣中,所述確定步驟基於所述半導體晶片的封裝條件來確定所述間隔距離。該情況下,理想為,所述封裝條件至少包含進行所述正式壓接時的所述晶片積層體的最下層的溫度即下層溫度,且所述確定步驟中,以所述下層溫度越高則所述間隔距離越長的方式確定所述間隔距離。
於另一較佳的態樣中,於所述半導體晶片的積層方向單側端面設置有用於將所述半導體晶片與鄰接封裝於所述積層方向單側的基板或半導體晶片固著的熱硬化性樹脂,且所述容許溫度較所述熱硬化性樹脂不可逆地開始硬化的硬化開始溫度低。
於另一有效的態樣中,進而具備:分佈圖(map)形成步驟,基於所述所確定的間隔距離來形成表示多個晶片積層體的形成位置的分佈圖,於所述臨時壓接步驟中,按照所述分佈圖來形成所述多個所述臨時壓接狀態的晶片積層體。
於另一較佳的態樣中,進而,配置有所述晶片積層體的
多個配置區域以規定的間距P呈格子狀排列設定於所述基板,所述確定步驟確定所述間隔距離之後,進而確定當將所述間隔距離設為Dd時滿足{(N-1)×P}≦Dd<N×P的整數N,且於所述臨時壓接步驟中,每隔N個所述配置區域來形成所述臨時壓接狀態的晶片積層體。
於另一較佳的態樣中,所述基板為半導體晶圓。
另一本發明即半導體裝置的製造方法的特徵在於具備:臨時壓接步驟,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體;以及正式壓接步驟,將對兩個以上的臨時壓接狀態的晶片積層體的上表面同時加熱加壓且同時進行正式壓接的處理重覆進行兩次以上,並使於所述臨時壓接步驟中形成的所有臨時壓接狀態的晶片積層體變化為正式壓接狀態,將所述臨時壓接步驟及正式壓接步驟重覆進行兩次以上,直至所述晶片積層體達到所需的個數,進而,具備確定步驟,即,於所述臨時壓接步驟之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離,且於所述臨時壓接步驟中,使未同時經正式壓接的臨時壓接狀態的晶片積層體彼此隔開所述間隔距離以上而形成。
另一本發明即封裝裝置是將一個以上的半導體晶片積層於基板上的多個部位並進行封裝的封裝裝置,且所述封裝裝置
的特徵在於具備:臨時壓接機構,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體;正式壓接機構,對所形成的全部所述臨時壓接狀態的晶片積層體的上表面依序加熱加壓,藉此一併對構成各晶片積層體的一個以上的半導體晶片進行正式壓接;以及間隔距離確定機構,於所述臨時壓接之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離,且所述臨時壓接機構使所述臨時壓接狀態的晶片積層體彼此隔開所確定的所述間隔距離以上而形成,所述正式壓接機構對隔開所述間隔距離以上而形成的所述臨時壓接狀態的晶片積層體進行正式壓接。
另一本發明即封裝裝置是將一個以上的半導體晶片積層於基板上的多個部位並進行封裝的封裝裝置,且所述封裝裝置的特徵在於具備:接合部,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體,並且對所形成的全部所述臨時壓接狀態的晶片積層體的上表面依序加熱加壓,藉此一併對構成各晶片積層體的一個以上的半導體晶片進行正式壓接;間隔距離確定機構,於所述臨時壓接之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離;以及控
制部,將所述接合部控制成:使所述臨時壓接狀態的晶片積層體彼此隔開所述間隔距離以上而形成之後,對所形成的所述臨時壓接狀態的晶片積層體進行正式壓接。
根據本發明,於正式壓接中的晶片積層體的附近不存在臨時壓接狀態的晶片積層體,因此可防止由正式壓接的熱引起的晶片積層體中的不期望的熱變化。
10‧‧‧半導體晶片
14、16、32‧‧‧電極端子
18‧‧‧凸塊
20‧‧‧NCF
30‧‧‧基板
34‧‧‧配置區域
100‧‧‧封裝裝置
102‧‧‧晶片供給部
104‧‧‧晶片搬送部
106‧‧‧接合部
110‧‧‧頂起部
114‧‧‧晶片拾取器
116‧‧‧移送頭
118‧‧‧旋轉台
120‧‧‧平台
122、122a‧‧‧封裝頭
130‧‧‧控制部
132‧‧‧臨時壓接部
134‧‧‧正式壓接部
136‧‧‧間隔距離確定部
138‧‧‧存儲部
A~P‧‧‧區域
Dd‧‧‧間隔距離
P‧‧‧配置間距
Ra、Rb‧‧‧旋轉軸
ST‧‧‧晶片積層體
T1‧‧‧第一溫度
T2‧‧‧第二溫度
Ta‧‧‧下層溫度
Td‧‧‧容許溫度
TE‧‧‧切割膠帶
△T‧‧‧溫度
圖1是本發明的實施形態即封裝裝置的概略構成圖。
圖2是作為基板而發揮功能的半導體晶圓的概略立體圖。
圖3是表示被封裝的半導體晶片的構成的圖。
圖4是表示半導體裝置的構成的圖。
圖5(a)~圖5(c)是表示積層多個半導體晶片並進行封裝的流程的圖。
圖6(a)~圖6(c)是表示積層多個半導體晶片並進行封裝的流程的圖。
圖7是表示半導體晶片的封裝與基板溫度的關係的圖。
圖8是表示間隔距離分佈圖的一例的圖。
圖9是表示熱傳導特性資料的一例的圖。
圖10是表示晶片積層體的形成位置的一例的圖。
圖11是表示晶片積層體的形成位置的另一例的圖。
以下,參照圖式來對本發明的實施形態進行說明。圖1是本發明的實施形態即封裝裝置100的概略構成圖。該封裝裝置100為將半導體晶片10封裝於基板30之上的裝置。該封裝裝置100的構成尤其適合於積層多個半導體晶片10並進行封裝的情況。
封裝裝置100具備:晶片供給部102、晶片搬送部104、接合部106及對該些部分的驅動進行控制的控制部130。晶片供給部102為將半導體晶片10自晶片供給源取出,並供給至晶片搬送部104的部位。該晶片供給部102具備:頂起部110、晶片拾取器(die picker)114及移送頭116。
於晶片供給部102中,多個半導體晶片10載置於切割膠帶(dicing tape)TE上。此時,半導體晶片10是以凸塊18朝向上側的面朝上狀態被載置。頂起部110自所述多個半導體晶片10中,僅將一個半導體晶片10以面朝上狀態向上方頂起。晶片拾取器114利用其下端來吸引保持並接受由頂起部110頂起的半導體晶片10。接受了半導體晶片10的晶片拾取器114以使該半導體晶片10的凸塊18朝向下方的方式,即以使半導體晶片10成為面朝下狀態的方式,當場旋轉180度。若成為該狀態,則移送頭116會自晶片拾取器114接受半導體晶片10。
移送頭116能夠沿上下方向及水平方向移動,且可利用其下端來吸附保持半導體晶片10。若晶片拾取器114旋轉180度,
半導體晶片10成為面朝下狀態,則移送頭116會利用其下端來吸附保持該半導體晶片10。之後,移送頭116沿水平方向及上下方向移動,向晶片搬送部104移動。
晶片搬送部104具有以鉛垂的旋轉軸Ra為中心而旋轉的旋轉台118。移送頭116將半導體晶片10載置於旋轉台118的規定位置。載置有半導體晶片10的旋轉台118以旋轉軸Ra為中心而旋轉,藉此將該半導體晶片10搬送至位於晶片供給部102的相反側的接合部106。
接合部106具備:對基板30進行支撐的平台120或者將半導體晶片10保持並安裝於基板30的封裝頭122等。平台120能夠沿水平方向移動,對所載置的基板30與封裝頭122之間的相對位置關係進行調整。另外,亦可於該平台120中內置加熱器。
封裝頭122可於其下端保持半導體晶片10,另外,能夠圍繞鉛垂的旋轉軸Rb旋轉與升降。該封裝頭122將半導體晶片10壓接於平台120所載置的基板30或其他半導體晶片10之上。
具體而言,封裝頭122下降,以將所保持的半導體晶片10按壓至基板30等,藉此對半導體晶片10進行臨時壓接或正式壓接。該封裝頭122中內置有溫度可變的加熱器,封裝頭122於執行臨時壓接時,被加熱至後述的第一溫度T1,於執行正式壓接時,被加熱至較第一溫度T1高的第二溫度T2。另外,封裝頭122於執行臨時壓接時,將第一負載F1附加至半導體晶片10,於執行正式壓接時,將第二負載F2附加至半導體晶片10。
於封裝頭122的附近設置有相機(未圖示)。於基板30及半導體晶片10分別標識有成為定位基準的對準標記(alignment mark)。相機是以映出該對準標記的方式來拍攝基板30及半導體晶片10。控制部130基於藉由該拍攝而獲得的圖像資料來掌握基板30及半導體晶片10的相對位置關係,且視需要,對封裝頭122的圍繞旋轉軸Rb的旋轉角度及平台120的水平位置進行調整。
控制部130對各部分的驅動進行控制,例如具備:進行各種運算的中央處理單元(Central Processing Unit,CPU)、及存儲各種資料或程式的存儲部138。控制部130自存儲部138讀取程式,藉此作為臨時壓接部132、正式壓接部134、間隔距離確定部136而發揮功能。臨時壓接部132驅動接合部106,一面對一個以上的半導體晶片依次進行臨時壓接一面進行積層,從而形成臨時壓接狀態的晶片積層體。正式壓接部134驅動接合部106,對所形成的臨時壓接狀態的晶片積層體的上表面進行加熱加壓,藉此一併對構成各晶片積層體的一個以上的半導體晶片進行正式壓接。
間隔距離確定部136於臨時壓接之前確定間隔距離。間隔距離於後文中詳細說明,是為了良好地積層半導體晶片10所需要的臨時壓接狀態的晶片積層體的間隔距離。
再者,此處所說明的封裝裝置100的構成為一例,亦可適宜變更。例如,本實施形態中,利用一個封裝頭122進行臨時壓接及正式壓接該兩者,但亦可設置臨時壓接用的封裝頭、與正式壓接用的封裝頭。另外,本實施形態中,採用了由平台120進
行水平移動的構成,但亦可採用如下構成,即,代替平台120,或除了平台120之外,封裝頭122亦進行水平移動。另外,晶片供給部102或晶片搬送部104等的構成亦可適宜變更。
其次,說明該封裝裝置100對於半導體晶片10的封裝(半導體裝置的製造)。本實施形態中,使用半導體晶圓作為基板30,將多個半導體晶片10積層封裝於該半導體晶圓(基板30)之上。因此,本實施形態的封裝製程為將半導體晶片10積層封裝於半導體晶圓的電路形成面的晶圓上晶片製程(chip on wafer process)。圖2是本實施形態中所使用的基板30(半導體晶圓)的概略概念圖。作為半導體晶圓的基板30主要包含矽,且與包含樹脂的一般的電路基板相比,具有高的熱傳導率。如圖2所示,於基板30設定有呈格子狀排列的多個配置區域34。於各配置區域34積層封裝多個半導體晶片10。配置區域34是以規定的配置間距P配設。該配置間距P的值可根據封裝對象的半導體晶片10的尺寸等適宜設定。另外,本實施形態中,將配置區域34設為大致正方形,但亦可適宜為其他形狀,例如大致長方形。
其次,簡單說明半導體晶片10的構成。圖3是表示被封裝的半導體晶片10的概略構成的圖。於半導體晶片10的上下表面形成有電極端子14、電極端子16。另外,於半導體晶片10的單面,與電極端子14相連地形成有凸塊18。凸塊18包含導電性金屬,且以規定的熔融溫度Tm熔融。
另外,於半導體晶片10的單面,以覆蓋凸塊18的方式
貼附有非導電性膜(以下稱為「NCF」)20。NCF 20作為將半導體晶片10與基板30或其他半導體晶片10接著的接著劑而發揮功能,且包含非導電性的熱硬化性樹脂,例如聚醯亞胺樹脂、環氧樹脂、丙烯酸樹脂、苯氧基樹脂、聚醚碸樹脂等。該NCF 20的厚度大於凸塊18的平均高度,藉由該NCF 20大致完全覆蓋凸塊18。
NCF 20於常溫下為固體膜,但若超過規定的軟化開始溫度Ts,則會漸漸可逆地軟化而顯現出流動性,若超過規定的硬化開始溫度Tt,則不可逆地開始硬化。
此處,軟化開始溫度Ts較凸塊18的熔融溫度Tm及硬化開始溫度Tt低。臨時壓接用的第一溫度T1高於該軟化開始溫度Ts,且低於熔融溫度Tm及硬化開始溫度Tt。另外,正式壓接用的第二溫度T2高於熔融溫度Tm及硬化開始溫度Tt。即,Ts<T1<(Tm、Tt)<T2。
當將半導體晶片10臨時壓接於基板30或下側的半導體晶片10(以下稱為「被壓接體」)時,於將封裝頭122加熱至第一溫度T1之後,對半導體晶片10加壓。此時,半導體晶片10的NCF 20藉由來自封裝頭122的導熱而被加熱至第一溫度T1附近,軟化且具有流動性。而且,藉此,NCF 20流入至半導體晶片10與被壓接體之間的間隙,從而可確實地填埋該間隙。
當將半導體晶片10正式壓接於被壓接體時,於將封裝頭122加熱至第二溫度T2之後,對半導體晶片10加壓。此時,半導體晶片10的凸塊18及NCF 20藉由來自封裝頭122的導熱而
被加熱至第二溫度T2附近。藉此,凸塊18熔融,且可熔接於相對向的被壓接體。另外,藉由該加熱,NCF 20於填埋半導體晶片10與被壓接體之間的間隙的狀態下硬化,因此半導體晶片10與被壓接體牢固地被固定。
其次,說明對半導體晶片10進行積層封裝而製造的半導體裝置。圖4是表示將多個半導體晶片10積層封裝於基板30而成的半導體裝置的構成的圖。將目標積層數的半導體晶片10分別積層封裝於多個配置區域34而構成半導體裝置。本實施形態中,將目標積層數設為「4」,將四個半導體晶片10積層封裝於一個配置區域34。以下,將積層封裝有四個半導體晶片10者稱為「晶片積層體ST」。
晶片積層體ST可藉由以下方式而形成:一面將目標積層數的半導體晶片10依次臨時壓接一面進行積層,從而形成臨時壓接狀態的晶片積層體ST之後,一面以第二溫度T2對該晶片積層體ST的上表面加熱一面加壓而進行正式壓接。而且,作為形成多個所述晶片積層體ST的順序,有以下方式:一個晶片積層體ST的臨時壓接及正式壓接結束後執行下一個晶片積層體ST的臨時壓接及正式壓接(以下稱為「串列方式」);以及將多個晶片積層體ST臨時壓接之後,對多個晶片積層體ST執行正式壓接(以下稱為「並列方式」)。並列方式是於連續執行臨時壓接之後連續執行正式壓接,因此與交替地重覆進行臨時壓接與正式壓接的串列方式相比,可大幅減少封裝頭122的溫度的切換次數等。藉由
減少溫度的切換次數,可減少用於封裝頭122的升降溫的待機時間,從而可減少封裝處理整體的處理時間。
因此,本實施形態中,亦以並列方式形成多個晶片積層體ST。但是,於為並列方式的情況下,當對一個晶片積層體ST進行正式壓接時,有時於其附近存在其他臨時壓接狀態的晶片積層體ST。該情況下,用於正式壓接的熱有時對位於附近的其他臨時壓接狀態的晶片積層體ST造成不良影響。因此,本實施形態中,使臨時壓接狀態的晶片積層體ST彼此隔開規定的間隔距離Dd以上而形成。以下,說明本實施形態中的半導體晶片10的封裝流程。
圖5(a)~圖5(c)、圖6(a)~圖6(c)是表示半導體晶片10的封裝流程的概念圖。於圖5(a)~圖5(c)、圖6(a)~圖6(c)中圖示有三個配置區域34,但為了便於說明,將該些配置區域34自左側起依次稱為區域A、區域B、區域C。另外,圖5(a)~圖5(c)、圖6(a)~圖6(c)的例子中,將間隔距離Dd設為與配置區域34的配置間距P幾乎相同。進而,以下所說明的封裝順序可於常壓下進行,亦可為了防止氣泡的夾雜等而於真空中實施。
本實施形態中,為了對多個晶片積層體ST進行封裝,重覆進行形成兩個以上的臨時壓接狀態的晶片積層體ST的臨時壓接步驟、以及依序將兩個以上的晶片積層體ST正式壓接的正式壓接步驟。
若具體地進行說明,則首先,最初如圖5(a)所示,使用封裝頭122將半導體晶片10配置於基板30上的區域A。此時,以使半導體晶片10的凸塊18與基板30上的電極端子32相向的方式,相對於半導體晶片10而對基板30進行定位。另外,此時,封裝頭122已被加熱至臨時壓接用的溫度即第一溫度T1。其次,如圖5(b)所示,利用封裝頭122,以規定的第一負載F1對半導體晶片10加壓,將半導體晶片10臨時壓接於基板30。此時,藉由來自封裝頭122的導熱,NCF 20被加熱至軟化開始溫度Ts以上而顯示出適度的流動性。藉此,NCF 20無間隙地填埋半導體晶片10與基板30之間的間隙。再者,第一負載F1只要為使凸塊18可推開已軟化的NCF 20而與基板30的電極端子32接觸,且凸塊18不會大幅度變形的程度的大小,則並無特別限定。
對第一層的半導體晶片10完成了臨時壓接之後,接著,進而將第二層的半導體晶片10臨時壓接於該經臨時壓接的第一層的半導體晶片10之上。當對第二層的半導體晶片10進行臨時壓接時,與第一層的情況同樣地,使用封裝頭122,以使第二層的半導體晶片10的凸塊18與第一層的半導體晶片10的電極端子16相向的方式,將第二層的半導體晶片10配置於第一層的半導體晶片10之上。而且,於該狀態下,以第一溫度T1對第二層的半導體晶片10進行加熱,且以第一負載F1進行加壓,將所述第二層的半導體晶片10臨時壓接於第一層的半導體晶片10。
以後,同樣地,逐步將第三層的半導體晶片10臨時壓
接於第二層的半導體晶片10之上,將第四層的半導體晶片10臨時壓接於第三層的半導體晶片10之上。圖5(c)表示於區域A中,一面對四層的半導體晶片10進行臨時壓接,一面進行積層的情形。積層有該四個半導體晶片10的積層體成為臨時壓接狀態的晶片積層體ST。
於區域A中形成了臨時壓接狀態的晶片積層體ST之後,以同樣的順序,亦於其他配置區域34形成臨時壓接狀態的晶片積層體ST。但是,由於將臨時壓接狀態的晶片積層體ST的間隔設為間隔距離Dd以上,因此於該階段,將臨時壓接狀態的晶片積層體ST形成於區域C而不形成於區域B。圖6(c)表示於2個以上的配置區域34(區域A、區域C)形成有臨時壓接狀態的晶片積層體ST的情形。於該階段,第一次壓接步驟結束。
壓接步驟結束之後,接著,對所形成的臨時壓接狀態的晶片積層體ST依序進行正式壓接。具體而言,如圖6(b)所示,首先,將封裝頭122加熱至正式壓接用的溫度即第二溫度T2。而且,如圖6(b)所示,使用已加熱至第二溫度T2的封裝頭122,以第二負載F2對臨時壓接狀態的晶片積層體ST加壓,且一併對四個半導體晶片10進行正式壓接。再者,第二負載F2只要能適當確保凸塊18的推壓量,則並無特別限定。
因受到已加熱至第二溫度T2的封裝頭122按壓,構成晶片積層體ST的四個半導體晶片10亦被加熱。但是,加熱溫度會隨著遠離封裝頭122而逐步下降。具體而言,最上層(第四層)
的半導體晶片10被加熱至與第二溫度T2幾乎相同的溫度,但最下層(第一層)的半導體晶片10是以自第二溫度T2下降了△T的下層溫度Ta=T2-△T被加熱。以使該下層溫度Ta成為較熔融溫度Tm及硬化開始溫度Tt大的目標溫度的方式來設定第二溫度T2。即,於正式壓接時,構成晶片積層體ST的四個半導體晶片10均被加熱至較熔融溫度Tm及硬化開始溫度Tt高的溫度。
各半導體晶片10超過硬化開始溫度Tt地被加熱,藉此半導體晶片10的NCF 20漸漸硬化。而且,藉由NCF 20硬化,而半導體晶片10與被壓接體(基板30或下側的半導體晶片10)機械性牢固地被固著。另外,藉由超過熔融溫度Tm地被加熱,而凸塊18熔融,且可密接於相對向的電極端子32、電極端子16。而且,藉此,四個半導體晶片10及基板30成為彼此電性接合的封裝狀態。而且,一併對構成該晶片積層體ST的四個半導體晶片10進行正式壓接的步驟成為正式壓接步驟。
再者,傳遞至下層的熱經由熱傳導率高的基板30(半導體晶圓)亦傳遞至其周邊。周邊的其他晶片積層體ST有時因經由該基板30所傳遞的熱而受到不良影響。為了避免此種由熱引起的不良影響,本實施形態中,使臨時壓接狀態的晶片積層體ST隔開間隔距離Dd以上,該情況於後文中詳細說明。
對一個晶片積層體ST完成了正式壓接之後,接著,亦對其他晶片積層體ST進行正式壓接。即,於區域C等全部兩個以上的配置區域34依序執行正式壓接。而且,對所形成的全部臨時
壓接狀態的晶片積層體ST進行正式壓接之後,接著執行第二次臨時壓接步驟。即,於第一次臨時壓接步驟中未形成晶片積層體ST的配置區域、圖6(a)~圖6(c)的例子中區域B等形成臨時壓接狀態的晶片積層體ST。圖6(c)是表示第二次臨時壓接步驟的情形的圖。與第一次臨時壓接步驟同樣地,於兩個以上的配置區域形成了臨時壓接狀態的晶片積層體ST之後,其次實施依序對該些晶片積層體ST進行正式壓接的第二次正式壓接步驟。以後,於所需的全部配置區域中重覆進行臨時壓接步驟與正式壓接步驟,直至可將晶片積層體ST封裝,從而封裝處理結束。
如由以上說明可知,本實施形態中,為於兩個以上的配置區域34連續進行臨時壓接之後連續進行正式壓接的並列方式。
因此,與對各配置區域34重覆執行臨時壓接與正式壓接的串列方式相比,可減少封裝頭122的溫度的切換次數。因此,可減少用於升溫或降溫的待機時間,從而可大幅減少封裝處理整體的時間。
而且,如根據說明可知,本實施形態中,使臨時壓接狀態的晶片積層體ST彼此隔開規定的間隔距離Dd以上而形成。參照圖7來說明設為所述構成的理由。圖7中,上半部分是表示半導體晶片10的封裝過程的概念圖,下半部分是表示基板30的表面溫度的圖表。
如圖7所示,另外,如已說明般,當一面藉由以第二溫度T2被加熱的封裝頭122對積層於區域A的晶片積層體ST的上表面加熱一面加壓時,下層的半導體晶片10被加熱至相較於NCF
20的硬化開始溫度Tt、凸塊18的熔融溫度Tm而充分高的下層溫度Ta。此時,與下層的半導體晶片10鄰接的區域A中的基板30的溫度亦高於硬化開始溫度Tt及熔融溫度Tm。另外,作為半導體晶圓的基板30由於熱傳導率比較高,因此自下層的半導體晶片10受到的熱進而傳遞至其周邊。結果,不僅於區域A,而且於鄰接的區域B,表面溫度亦有時超過硬化開時溫度Tt及熔融溫度Tm。
於該情況下,若於區域B存在臨時壓接狀態的晶片積層體ST,則該晶片積層體ST的NCF 20於正式壓接前開始硬化,或者凸塊18開始熔融。若於正式壓接之前發生NCF 20的硬化或者凸塊18的熔融,則會導致半導體晶片10與基板的接合不良。另外,即使為不會發生NCF 20的硬化或者凸塊18的熔融的情況,亦有長時間暴露於高溫下,從而發生不期望的熱變化之虞。
因此,本實施形態中,預先確定自正式壓接中的晶片積層體ST起至藉由用於該正式壓接的熱而升溫的基板30的溫度成為規定的容許溫度Td以下的部位為止的距離即間隔距離Dd。而且,以全部臨時壓接狀態的晶片積層體ST彼此隔開間隔距離Dd以上的方式來決定晶片積層體ST的形成部位。
容許溫度Td只要為NCF 20不可逆地開始硬化的硬化開始溫度Tt以下且凸塊18開始熔融的熔融溫度Tm以下,則並無特別限定。間隔距離Dd為自正式壓接中的晶片積層體ST起至表面溫度成為容許溫度Td的部位為止的距離,但該間隔距離Dd的確
定方式亦無特別限定。例如,亦可向用戶提醒輸入間隔距離Dd而將由用戶輸入的值確定為間隔距離Dd。該情況下,用戶預先藉由實驗或模擬等求出間隔距離Dd。
另外,作為另一形態,亦可由封裝裝置100的控制部基於封裝條件來確定間隔距離Dd。例如,控制部亦可基於經正式壓接的晶片積層體ST的下層的半導體晶片10的溫度即下層溫度Ta來確定間隔距離Dd。此處,下層溫度Ta為未藉由感測器等檢測的未知的值。但是,正式壓接時的封裝頭122的溫度即第二溫度T2被設定為如使下層溫度Ta成為熔融溫度Tm及硬化開始溫度Tt以上即目標溫度般的溫度。該目標溫度預先為已知,因此可將該目標溫度視為下層溫度Ta。
控制部預先存儲表示下層溫度Ta與間隔距離Dd的關聯的間隔距離分佈圖。圖8是表示間隔距離分佈圖的一例的圖。若下層溫度Ta為容許溫度Td以下,則間隔距離Dd為0,但隨著下層溫度Ta超過容許溫度Td地上升,間隔距離Dd亦逐步上升。控制部使正式壓接時的實際所使用的第二溫度T2對照該間隔距離分佈圖來確定間隔距離Dd。
另外,間隔距離Dd亦因基板30的導熱特性而不同。認為即使下層溫度Ta相同,基板30的導熱特性越高,則間隔距離Dd亦越長。因此,根據基板30的導熱特性,亦可預先準備多種間隔距離分佈圖。圖8中,實線表示導熱特性低的情況下的間隔距離Dd,一點鏈線表示導熱特性高的情況下的間隔距離Dd,虛
線表示導熱特性為中等程度的情況下的間隔距離Dd。
基板30的導熱特性因基板30的形狀(厚度)、或材質等特徵的差異而不同。因此,控制部亦可預先存儲表示基板30的特徵與導熱特性的相關關係的導熱特性資料,並基於該導熱特性資料來確定基板30的導熱特性。圖9是表示導熱特性資料的一例的圖。控制部使實際所使用的基板30的厚度及材質對照導熱特性資料來確定該基板30的導熱特性。詳細來說,在圖9所繪示的表中,對應「厚度」欄位的「第一厚度~第三厚度」用以表示不同的厚度;對應「材質」欄位的「第一材質~第N材質」用以表示不同的材質。如此一來,控制部可藉由比對基板30的材質與「材質」欄位的「第一材質~第N材質」以及比對基板30的厚度與「厚度」欄位的「第一厚度~第三厚度」來對照到對應基板30的導熱特性資料為「高」、「中」、「低」的其中一者,進而可確定基板30的導熱特性。
另外,間隔距離Dd進而亦因正式壓接的持續時間、或周邊的環境溫度而不同。因而,當確定間隔距離Dd時,除所述下層溫度Ta及導熱特性以外,進而亦可考慮正式壓接的持續時間、環境溫度等。例如亦可為,即使下層溫度Ta及導熱特性相同,正式壓接的持續時間越長,另外環境溫度越高,則間隔距離Dd亦越長。
進而,至此為止所說明的間隔距離Dd的確定方法為一例,亦可適宜變更。例如,所述形態中,將預先設定的目標溫度
作為下層溫度Ta來處理。但是,亦可基於正式壓接時的封裝頭122的溫度即第二溫度T2及晶片積層體ST的晶片積層數或高度來推斷下層溫度Ta。
其次,對臨時壓接狀態的晶片積層體ST的形成位置的確定方法進行說明。如反覆所說明般,本實施形態中,使臨時壓接狀態的晶片積層體ST彼此隔開間隔距離Dd以上。為了滿足該條件,本實施形態中,以數個為單位空開配置區域34來配置臨時壓接狀態的晶片積層體ST。具體而言,於將配置區域34的配置間距設為P的情況下,控制部確定滿足{(N-1)×P}≦Dd<N×P的整數N。而且,於臨時壓接步驟中,每隔N個配置區域來形成臨時壓接狀態的晶片積層體ST。
參照圖10來說明該情況。圖10表示將多個晶片積層體ST形成於設定有4×4=16個配置區域34的基板30的情形。圖10中,空白的矩形表示臨時壓接狀態的晶片積層體ST,施以影線的矩形表示正式壓接後的晶片積層體ST。另外,為了便於說明,將多個配置區域34自左下起依次稱為區域A、區域B、…、區域P。
該例子中,配置區域34的配置間距為P,間隔距離Dd設為0.3×P。該情況下,Dd=0.3×P大於0且小於P,因此滿足{(N-1)×P}≦Dd<N×P的整數N為「1」。因而,該情況下,臨時壓接狀態的晶片積層體ST每隔一個配置區域而配置於配置區域。
即,如圖10的左上所示,於第一次臨時壓接步驟中,於將臨時壓接狀態的晶片積層體ST形成於區域A的情況下,亦將
臨時壓接狀態的晶片積層體ST形成於自該區域A觀察而於縱向及橫向上跳過一個配置區域34所得的區域C、區域I以及與區域C、區域I相距一個配置區域34的區域K。而且,於區域A、區域C、區域K、區域I形成了臨時壓接狀態的晶片積層體ST之後,接著,依序對所述四個晶片積層體ST進行正式壓接。即使進行了正式壓接,因於基板30成為高溫的區域(不足間隔距離Dd的區域)不存在其他臨時壓接狀態的晶片積層體ST,因此亦可防止違背意願的NCF 20的硬化或者凸塊18的熔融等不期望的熱變化。
於第二次臨時壓接步驟中,將臨時壓接狀態的晶片積層體ST形成於空開的配置區域34。例如,於第二次臨時壓接步驟中,於將臨時壓接狀態的晶片積層體ST形成於區域B的情況下,亦將臨時壓接狀態的晶片積層體ST形成於自該區域B觀察而於縱向及橫向上跳過一個配置區域34所得的區域D、區域J以及與區域D、區域J相距一個配置區域34的區域L。而且,於區域B、區域D、區域L、區域J形成了臨時壓接狀態的晶片積層體ST之後,接著,依序對所述四個晶片積層體ST進行正式壓接。即,執行第二次正式壓接步驟。此時,於經正式壓接的晶片積層體ST、例如區域B的晶片積層體ST的附近即區域A、區域C存在其他晶片積層體ST。但是,該區域A、區域C的晶片積層體ST已被正式壓接,因此即使高溫傳遞至區域A、區域C的晶片積層體ST,亦不會出現問題。即,該情況下,亦可防止違背意願的NCF 20的硬化或者凸塊18的熔融等不期望的熱變化。第二次壓接步驟結束
後,之後亦同樣地,重覆進行臨時壓接步驟與正式壓接步驟,於空開的區域以跳過一個區域的間隔形成晶片積層體ST。
如所述般,本實施形態中,確定滿足{(N-1)×P}≦Dd<N×P的整數N,並基於該整數N來確定臨時壓接狀態的晶片積層體ST的形成位置。再者,此種形成位置的確定亦可於執行臨時壓接步驟的時候隨時進行。另外,作為另一形態,亦可於第一次臨時壓接步驟之前確定臨時壓接狀態的晶片積層體ST的形成位置。即,亦可於第一次臨時壓接步驟之前,基於間隔距離Dd來預先形成表示各臨時壓接步驟的晶片積層體ST的形成位置的分佈圖,且於實際的臨時壓接步驟中,按照該分佈圖來形成臨時壓接狀態的晶片積層體ST。
而且,於至此為止的說明中,說明了利用一個封裝頭122來執行臨時壓接及正式壓接該兩者的例子。但是,封裝頭122不必為一個,亦可設置臨時壓接用的封裝頭、與正式壓接用的封裝頭該兩者。該情況下,只要預先總是將臨時壓接專用的封裝頭加熱至第一溫度T1,且總是將正式壓接專用的封裝頭加熱至第二溫度T2即可。藉由設為所述構成,無需對封裝頭的溫度進行切換,因此可消除封裝頭升降溫所需的時間,從而可進一步縮短封裝時間。
另外,此時,正式壓接用的封裝頭亦可設為能夠同時對两個以上的晶片積層體ST進行加熱.加壓(正式壓接)的尺寸。例如,如圖11的上半部分所示,亦可將正式壓接用的封裝頭122a
設為能夠同時對四個晶片積層體ST進行正式壓接的尺寸。該情況下,同時經正式壓接的晶片積層體ST不必隔開間隔距離Dd,只要未同時經正式壓接的臨時壓接狀態的晶片積層體ST隔開間隔距離Dd以上即可。
例如,圖11的例子中,於第一次臨時壓接步驟中,只要將臨時壓接狀態的晶片積層體ST形成於區域A~區域D以及與所述區域A~區域D相距一行(間隔距離Dd以上)的區域L~區域I即可。而且,於第一次正式壓接步驟中,對區域A~區域D的晶片積層體ST同時進行正式壓接之後,對區域L~區域I的晶片積層體ST同時進行正式壓接。而且,於第二次臨時壓接步驟中,將臨時壓接狀態的晶片積層體ST形成於區域E~區域H以及區域M~區域P。於第二次正式壓接步驟中,對區域E~區域H的晶片積層體ST同時進行正式壓接,另外,對區域M~區域P的晶片積層體ST同時進行正式壓接
如此,藉由對兩個以上的晶片積層體ST同時進行正式壓接,可減少各步驟的執行次數,從而可進一步縮短封裝處理整體的時間。另外,該情況下,亦由於未同時經正式壓接的臨時壓接狀態的晶片積層體隔開間隔距離Dd以上,因此可有效地防止違背意願的NCF 20的硬化或者凸塊18的熔融。
另外,於至此為止的說明中,將各晶片積層體ST設為四層進行了說明,但只要晶片積層體ST的積層數為1以上,則並無特別限定。另外,於至此為止的說明中,作為基板30,使用了
半導體晶圓,但亦可使用其他基板。但是,本實施形態的技術尤其適合使用包含熱傳導性比較高的材料的基板的情況。
Claims (10)
- 一種半導體裝置的製造方法,其為將一個以上的半導體晶片積層於基板上的多個部位並進行封裝的半導體裝置的製造方法,且所述半導體裝置的製造方法的特徵在於具備:臨時壓接步驟,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體;以及正式壓接步驟,對所形成的全部所述臨時壓接狀態的晶片積層體的上表面依序加熱加壓,藉此一併對構成各晶片積層體的一個以上的半導體晶片進行正式壓接,將所述臨時壓接步驟及正式壓接步驟重覆進行兩次以上,直至所述晶片積層體達到所需的個數,進而,具備確定步驟,即,於所述臨時壓接步驟之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離,於所述臨時壓接步驟中,使所述臨時壓接狀態的晶片積層體彼此隔開所述間隔距離以上而形成,且於所述正式壓接步驟中,對隔開所述間隔距離以上而形成的所述臨時壓接狀態的晶片積層體進行正式壓接。
- 如申請專利範圍第1項所述的半導體裝置的製造方法,其中所述確定步驟基於所述半導體晶片的封裝條件來確定所述間隔距離。
- 如申請專利範圍第2項所述的半導體裝置的製造方法,其中包含進行所述正式壓接時的所述晶片積層體的最下層的溫度即下層溫度,且所述確定步驟中,以所述下層溫度越高則所述間隔距離越長的方式確定所述間隔距離。
- 如申請專利範圍第1項至第3項中任一項所述的半導體裝置的製造方法,其中於所述半導體晶片的積層方向單側端面設置有用於將所述半導體晶片與鄰接封裝於所述積層方向單側的基板或半導體晶片固著的熱硬化性樹脂,且所述容許溫度較所述熱硬化性樹脂不可逆地開始硬化的硬化開始溫度低。
- 如申請專利範圍第1項至第3項中任一項所述的半導體裝置的製造方法,其進而具備:分佈圖形成步驟,基於所述所確定的間隔距離來形成表示多個晶片積層體的形成位置的分佈圖,於所述臨時壓接步驟中,按照所述分佈圖來形成所述多個所述臨時壓接狀態的晶片積層體。
- 如申請專利範圍第1項至第3項中任一項所述的半導體裝置的製造方法,其中,進而配置有所述晶片積層體的多個配置區域以規定的間距P呈格子狀排列設定於所述基板,所述確定步驟確定所述間隔距離之後,進而確定當將所述間隔距離設為Dd時滿足{(N-1)×P}≦Dd<N×P的整數N,且於所述臨時壓接步驟中,每隔N個所述配置區域來形成所述臨時壓接狀態的晶片積層體。
- 如申請專利範圍第1項至第3項中任一項所述的半導體裝置的製造方法,其中所述基板為半導體晶圓。
- 一種半導體裝置的製造方法,其特徵在於具備:臨時壓接步驟,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體;以及正式壓接步驟,將對兩個以上的臨時壓接狀態的晶片積層體的上表面同時加熱加壓且同時進行正式壓接的處理重覆進行兩次以上,並使於所述臨時壓接步驟中形成的所有臨時壓接狀態的晶片積層體變化為正式壓接狀態,將所述臨時壓接步驟及正式壓接步驟重覆進行兩次以上,直至所述晶片積層體達到所需的個數,進而,具備確定步驟,即,於所述臨時壓接步驟之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離,且於所述臨時壓接步驟中,使未同時經正式壓接的臨時壓接狀態的晶片積層體彼此隔開所述間隔距離以上而形成。
- 一種封裝裝置,其為將一個以上的半導體晶片積層於基板上的多個部位並進行封裝的封裝裝置,且所述封裝裝置的特徵在於具備:臨時壓接機構,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體;正式壓接機構,對所形成的全部所述臨時壓接狀態的晶片積層體的上表面依序加熱加壓,藉此一併對構成各晶片積層體的一個以上的半導體晶片進行正式壓接;以及間隔距離確定機構,於所述臨時壓接之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離,且所述臨時壓接機構使所述臨時壓接狀態的晶片積層體彼此隔開所確定的所述間隔距離以上而形成,所述正式壓接機構對隔開所述間隔距離以上而形成的所述臨時壓接狀態的晶片積層體進行正式壓接。
- 一種封裝裝置,其為將一個以上的半導體晶片積層於基板上的多個部位並進行封裝的封裝裝置,且所述封裝裝置的特徵在於具備:接合部,一面將一個以上的半導體晶片依次分別臨時壓接於所述基板上的兩個以上的部位,一面進行積層,從而形成臨時壓接狀態的晶片積層體,並且對所形成的全部所述臨時壓接狀態的晶片積層體的上表面依序加熱加壓,藉此一併對構成各晶片積層體的一個以上的半導體晶片進行正式壓接;間隔距離確定機構,於所述臨時壓接之前,確定自正式壓接中的晶片積層體起至藉由用於所述正式壓接的加熱而升溫的所述基板的溫度成為規定的容許溫度以下的部位為止的距離即間隔距離;以及控制部,將所述接合部控制成:使所述臨時壓接狀態的晶片積層體彼此隔開所述間隔距離以上而形成之後,對所形成的所述臨時壓接狀態的晶片積層體進行正式壓接。
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2016194945A JP6349538B2 (ja) | 2016-09-30 | 2016-09-30 | 半導体装置の製造方法および実装装置 |
JP2016-194945 | 2016-09-30 |
Publications (2)
Publication Number | Publication Date |
---|---|
TW201816903A TW201816903A (zh) | 2018-05-01 |
TWI659479B true TWI659479B (zh) | 2019-05-11 |
Family
ID=61759677
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW106133433A TWI659479B (zh) | 2016-09-30 | 2017-09-28 | 半導體裝置的製造方法以及封裝裝置 |
Country Status (6)
Country | Link |
---|---|
US (1) | US10896901B2 (zh) |
JP (1) | JP6349538B2 (zh) |
KR (1) | KR102147681B1 (zh) |
CN (1) | CN110024095B (zh) |
TW (1) | TWI659479B (zh) |
WO (1) | WO2018062423A1 (zh) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6349539B2 (ja) * | 2016-09-30 | 2018-07-04 | 株式会社新川 | 半導体装置の製造方法および実装装置 |
KR102457039B1 (ko) * | 2017-12-27 | 2022-10-20 | 삼성디스플레이 주식회사 | 본딩 장치 및 이를 이용한 표시 패널의 제조 방법 |
CN110858552B (zh) * | 2018-08-24 | 2022-06-17 | 上海微电子装备(集团)股份有限公司 | 一种键合设备和键合方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013021058A (ja) * | 2011-07-08 | 2013-01-31 | Elpida Memory Inc | 半導体装置の製造方法 |
JP2013080758A (ja) * | 2011-10-03 | 2013-05-02 | Panasonic Corp | 半導体素子の実装方法 |
JP2014060241A (ja) * | 2012-09-18 | 2014-04-03 | Toray Ind Inc | 半導体装置の製造方法 |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2004006465A (ja) * | 2002-05-31 | 2004-01-08 | Renesas Technology Corp | 半導体装置の製造方法 |
US8552567B2 (en) * | 2011-07-27 | 2013-10-08 | Micron Technology, Inc. | Semiconductor die assemblies, semiconductor devices including same, and methods of fabrication |
JP6044885B2 (ja) * | 2012-08-08 | 2016-12-14 | パナソニックIpマネジメント株式会社 | 実装方法 |
JP2015005637A (ja) * | 2013-06-21 | 2015-01-08 | ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. | 半導体装置 |
JP6518461B2 (ja) * | 2015-03-03 | 2019-05-22 | 東レエンジニアリング株式会社 | 実装装置および実装方法 |
-
2016
- 2016-09-30 JP JP2016194945A patent/JP6349538B2/ja active Active
-
2017
- 2017-09-28 US US16/337,926 patent/US10896901B2/en active Active
- 2017-09-28 TW TW106133433A patent/TWI659479B/zh active
- 2017-09-28 CN CN201780074330.7A patent/CN110024095B/zh active Active
- 2017-09-28 KR KR1020197011969A patent/KR102147681B1/ko active IP Right Grant
- 2017-09-28 WO PCT/JP2017/035323 patent/WO2018062423A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2013021058A (ja) * | 2011-07-08 | 2013-01-31 | Elpida Memory Inc | 半導体装置の製造方法 |
JP2013080758A (ja) * | 2011-10-03 | 2013-05-02 | Panasonic Corp | 半導体素子の実装方法 |
JP2014060241A (ja) * | 2012-09-18 | 2014-04-03 | Toray Ind Inc | 半導体装置の製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US10896901B2 (en) | 2021-01-19 |
JP6349538B2 (ja) | 2018-07-04 |
US20190312020A1 (en) | 2019-10-10 |
TW201816903A (zh) | 2018-05-01 |
KR102147681B1 (ko) | 2020-08-26 |
CN110024095A (zh) | 2019-07-16 |
CN110024095B (zh) | 2023-04-18 |
JP2018060824A (ja) | 2018-04-12 |
WO2018062423A1 (ja) | 2018-04-05 |
KR20190051067A (ko) | 2019-05-14 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI652743B (zh) | 半導體晶片的封裝裝置以及半導體裝置的製造方法 | |
TWI670776B (zh) | 半導體裝置的製造方法以及封裝裝置 | |
US8377745B2 (en) | Method of forming a semiconductor device | |
TW201336039A (zh) | 製造半導體裝置之方法 | |
TWI555099B (zh) | Semiconductor device manufacturing method and semiconductor device | |
TWI659479B (zh) | 半導體裝置的製造方法以及封裝裝置 | |
TW201426928A (zh) | 具有在封裝間之電絕緣材料之層疊封裝(PoP) | |
TWI673805B (zh) | 安裝裝置以及安裝系統 | |
JP2012146853A (ja) | 半導体装置の製造方法 | |
TWI607516B (zh) | Semiconductor device manufacturing method and manufacturing apparatus | |
KR101750206B1 (ko) | 반도체 실장 장치의 가열 헤더 및 반도체의 접합 방법 | |
KR101619455B1 (ko) | 적층형 반도체 패키지의 제조방법 | |
WO2010104001A1 (ja) | 電子装置の製造方法及び電子装置の製造装置 |