CN110024095A - 半导体装置的制造方法以及封装装置 - Google Patents

半导体装置的制造方法以及封装装置 Download PDF

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CN110024095A
CN110024095A CN201780074330.7A CN201780074330A CN110024095A CN 110024095 A CN110024095 A CN 110024095A CN 201780074330 A CN201780074330 A CN 201780074330A CN 110024095 A CN110024095 A CN 110024095A
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interim
die
stacks
crimped
semiconductor chip
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CN110024095B (zh
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中村智宣
前田彻
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Arakawa Co Ltd
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Arakawa Co Ltd
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Abstract

本发明具备：临时压接步骤，一面将一个以上的半导体芯片10依次分别临时压接于基板30上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体ST；以及正式压接步骤，对所形成的全部所述临时压接状态的芯片层叠体ST的上表面依序加热加压并进行正式压接，进而，具备确定步骤，即，在所述临时压接步骤之前，确定自正式压接中的芯片层叠体ST起至通过用于所述正式压接的加热而升温的所述基板30的温度成为规定的容许温度Td以下的部位为止的距离即间隔距离Dd，在所述临时压接步骤中，使所述临时压接状态的芯片层叠体ST彼此隔开所述间隔距离Dd以上而形成。

Description

半导体装置的制造方法以及封装装置
技术领域
本发明涉及一种将一个以上的半导体芯片层叠于基板上的多个部位并进行封装的半导体装置的制造方法以及将半导体芯片封装于基板的封装装置。
背景技术
一直以来要求半导体装置的进一步的高功能化、小型化。因此，已部分地提出了层叠多个半导体芯片并进行封装。通常，在半导体芯片的单面设置有凸块、及覆盖所述凸块的被导电性膜(以下称为“NCF”)。NCF包含热硬化性树脂，若不足规定的硬化开始温度，则伴随温度上升而可逆地软化，但若超过硬化开始温度，则伴随温度上升而不可逆地硬化。为了对所述半导体芯片进行层叠封装，提出了一面对多个半导体芯片进行临时压接，一面进行层叠，从而形成临时压接状态的芯片层叠体，之后对所述临时压接状态的芯片层叠体进行加热加压并进行正式压接。再者，临时压接中，以NCF软化的温度对半导体芯片进行加热加压。另外，正式压接中，以构成芯片层叠体的全部多个半导体芯片的凸块熔融且NCF硬化的温度对芯片层叠体进行加热加压。
此种层叠技术例如在专利文献1中有所公开。在所述专利文献1中，预先将热硬化性接着剂膜层压于半导体芯片中的凸块(bump)形成面。当进行层叠封装时，首先一面将多个半导体芯片依次临时压接于基板或其他半导体芯片之上，一面进行层叠，从而形成多段临时压接层叠体。其次，执行正式压接步骤，即自上侧对所述多段临时压接层叠体进行加压且进行加热，由此使凸块熔融，并且使热硬化性接着剂膜硬化。根据此种技术，可在小面积中封装更多的半导体芯片，因此能够实现进一步的高功能化、小型化。
现有技术文献
专利文献
专利文献1：日本专利特开2014-60241号公报
发明内容
发明所要解决的问题
而且，一般而言，将多个芯片层叠体封装于一个基板上。已部分地提出了如下技术：在封装多个芯片层叠体的情况下，在形成多个临时压接状态的芯片层叠体之后，对所述多个临时压接状态的芯片层叠体进行正式压接。所述情况下，与一个芯片层叠体的临时压接及正式压接结束后执行下一个芯片层叠体的临时压接及正式压接的情况相比，可减少临时压接处理与正式压接处理的切换次数，因此能够实现封装步骤的进一步简易化、缩短化。
另一方面，在为形成多个临时压接状态的芯片层叠体之后进行正式压接的技术的情况下，为了进行正式压接，对一个芯片层叠体附加的热有时也传递至周边的临时压接状态的其他芯片层叠体。尤其，在基板的热传导率高的情况下，对一个芯片层叠体附加的正式压接用的热可高效率地传递至周边的临时压接状态的其他芯片层叠体。所述情况下，有在位于周边的芯片层叠体的下层的半导体芯片中，发生NCF的硬化或凸块的熔融等不期望的热变化之虞。若在正式压接之前发生NCF的硬化或凸块的熔融，则所述半导体芯片与基板的适当接合受到阻碍。
为了防止此种违背意愿的热变化，也考虑到将正式压接中的加热温度设定得稍低。但是，在将加热温度设定得稍低的情况下，有无法充分加热至芯片层叠体的下层，从而仍然产生接合不良之虞。
因此，本发明中，目的在于提供一种如下的半导体装置的制造方法及封装装置，即，在形成两个以上的临时压接状态的芯片层叠体之后进行正式压接的情况下，可防止经正式压接的芯片层叠体的周边的芯片层叠体中的不期望的热变化。
解决问题的技术手段
本发明的半导体装置的制造方法是将一个以上的半导体芯片层叠于基板上的多个部位并进行封装的半导体装置的制造方法，且所述半导体装置的制造方法的特征在于具备：临时压接步骤，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体；以及正式压接步骤，对所形成的全部所述临时压接状态的芯片层叠体的上表面依序加热加压，由此一并对构成各芯片层叠体的一个以上的半导体芯片进行正式压接，将所述临时压接步骤及所述正式压接步骤重复进行两次以上，直至所述芯片层叠体达到所需的个数，进而，具备确定步骤，即在所述临时压接步骤之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离，在所述临时压接步骤中，使所述临时压接状态的芯片层叠体彼此隔开所述间隔距离以上而形成，且在所述正式压接步骤中，对隔开所述间隔距离以上而形成的所述临时压接状态的芯片层叠体进行正式压接。
在优选的方案中，所述确定步骤基于所述半导体芯片的封装条件来确定所述间隔距离。所述情况下，理想为，所述封装条件至少包含进行所述正式压接时的所述芯片层叠体的最下层的温度即下层温度，且所述确定步骤中，以所述下层温度越高则所述间隔距离越长的方式确定所述间隔距离。
在另一优选的方案中，在所述半导体芯片的层叠方向单侧端面设置有用于将所述半导体芯片与邻接封装于所述层叠方向单侧的基板或半导体芯片固着的热硬化性树脂，且所述容许温度较所述热硬化性树脂不可逆地开始硬化的硬化开始温度低。
在另一有效的方案中，进而具备：分布图(map)形成步骤，基于所述所确定的间隔距离来形成表示多个芯片层叠体的形成位置的分布图，在所述临时压接步骤中，按照所述分布图来形成所述多个所述临时压接状态的芯片层叠体。
在另一优选的方案中，进而，配置有所述芯片层叠体的多个配置区域以规定的间距P呈格子状排列设定于所述基板，所述确定步骤确定所述间隔距离之后，进而确定当将所述间隔距离设为Dd时满足{(N-l)×P}≦Dd<N×P的整数N，且在所述临时压接步骤中，每隔N个所述配置区域来形成所述临时压接状态的芯片层叠体。
在另一优选的方案中，所述基板为半导体晶片。
另一本发明即半导体装置的制造方法的特征在于具备：临时压接步骤，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体；以及正式压接步骤，将对两个以上的临时压接状态的芯片层叠体的上表面同时加热加压且同时进行正式压接的处理重复进行两次以上，并使在所述临时压接步骤中形成的所有临时压接状态的芯片层叠体变化为正式压接状态，将所述临时压接步骤及所述正式压接步骤重复进行两次以上，直至所述芯片层叠体达到所需的个数，进而，具备确定步骤，即，在所述临时压接步骤之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离，且在所述临时压接步骤中，使未同时经正式压接的临时压接状态的芯片层叠体彼此隔开所述间隔距离以上而形成。
另一本发明即封装装置是将一个以上的半导体芯片层叠于基板上的多个部位并进行封装的封装装置，且所述封装装置的特征在于具备：临时压接机构，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体；正式压接机构，对所形成的全部所述临时压接状态的芯片层叠体的上表面依序加热加压，由此一并对构成各芯片层叠体的一个以上的半导体芯片进行正式压接；以及间隔距离确定机构，在所述临时压接之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离，且所述临时压接机构使所述临时压接状态的芯片层叠体彼此隔开所确定的所述间隔距离以上而形成，所述正式压接机构对隔开所述间隔距离以上而形成的所述临时压接状态的芯片层叠体进行正式压接。
另一本发明即封装装置是将一个以上的半导体芯片层叠于基板上的多个部位并进行封装的封装装置，且所述封装装置的特征在于具备：接合部，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体，并且对所形成的全部所述临时压接状态的芯片层叠体的上表面依序加热加压，由此一并对构成各芯片层叠体的一个以上的半导体芯片进行正式压接；间隔距离确定机构，在所述临时压接之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离；以及控制部，将所述接合部控制成：使所述临时压接状态的芯片层叠体彼此隔开所述间隔距离以上而形成之后，对所形成的所述临时压接状态的芯片层叠体进行正式压接。
发明的效果
根据本发明，在正式压接中的芯片层叠体的附近不存在临时压接状态的芯片层叠体，因此可防止由正式压接的热引起的芯片层叠体中的不期望的热变化。
附图说明
[图1]是本发明的实施方式即封装装置的概略构成图。
[图2]是作为基板而发挥功能的半导体晶片的概略立体图。
[图3]是表示被封装的半导体芯片的构成的图。
[图4]是表示半导体装置的构成的图。
[图5]是表示层叠多个半导体芯片并进行封装的流程的图。
[图6]是表示层叠多个半导体芯片并进行封装的流程的图。
[图7]是表示半导体芯片的封装与基板温度的关系的图。
[图8]是表示间隔距离分布图的一例的图。
[图9]是表示热传导特性数据的一例的图。
[图10]是表示芯片层叠体的形成位置的一例的图。
[图11]是表示芯片层叠体的形成位置的另一例的图。
具体实施方式
以下，参照附图来对本发明的实施方式进行说明。图1是本发明的实施方式即封装装置100的概略构成图。所述封装装置100为将半导体芯片10封装于基板30之上的装置。所述封装装置100的构成尤其适合于层叠多个半导体芯片10并进行封装的情况。
封装装置100具备：芯片供给部102、芯片搬送部104、接合部106及对这些部分的驱动进行控制的控制部130。芯片供给部102为将半导体芯片10自芯片供给源取出，并供给至芯片搬送部104的部位。所述芯片供给部102具备：顶起部110、裸片拾取器(die picker)114及移送头116。
在芯片供给部102中，多个半导体芯片10载置于切割胶带(dicing tape)TE上。此时，半导体芯片10是以凸块18朝向上侧的面朝上状态被载置。顶起部110自所述多个半导体芯片10中，仅将一个半导体芯片10以面朝上状态向上方顶起。裸片拾取器114利用其下端来吸引保持并接受由顶起部110顶起的半导体芯片10。接受了半导体芯片10的裸片拾取器114以使所述半导体芯片10的凸块18朝向下方的方式，即以使半导体芯片10成为面朝下状态的方式，当场旋转180度。若成为所述状态，则移送头116会自裸片拾取器114接受半导体芯片10。
移送头116能够沿上下方向及水平方向移动，且可利用其下端来吸附保持半导体芯片10。若裸片拾取器114旋转180度，半导体芯片10成为面朝下状态，则移送头116会利用其下端来吸附保持所述半导体芯片10。之后，移送头116沿水平方向及上下方向移动，向芯片搬送部104移动。
芯片搬送部104具有以铅垂的旋转轴Ra为中心而旋转的旋转台118。移送头116将半导体芯片10载置于旋转台118的规定位置。载置有半导体芯片10的旋转台118以旋转轴Ra为中心而旋转，由此将所述半导体芯片10搬送至位于芯片供给部102的相反侧的接合部106。
接合部106具备：对基板30进行支撑的平台120或者将半导体芯片10保持并安装于基板30的封装头122等。平台120能够沿水平方向移动，对所载置的基板30与封装头122之间的相对位置关系进行调整。另外，也可在所述平台120中内置加热器。
封装头122可在其下端保持半导体芯片10，另外，能够围绕铅垂的旋转轴Rb旋转与升降。所述封装头122将半导体芯片10压接于平台120所载置的基板30或其他半导体芯片10之上。具体而言，封装头122下降，以将所保持的半导体芯片10按压至基板30等，由此对半导体芯片10进行临时压接或正式压接。所述封装头122中内置有温度可变的加热器，封装头122在执行临时压接时，被加热至后述的第一温度T1，在执行正式压接时，被加热至较第一温度T1高的第二温度T2。另外，封装头122在执行临时压接时，将第一负载F1附加至半导体芯片10，在执行正式压接时，将第二负载F2附加至半导体芯片10。
在封装头122的附近设置有相机(未图示)。在基板30及半导体芯片10分别标识有成为定位基准的对准标记(alignment mark)。相机是以映出所述对准标记的方式来拍摄基板30及半导体芯片10。控制部130基于通过所述拍摄而获得的图像数据来掌握基板30及半导体芯片10的相对位置关系，且视需要，对封装头122的围绕轴Rb的旋转角度及平台120的水平位置进行调整。
控制部130对各部分的驱动进行控制，例如具备：进行各种运算的中央处理器(Central Processing Unit，CPU)、及存储各种数据或程序的存储部138。控制部130自存储部138读取程序，由此作为临时压接部132、正式压接部134、间隔距离确定部136而发挥功能。临时压接部132驱动接合部106，一面对一个以上的半导体芯片依次进行临时压接一面进行层叠，从而形成临时压接状态的芯片层叠体。正式压接部134驱动接合部106，对所形成的临时压接状态的芯片层叠体的上表面进行加热加压，由此一并对构成各芯片层叠体的一个以上的半导体芯片进行正式压接。间隔距离确定部136在临时压接之前确定间隔距离。间隔距离在后文中详细说明，是为了良好地层叠半导体芯片10所需要的临时压接状态的芯片层叠体的间隔距离。
再者，此处所说明的封装装置100的构成为一例，也可适宜变更。例如，本实施方式中，利用一个封装头122进行临时压接及正式压接所述两者，但也可设置临时压接用的封装头、与正式压接用的封装头。另外，本实施方式中，采用了平台120进行水平移动的构成，但也可采用如下构成，即，代替平台120，或除了平台120之外，封装头122也进行水平移动。另外，芯片供给部102或芯片搬送部104等的构成也可适宜变更。
其次，说明利用所述封装装置100的半导体芯片10的封装(半导体装置的制造)。本实施方式中，使用半导体晶片作为基板30，将多个半导体芯片10层叠封装于所述半导体晶片(基板30)之上。因此，本实施方式的封装工艺为将半导体芯片10层叠封装于半导体晶片的电路形成面的“晶片上芯片工艺(chip on wafer process)”。图2是本实施方式中所使用的基板30(半导体晶片)的概略概念图。作为半导体晶片的基板30主要包含硅，且与包含树脂的一般的电路基板相比，具有高的热传导率。如图2所示，在基板30设定有呈格子状排列的多个配置区域34。在各配置区域34层叠封装多个半导体芯片10。配置区域34是以规定的配置间距P配设。所述配置间距P的值可根据封装对象的半导体芯片10的尺寸等适宜设定。另外，本实施方式中，将配置区域34设为大致正方形，但也可适宜为其他形状，例如大致长方形。
其次，简单说明半导体芯片10的构成。图3是表示被封装的半导体芯片10的概略构成的图。在半导体芯片10的上下表面形成有电极端子14、电极端子16。另外，在半导体芯片10的单面，与电极端子14相连地形成有凸块18。凸块18包含导电性金属，且以规定的熔融温度Tm熔融。
另外，在半导体芯片10的单面，以覆盖凸块18的方式贴附有非导电性膜(以下称为“NCF”)20。NCF 20作为将半导体芯片10与基板30或其他半导体芯片10接着的接着剂而发挥功能，且包含非导电性的热硬化性树脂，例如聚酰亚胺树脂、环氧树脂、丙烯酸树脂、苯氧基树脂、聚醚砜树脂等。所述NCF 20的厚度大于凸块18的平均高度，通过所述NCF 20大致完全覆盖凸块18。NCF 20在常温下为固体膜，但若超过规定的软化开始温度Ts，则会渐渐可逆地软化而显现出流动性，若超过规定的硬化开始温度Tt，则不可逆地开始硬化。
此处，软化开始温度Ts较凸块18的熔融温度Tm及硬化开始温度Tt低。临时压接用的第一温度T1高于所述软化开始温度Ts，且低于熔融温度Tm及硬化开始温度Tt。另外，正式压接用的第二温度T2高于熔融温度Tm及硬化开始温度Tt。即，Ts＜T1＜(Tm、Tt)＜T2。
当将半导体芯片10临时压接于基板30或下侧的半导体芯片10(以下称为“被压接体”)时，在将封装头122加热至第一温度T1之后，对半导体芯片10加压。此时，半导体芯片10的NCF 20通过来自封装头122的导热而被加热至第一温度T1附近，软化且具有流动性。而且，由此，NCF 20流入至半导体芯片10与被压接体之间的间隙，从而可确实地填埋所述间隙。
当将半导体芯片10正式压接于被压接体时，在将封装头122加热至第二温度T2之后，对半导体芯片10加压。此时，半导体芯片10的凸块18及NCF 20通过来自封装头122的导热而被加热至第二温度T2附近。由此，凸块18熔融，且可熔接于相对向的被压接体。另外，通过所述加热，NCF 20在填埋半导体芯片10与被压接体之间的间隙的状态下硬化，因此半导体芯片10与被压接体牢固地被固定。
其次，说明对半导体芯片10进行层叠封装而制造的半导体装置。图4是表示将多个半导体芯片10层叠封装于基板30而成的半导体装置的构成的图。将目标层叠数的半导体芯片10分别层叠封装于多个配置区域34而构成半导体装置。本实施方式中，将目标层叠数设为“4”，将四个半导体芯片10层叠封装于一个配置区域34。以下，将层叠封装有四个半导体芯片10者称为“芯片层叠体ST”。
芯片层叠体ST可通过以下方式而形成：一面将目标层叠分的半导体芯片10依次临时压接一面进行层叠，从而形成临时压接状态的芯片层叠体ST之后，一面以第二温度T2对所述芯片层叠体ST的上表面加热一面加压而进行正式压接。而且，作为形成多个所述芯片层叠体ST的顺序，有以下方式：一个芯片层叠体ST的临时压接及正式压接结束后执行下一个芯片层叠体ST的临时压接及正式压接(以下称为“串行方式”)；以及将多个芯片层叠体ST临时压接之后，对多个芯片层叠体ST执行正式压接(以下称为“并行方式”)。并行方式是在连续执行临时压接之后连续执行正式压接，因此与交替地重复进行临时压接与正式压接的串行方式相比，可大幅减少封装头122的温度的切换次数等。通过减少温度的切换次数，可减少用于封装头122的升降温的待机时间，从而可减少封装处理整体的处理时间。
因此，本实施方式中，也以并行方式形成多个芯片层叠体ST。但是，在为并行方式的情况下，当对一个芯片层叠体ST进行正式压接时，有时在其附近存在其他临时压接状态的芯片层叠体ST。所述情况下，用于正式压接的热有时对位于附近的其他临时压接状态的芯片层叠体ST造成不良影响。因此，本实施方式中，使临时压接状态的芯片层叠体ST彼此隔开规定的间隔距离Dd以上而形成。以下，说明本实施方式中的半导体芯片10的封装流程。
图5、图6是表示半导体芯片10的封装流程的概念图。在图5、图6中图示有三个配置区域34，但为了便于说明，将这些配置区域34自左侧起依次称为区域A、区域B、区域C。另外，图5、图6的例子中，将间隔距离Dd设为与配置区域34的配置间距P几乎相同。进而，以下所说明的封装顺序可在常压下进行，也可为了防止气泡的夹杂等而在真空中实施。
本实施方式中，为了对多个芯片层叠体ST进行封装，重复进行形成两个以上的临时压接状态的芯片层叠体ST的临时压接步骤、以及依序将两个以上的芯片层叠体ST正式压接的正式压接步骤。
若具体地进行说明，则首先，最初如图5(a)所示，使用封装头122将半导体芯片10配置于基板30上的区域A。此时，以使半导体芯片10的凸块18与基板30上的电极端子32相向的方式，相对于半导体芯片10而对基板30进行定位。另外，此时，封装头122已被加热至临时压接用的温度即第一温度T1。其次，如图5(b)所示，利用封装头122，以规定的第一负载F1对半导体芯片10加压，将半导体芯片10临时压接于基板30。此时，通过来自封装头122的导热，NCF 20被加热至软化开始温度Ts以上而显示出适度的流动性。由此，NCF 20无间隙地填埋半导体芯片10与基板30之间的间隙。再者，第一负载F1只要为使凸块18可推开已软化的NCF20而与基板30的电极端子32接触，且凸块18不会大幅度变形的程度的大小，则并无特别限定。
对第一层的半导体芯片10完成了临时压接之后，接着，进而将第二层的半导体芯片10临时压接于所述经临时压接的第一层的半导体芯片10之上。当对第二层的半导体芯片10进行临时压接时，与第一层的情况同样地，使用封装头122，以使第二层的半导体芯片10的凸块18与第一层的半导体芯片10的电极端子16相向的方式，将第二层的半导体芯片10配置于第一层的半导体芯片10之上。而且，在所述状态下，以第一温度T1对第二层的半导体芯片10进行加热，且以第一负载F1进行加压，将所述第二层的半导体芯片10临时压接于第一层的半导体芯片10。
以后，同样地，逐步将第三层的半导体芯片10临时压接于第二层的半导体芯片10之上，将第四层的半导体芯片10临时压接于第三层的半导体芯片10之上。图5(c)表示在区域A中，一面对四层的半导体芯片10进行临时压接，一面进行层叠的情形。层叠有所述四个半导体芯片10的层叠体成为临时压接状态的芯片层叠体ST。
在区域A中形成了临时压接状态的芯片层叠体ST之后，以同样的顺序，也在其他配置区域34形成临时压接状态的芯片层叠体ST。但是，由于将临时压接状态的芯片层叠体ST的间隔设为间隔距离Dd以上，因此在所述阶段，将临时压接状态的芯片层叠体ST形成于区域C而不形成于区域B。图6(c)表示在2个以上的配置区域34(区域A、区域C)形成有临时压接状态的芯片层叠体ST的情形。在所述阶段，第一次压接步骤结束。
压接步骤结束之后，接着，对所形成的临时压接状态的芯片层叠体ST依序进行正式压接。具体而言，如图6(b)所示，首先，将封装头122加热至正式压接用的温度即第二温度T2。而且，如图6(b)所示，使用已加热至第二温度T2的封装头122，以第二负载F2对临时压接状态的芯片层叠体ST加压，且一并对四个半导体芯片10进行正式压接。再者，第二负载F2只要能适当确保凸块18的推压量，则并无特别限定。
因受到已加热至第二温度T2的封装头122按压，构成芯片层叠体ST的四个半导体芯片10也被加热。但是，加热温度会随着远离封装头122而逐步下降。具体而言，最上层(第四层)的半导体芯片10被加热至与第二温度T2几乎相同的温度，但最下层(第一层)的半导体芯片10是以自第二温度T2仅下降了ΔT的下层温度Ta＝T2-ΔT被加热。以使所述下层温度Ta成为较熔融温度Tm及硬化开始温度Tt大的目标温度的方式来设定第二温度T2。即，在正式压接时，构成芯片层叠体ST的四个半导体芯片10均被加热至较熔融温度Tm及硬化开始温度Tt高的温度。
各半导体芯片10超过硬化开始温度Tt地被加热，由此半导体芯片10的NCF 20渐渐硬化。而且，通过NCF 20硬化，而半导体芯片10与被压接体(基板30或下侧的半导体芯片10)机械性牢固地被固着。另外，通过超过熔融温度Tm地被加热，而凸块18熔融，且可密接于相对向的电极端子32、电极端子16。而且，由此，四个半导体芯片10及基板30成为彼此电性接合的封装状态。而且，一并对构成所述芯片层叠体ST的四个半导体芯片10进行正式压接的步骤成为正式压接步骤。
再者，传递至下层的热经由热传导率高的基板30(半导体晶片)也传递至其周边。周边的其他芯片层叠体ST有时因经由所述基板30所传递的热而受到不良影响。为了避免此种由热引起的不良影响，本实施方式中，使临时压接状态的芯片层叠体ST隔开间隔距离Dd以上，所述情况在后文中详细说明。
对一个芯片层叠体ST完成了正式压接之后，接着，也对其他芯片层叠体ST进行正式压接。即，在区域C等全部两个以上的配置区域34依序执行正式压接。而且，对所形成的全部临时压接状态的芯片层叠体ST进行正式压接之后，接着执行第二次临时压接步骤。即，在第一次临时压接步骤中未形成芯片层叠体ST的配置区域、图6的例子中区域B等形成临时压接状态的芯片层叠体ST。图6(c)是表示第二次临时压接步骤的情形的图。与第一次临时压接步骤同样地，在两个以上的配置区域形成了临时压接状态的芯片层叠体ST之后，其次实施依序对这些芯片层叠体ST进行正式压接的第二次正式压接步骤。以后，在所需的全部配置区域中重复进行临时压接步骤与正式压接步骤，直至可将芯片层叠体ST封装，从而封装处理结束。
如由以上说明可知，本实施方式中，为在两个以上的配置区域34连续进行临时压接之后连续进行正式压接的并行方式。因此，与对各配置区域34重复执行临时压接与正式压接的串行方式相比，可减少封装头122的温度的切换次数。因此，可减少用于升温或降温的待机时间，从而可大幅减少封装处理整体的时间。
而且，如根据说明可知，本实施方式中，使临时压接状态的芯片层叠体ST彼此隔开规定的间隔距离Dd以上而形成。参照图7来说明设为所述构成的理由。图7中，上半部分是表示半导体芯片10的封装过程的概念图，下半部分是表示基板30的表面温度的图表。
如图7所示，另外，如已说明那样，当一面通过以第二温度T2被加热的封装头122对层叠于区域A的芯片层叠体ST的上表面加热一面加压时，下层的半导体芯片10被加热至相较于NCF 20的硬化开始温度Tt、凸块18的熔融温度Tm而充分高的温度Ta。此时，与下层的半导体芯片10邻接的区域A中的基板30的温度也高于硬化开始温度Tt及熔融温度Tm。另外，作为半导体晶片的基板30由于热传导率比较高，因此自下层的半导体芯片10受到的热进而传递至其周边。结果，不仅在区域A，而且在邻接的区域B，表面温度也有时超过硬化开时温度Tt及熔融温度Tm。
在所述情况下，若在区域B存在临时压接状态的芯片层叠体ST，则所述芯片层叠体ST的NCF 20在正式压接前开始硬化，或者凸块18开始熔融。若在正式压接之前发生NCF 20的硬化或者凸块18的熔融，则会导致半导体芯片10与基板的接合不良。另外，即使为不会发生NCF 20的硬化或者凸块18的熔融的情况，也有长时间暴露于高温下，从而发生不期望的热变化之虞。
因此，本实施方式中，预先确定自正式压接中的芯片层叠体ST起至通过用于所述正式压接的热而升温的基板30的温度成为规定的容许温度Td以下的部位为止的距离即间隔距离Dd。而且，以全部临时压接状态的芯片层叠体ST彼此隔开间隔距离Dd以上的方式来决定芯片层叠体ST的形成部位。
容许温度Td只要为NCF 20不可逆地开始硬化的硬化开始温度Tt以下且凸块18开始熔融的熔融温度Tm以下，则并无特别限定。间隔距离Dd为自正式压接中的芯片层叠体ST起至表面温度成为容许温度Td的部位为止的距离，但所述间隔距离Dd的确定方式也无特别限定。例如，也可向用户提醒输入间隔距离Dd而将由用户输入的值确定为间隔距离Dd。所述情况下，用户预先通过实验或模拟等求出间隔距离Dd。
另外，作为另一方式，也可由封装装置100的控制部基于封装条件来确定间隔距离Dd。例如，控制部也可基于经正式压接的芯片层叠体ST的下层的半导体芯片10的温度即下层温度Ta来确定间隔距离Dd。此处，下层温度Ta为未通过传感器等检测的未知的值。但是，正式压接时的封装头122的温度即第二温度T2被设定为如使下层温度Ta成为熔融温度Tm及硬化开始温度Tt以上即目标温度那样的温度。所述目标温度预先为已知，因此可将所述目标温度视为下层温度Ta。
控制部预先存储表示下层温度Ta与间隔距离Dd的关联的间隔距离分布图。图8是表示间隔距离分布图的一例的图。若下层温度Ta为容许温度Td以下，则间隔距离Dd为0，但随着下层温度Ta超过容许温度Td地上升，间隔距离Dd也逐步上升。控制部使正式压接时的实际所使用的第二温度T2对照所述间隔距离分布图来确定间隔距离Dd。
另外，间隔距离Dd也因基板30的导热特性而不同。认为即使下层温度Ta相同，基板30的导热特性越高，则间隔距离Dd也越长。因此，根据基板30的导热特性，也可预先准备多种间隔距离分布图。图8中，实线表示导热特性低的情况下的间隔距离Dd，一点划线表示导热特性高的情况下的间隔距离Dd，虚线表示导热特性为中等程度的情况下的间隔距离Dd。
基板30的导热特性因基板30的形状(厚度)、或材质等特征的差异而不同。因此，控制部也可预先存储表示基板30的特征与导热特性的关联的导热特性数据，并基于所述导热特性数据来确定基板30的导热特性。图9是表示导热特性数据的一例的图。控制部使实际所使用的基板30的厚度及材质对照导热特性数据来确定所述基板30的导热特性。
另外，间隔距离Dd进而也因正式压接的持续时间、或周边的环境温度而不同。因而，当确定间隔距离Dd时，除所述下层温度Ta及导热特性以外，进而也可考虑正式压接的持续时间、环境温度等。例如也可为，即使下层温度Ta及导热特性相同，正式压接的持续时间越长，另外环境温度越高，则间隔距离Dd也越长。
进而，至此为止所说明的间隔距离Dd的确定方法为一例，也可适宜变更。例如，所述形态中，将预先设定的目标温度作为下层温度Ta来处理。但是，也可基于正式压接时的封装头122的温度即第二温度T2及芯片层叠体ST的芯片层叠数或高度来推断下层温度Ta。
其次，对临时压接状态的芯片层叠体ST的形成位置的确定方法进行说明。如反复所说明那样，本实施方式中，使临时压接状态的芯片层叠体ST彼此隔开间隔距离Dd以上。为了满足所述条件，本实施方式中，以数个为单位空开配置区域34来配置临时压接状态的芯片层叠体ST。具体而言，在将配置区域34的配置间距设为P的情况下，控制部确定满足{(N-l)×P}≦Dd<N×P的整数N。而且，在临时压接步骤中，每隔N个配置区域来形成临时压接状态的芯片层叠体ST。
参照图10来说明所述情况。图10表示将多个芯片层叠体ST形成于设定有4×4＝16个配置区域34的基板30的情形。图10中，空白的矩形表示临时压接状态的芯片层叠体ST，施以影线的矩形表示正式压接后的芯片层叠体ST。另外，为了便于说明，将多个配置区域34自左下起依次称为区域A、区域B、···、区域P。
所述例子中，配置区域34的配置间距为P，间隔距离Dd设为0.3×P。所述情况下，Dd＝0.3×P大于0且小于P，因此满足{(N-l)×P}≦Dd<N×P的整数N为“1”。因而，所述情况下，临时压接状态的芯片层叠体ST每隔一个配置区域而配置于配置区域。
即，如图10的左上所示，在第一次临时压接步骤中，在将临时压接状态的芯片层叠体ST形成于区域A的情况下，也将临时压接状态的芯片层叠体ST形成于自所述区域A观察而在纵向及横向上跳过一个配置区域34所得的区域C、区域I以及与区域C、区域I相距一个配置区域34的区域K。而且，在区域A、区域C、区域K、区域I形成了临时压接状态的芯片层叠体ST之后，接着，依序对所述四个芯片层叠体ST进行正式压接。即使进行了正式压接，因在基板30成为高温的区域(不足间隔距离Dd的区域)不存在其他临时压接状态的芯片层叠体ST，因此也可防止违背意愿的NCF 20的硬化或者凸块18的熔融等不期望的热变化。
在第二次临时压接步骤中，将临时压接状态的芯片层叠体ST形成于空开的配置区域34。例如，在第一次临时压接步骤中，在将临时压接状态的芯片层叠体ST形成于区域B的情况下，也将临时压接状态的芯片层叠体ST形成于自所述区域B观察而在纵向及横向上跳过一个配置区域34所得的区域D、区域J以及与区域D、区域J相距一个配置区域34的区域L。而且，在区域B、区域D、区域L、区域J形成了临时压接状态的芯片层叠体ST之后，接着，依序对所述四个芯片层叠体ST进行正式压接。即，执行第二次正式压接步骤。此时，在经正式压接的芯片层叠体ST、例如区域B的芯片层叠体ST的附近即区域A、区域C存在其他芯片层叠体ST。但是，所述区域A、区域C的芯片层叠体ST已被正式压接，因此即使高温传递至区域A、区域C的芯片层叠体ST，也不会出现问题。即，所述情况下，也可防止违背意愿的NCF 20的硬化或者凸块18的熔融等不期望的热变化。第二次压接步骤结束后，之后也同样地，重复进行临时压接步骤与正式压接步骤，在空开的区域以跳过一个区域的间隔形成芯片层叠体ST。
如所述那样，本实施方式中，确定满足{(N-l)×P}≦Dd<N×P的整数N，并基于所述整数N来确定临时压接状态的芯片层叠体ST的形成位置。再者，此种形成位置的确定也可在执行临时压接步骤的时候随时进行。另外，作为另一方式，也可在第一次临时压接步骤之前确定临时压接状态的芯片层叠体ST的形成位置。即，也可在第一次临时压接步骤之前，基于间隔距离Dd来预先形成表示各临时压接步骤的芯片层叠体ST的形成位置的分布图，且在实际的临时压接步骤中，按照所述分布图来形成临时压接状态的芯片层叠体ST。
而且，在至此为止的说明中，说明了利用一个封装头122来执行临时压接及正式压接所述两者的例子。但是，封装头122不必为一个，也可设置临时压接用的封装头、与正式压接用的封装头所述两者。所述情况下，只要预先总是将临时压接专用的封装头加热至第一温度T1，且总是将正式压接专用的封装头加热至第二温度T2即可。通过设为所述构成，无需对封装头的温度进行切换，因此可消除封装头升降温所需的时间，从而可进一步缩短封装时间。
另外，此时，正式压接用的封装头也可设为能够同时对两个以上的芯片层叠体ST进行加热·加压(正式压接)的尺寸。例如，如图11的上半部分所示，也可将正式压接用的封装头122a设为能够同时对四个芯片层叠体ST进行正式压接的尺寸。所述情况下，同时经正式压接的芯片层叠体ST不必仅隔开间隔距离Dd，只要未同时经正式压接的临时压接状态的芯片层叠体ST隔开间隔距离Dd以上即可。
例如，图11的例子中，在第一次临时压接步骤中，只要将临时压接状态的芯片层叠体ST形成于区域A～区域D以及与所述区域A～区域D相距一列(间隔距离Dd以上)的区域L～区域I即可。而且，在第一次正式压接步骤中，对区域A～区域D的芯片层叠体ST同时进行正式压接之后，对区域L～区域I的芯片层叠体ST同时进行正式压接。而且，在第二次临时压接步骤中，将临时压接状态的芯片层叠体ST形成于区域E～区域H以及区域M～区域P。在第二次正式压接步骤中，对区域E～区域H的芯片层叠体ST同时进行正式压接，另外，对区域M～区域P的芯片层叠体ST同时进行正式压接。
如此，通过对两个以上的芯片层叠体ST同时进行正式压接，可减少各步骤的执行次数，从而可进一步缩短封装处理整体的时间。另外，所述情况下，也由于未同时经正式压接的临时压接状态的芯片层叠体隔开间隔距离Dd以上，因此可有效地防止违背意愿的NCF20的硬化或者凸块18的熔融。
另外，在至此为止的说明中，将各芯片层叠体ST设为四层进行了说明，但只要芯片层叠体ST的层叠数为1以上，则并无特别限定。另外，在至此为止的说明中，作为基板30，使用了半导体晶片，但也可使用其他基板。但是，本实施方式的技术尤其适合使用包含热传导性比较高的材料的基板的情况。
符号的说明
10：半导体芯片
14、16、32：电极端子
18：凸块
30：基板
34：配置区域
100：封装装置
102：芯片供给部
104：芯片搬送部
106：接合部
110：顶起部
114：裸片拾取器
116：移送头
118：旋转台
120：平台
122：封装头

Claims (10)

1.一种半导体装置的制造方法，其为将一个以上的半导体芯片层叠于基板上的多个部位并进行封装的半导体装置的制造方法，且所述半导体装置的制造方法的特征在于包括：
临时压接步骤，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体；以及
正式压接步骤，对所形成的全部所述临时压接状态的芯片层叠体的上表面依序加热加压，由此一并对构成各芯片层叠体的一个以上的半导体芯片进行正式压接，
将所述临时压接步骤及所述正式压接步骤重复进行两次以上，直至所述芯片层叠体达到所需的个数，进而，包括
确定步骤，即，在所述临时压接步骤之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离，
在所述临时压接步骤中，使所述临时压接状态的芯片层叠体彼此隔开所述间隔距离以上而形成，且
在所述正式压接步骤中，对隔开所述间隔距离以上而形成的所述临时压接状态的芯片层叠体进行正式压接。
2.一种封装方法，其为根据权利要求1所述的半导体装置的制造方法，且所述半导体装置的制造方法的特征在于：
所述确定步骤基于所述半导体芯片的封装条件来确定所述间隔距离。
3.一种半导体装置的制造方法，其为根据权利要求2所述的封装方法，且所述半导体装置的制造方法的特征在于：
包含进行所述正式压接时的所述芯片层叠体的最下层的温度即下层温度，且
所述确定步骤中，以所述下层温度越高则所述间隔距离越长的方式确定所述间隔距离。
4.根据权利要求1至3中任一项所述的半导体装置的制造方法，其特征在于：
在所述半导体芯片的层叠方向单侧端面设置有用于将所述半导体芯片与邻接封装于所述层叠方向单侧的基板或半导体芯片固着的热硬化性树脂，且
所述容许温度较所述热硬化性树脂不可逆地开始硬化的硬化开始温度低。
5.根据权利要求1至4中任一项所述的半导体装置的制造方法，其特征在于进而包括：
分布图形成步骤，基于所确定的所述间隔距离来形成表示多个芯片层叠体的形成位置的分布图，
在所述临时压接步骤中，按照所述分布图来形成所述多个所述临时压接状态的芯片层叠体。
6.根据权利要求1至3中任一项所述的半导体装置的制造方法，其特征在于，进而
配置有所述芯片层叠体的多个配置区域以规定的间距P呈格子状排列设定于所述基板，
所述确定步骤确定所述间隔距离之后，进而确定当将所述间隔距离设为Dd时满足{(N-l)×P}≦Dd<N×P的整数N，且
在所述临时压接步骤中，每隔N个所述配置区域来形成所述临时压接状态的芯片层叠体。
7.根据权利要求1所述的半导体装置的制造方法，其特征在于
所述基板为半导体晶片。
8.一种半导体装置的制造方法，其特征在于包括：
临时压接步骤，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体；以及
正式压接步骤，将对两个以上的临时压接状态的芯片层叠体的上表面同时加热加压且同时进行正式压接的处理重复进行两次以上，并使在所述临时压接步骤中形成的所有临时压接状态的芯片层叠体变化为正式压接状态，
将所述临时压接步骤及所述正式压接步骤重复进行两次以上，直至所述芯片层叠体达到所需的个数，进而，包括
确定步骤，即，在所述临时压接步骤之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离，且
在所述临时压接步骤中，使未同时经正式压接的临时压接状态的芯片层叠体彼此隔开所述间隔距离以上而形成。
9.一种封装装置，其为将一个以上的半导体芯片层叠于基板上的多个部位并进行封装的封装装置，且所述封装装置的特征在于包括：
临时压接机构，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体；
正式压接机构，对所形成的全部所述临时压接状态的芯片层叠体的上表面依序加热加压，由此一并对构成各芯片层叠体的一个以上的半导体芯片进行正式压接；以及
间隔距离确定机构，在所述临时压接之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离，且
所述临时压接机构使所述临时压接状态的芯片层叠体彼此隔开所确定的所述间隔距离以上而形成，
所述正式压接机构对隔开所述间隔距离以上而形成的所述临时压接状态的芯片层叠体进行正式压接。
10.一种封装装置，其为将一个以上的半导体芯片层叠于基板上的多个部位并进行封装的封装装置，且所述封装装置的特征在于包括：
接合部，一面将一个以上的半导体芯片依次分别临时压接于所述基板上的两个以上的部位，一面进行层叠，从而形成临时压接状态的芯片层叠体，并且对所形成的全部所述临时压接状态的芯片层叠体的上表面依序加热加压，由此一并对构成各芯片层叠体的一个以上的半导体芯片进行正式压接；
间隔距离确定机构，在所述临时压接之前，确定自正式压接中的芯片层叠体起至通过用于所述正式压接的加热而升温的所述基板的温度成为规定的容许温度以下的部位为止的距离即间隔距离；以及
控制部，将所述接合部控制成：使所述临时压接状态的芯片层叠体彼此隔开所述间隔距离以上而形成之后，对所形成的所述临时压接状态的芯片层叠体进行正式压接。
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Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021058A (ja) * 2011-07-08 2013-01-31 Elpida Memory Inc 半導体装置の製造方法
JP2014060241A (ja) * 2012-09-18 2014-04-03 Toray Ind Inc 半導体装置の製造方法
CN103718289A (zh) * 2011-07-27 2014-04-09 美光科技公司 半导体裸片组合件、包含所述半导体裸片组合件的半导体装置及制造方法
CN104520976A (zh) * 2012-08-08 2015-04-15 松下知识产权经营株式会社 安装方法
WO2016140124A1 (ja) * 2015-03-03 2016-09-09 東レエンジニアリング株式会社 実装装置および実装方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004006465A (ja) * 2002-05-31 2004-01-08 Renesas Technology Corp 半導体装置の製造方法
JP5732623B2 (ja) * 2011-10-03 2015-06-10 パナソニックＩｐマネジメント株式会社 半導体素子の実装方法
JP2015005637A (ja) * 2013-06-21 2015-01-08 ピーエスフォー ルクスコ エスエイアールエルＰＳ４ Ｌｕｘｃｏ Ｓ．ａ．ｒ．ｌ． 半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013021058A (ja) * 2011-07-08 2013-01-31 Elpida Memory Inc 半導体装置の製造方法
CN103718289A (zh) * 2011-07-27 2014-04-09 美光科技公司 半导体裸片组合件、包含所述半导体裸片组合件的半导体装置及制造方法
CN104520976A (zh) * 2012-08-08 2015-04-15 松下知识产权经营株式会社 安装方法
JP2014060241A (ja) * 2012-09-18 2014-04-03 Toray Ind Inc 半導体装置の製造方法
WO2016140124A1 (ja) * 2015-03-03 2016-09-09 東レエンジニアリング株式会社 実装装置および実装方法

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