TWI253153B - Method for producing flip chip package - Google Patents

Abstract

A method for producing a flip chip package is disclosed. First, a stencil having a plurality of central openings and a plurality of peripheral openings is placed on a substrate having a plurality of central contact pads and a plurality of peripheral contact pads around the central contact pads in a manner that the central openings of the stencil are aligned with the central contact pads of the substrate and the peripheral openings of the stencil are aligned with the peripheral contact pads of the substrate. A flux is applied to the substrate through the central openings and the peripheral openings of the stencil such that the flux on any peripheral contact pad has a volume more than the volume of the flux on any central contact pad but less than or equal to the double of the volume of the flux on any central contact pad. After the stencil is removed, a semiconductor chip having a plurality of bumps is placed on the substrate with the bumps thereof aligned with the central contact pads and the peripheral contact pads of the substrate. The bumps are reflowed so as to mechanically and electrically connect the semiconductor chip to the substrate.

Description

1253153 V. INSTRUCTION DESCRIPTION (i) Technical Field of the Invention The present invention relates to a method of manufacturing a flip chip package structure. [Prior Art] With the increasing demand for lighter and more complex electronic devices, the speed and complexity of wafers are relatively higher, so higher packaging efficiency is required. Minaturization It is the main driving force using advanced packaging technologies such as chip-scale package (chipsca 1 epackage) and flip chip (f1 ipchip). Compared to ball grid array packages or thin rim packages (thinsma 1 1 ou 11 inepackage, TS 0 P ), both wafer size packaging and flip chip technology greatly increase package efficiency, thereby reducing the need The substrate space. In general, a wafer size package is approximately twenty percent larger than the wafer itself, whereas flip chip is described as the ultimate package technology because it is about the same size as the wafer itself. The wafer itself is bonded directly to the substrate by using a solder bump mounted on the wafer. In general, 'cladding needs to apply flux (f 1 u X ) before the wafer is placed on the substrate, which has two major functions: (A) as a mechanism to hold the wafer in position before reflow; (B) as a wetting agent during reflow. Then, the flip chip is accurately placed on a predetermined position on the substrate by an automatically selected and placed machine, so that the tin-lead bumps on the wafer are precisely aligned with the corresponding pads on the substrate. Next, the product of the previous step is moved into a reflow oven, and a tin-lead connection (s ο 1 derj 〇int) is formed through the reflow process for electrically and mechanically connecting the wafer and the substrate. .

00709.ptd Page 7 1253153 V. INSTRUCTIONS (2) Generally, the flux suitable for the above-mentioned flip chip process is a low-residue no-clean flux (η 〇 - c 1 e a n t y p e f 1 u X ). "Low residue" means that the residue remaining on any surface of the flux after a subsequent reflow step is less than a certain value. In general, the no-clean flux contains a high proportion of volatile components (v〇1 a t i 1 e i n g r e d i e n t ) thereby reducing the residue after reflow. However, in the step of reflow soldering, the heat flow of the reflow furnace is poured into the gap between the wafer and the substrate from the edge of the wafer, so that the flux disposed at the edge of the wafer is more volatile than the flux disposed at the center of the wafer, resulting in The amount of flux on the edges is insufficient, and the solder connections at the edges often have incomplete "cold soldering". SUMMARY OF THE INVENTION Accordingly, it is a primary object of the present invention to provide a flip chip package construction method that overcomes or at least ameliorates the problems of the prior art. The method of manufacturing the flip chip package structure according to the present invention, which is mainly included, will be described below. First, a printing stencil having a plurality of central openings (c e n t r a 1 opening) and a plurality of peripheral openings is placed on a substrate. The substrate has a plurality of central contact pads and a plurality of peripheral interfaces (peripheral c n n t a c t p a d) disposed on the periphery of the central interface. The central opening of the printed screen is aligned with the central pad of the substrate and the peripheral opening of the printed screen is aligned with the peripheral pads of the substrate. Next, a flux is applied to the substrate via the central opening of the printed screen and the peripheral opening such that the amount of flux on any of the peripheral pads is greater than the amount of flux on any of the central pads, but less than or Equal to twice the flux on any central pad

00709.ptd Page 8 1253153 V. Description of invention (3) Quantity. In accordance with an embodiment of the present invention, the amount of flux on any of the peripheral pads of the substrate is greater than the amount of flux on any of the center pads but less than or equal to twice the amount of flux on any of the center pads. The amount of the peripheral opening radius of the printed screen can be controlled to be more than one times the radius of the central opening but equal to or less than V5 times the radius of the central opening; or the depth control of the peripheral opening of the printing screen It is more than double the depth of the central opening, but equal to or less than twice the depth of the central opening. The printed screen is then removed. Next, a semiconductor wafer having a plurality of bumps is placed on the substrate such that the bumps on the semiconductor wafer align the center pads of the substrate and the peripheral pads. The bump is reflowed to electrically and mechanically bond the semiconductor wafer to the substrate. The flip chip package structure manufacturing method provided by the present invention is such that the flux amount on any peripheral pads of the substrate is more than the amount of flux on any central pad but less than or equal to any central pad. The amount of flux twice. In this way, although the flux on the peripheral interface is more volatile than the flux on the central interface during the reflow step, since the peripheral pad is covered with more flux than the central pad, The peripheral pads still have enough flux to perform the reflow step to form a fully soldered connection. Therefore, the aforementioned cold welding problem can be overcome or at least improved by the method provided by the present invention. In addition, according to an embodiment of the present invention, a solder paste process similar to the foregoing may be used to form a solder paste on the central interface of the substrate and the peripheral pads by another printing screen before the step of applying the flux. ,

00709.ptd Page 9 1253153 V. INSTRUCTIONS (4) The amount of solder paste on any peripheral pads is less than or equal to the amount of solder paste. In general, since the half difference is quite large, stress is generated when the coefficient of swell is not matched, and the influence of the stress is the largest, so that the dressing is warped and deformed. According to the present invention, a large amount of solder paste is used, so that although the coating is more than the two-conductor wafer of the solder paste on any of the central pads on any of the central pads and the thermal expansion of the substrate is heated, Since the peripheral portion of the thermal expansion package structure is susceptible to being exposed in the peripheral portion by the crystal package structure, there is still a phenomenon that the peripheral pad has a warp age in the reflow step, for example, in the reflow process. A quantity of solder is used to connect the substrate and the semiconductor wafer, thereby ensuring connection reliability between the semiconductor wafer and the substrate. [Embodiment] Figs. 1 to 3 disclose the main steps of a method of manufacturing a flip chip package structure according to an embodiment of the present invention. First, referring to Fig. 1, a printing screen 1 〇 is placed on a substrate 1 1 。. The substrate 110 has a plurality of central contact pads 112 and a plurality of peripheral contacts p a d 1 1 4 disposed on the periphery of the central pads 1 1 2 . The printed screen 100 has a plurality of central openings (c e n t r a 1 〇 p e n i n g ) 102 and a plurality of peripheral openings 104. The printing screen 100 is aligned with the central opening 1 〇 2 of the central opening 1 1 2 of the substrate 1 1 0 and its peripheral opening 1 〇 4 is aligned with the peripheral pad 1 1 4 of the substrate 11 的The method is placed on the substrate 110. Next, a flux 120 is applied to the printing screen 110. The welding

00709.ptd Page 10 1253153 V. INSTRUCTION DESCRIPTION (5) The agent 1 2 0 can be applied to the substrate 1 1 0 via the central opening 1 0 2 of the printing screen 100 and the peripheral opening 1 0 4 . In this embodiment, since the peripheral opening 104 of the printing screen 100 is deeper than the depth of the central opening 10 2, but equal to or smaller than the depth of the central opening 10 2 Twice, such that the amount of flux on any of the peripheral pads 1 14 is greater than the amount of flux 1 2 0 on any of the center pads 11 2 , but less than or equal to any central pads 1 1 2 The amount of flux is twice that of 1 2 0. According to another embodiment of the present invention, as shown in FIG. 4, another printing screen 400 can be provided, and the radius of the peripheral opening 410 is controlled to be more than double the radius of the central opening 40 2, but Equal to or less than 々 times the radius of the central opening 4 0 2 . In this way, the use of the printing stencil 400 can also make the amount of flux on any of the peripheral pads 141 more than the amount of flux 1 2 2 on any of the central pads 1 1 2, but less It is equal to or equal to twice the amount of flux 1 2 0 on any central pad 1 1 2 . Then, referring to Fig. 2, the printing screen 100 is removed. Next, a semiconductor wafer 130 with a plurality of bumps 1 3 2 is placed on the substrate 110, such that the bumps 1 3 2 on the semiconductor wafer 130 are aligned with the center of the substrate 110. Pad 1 1 2 and peripheral pad 1 1 4 . Next, referring to Fig. 3, the bumps 1 3 2 are reflowed by heating, whereby the semiconductor wafer 130 is electrically and mechanically connected to the substrate 110. The flip chip package structure manufacturing method provided by the present invention is such that the flux amount on any peripheral pads of the substrate is more than the amount of flux on any central pad, but less than or equal to any central pad. Double the amount of flux. As a result, although on the peripheral pad during the reflow step

00709.ptd Page 11 1253153 V. INSTRUCTIONS (6) The flux is more volatile than the flux on the central pad, however, since the peripheral pad is covered with more flux than the central pad, the peripheral pad There is still enough flux to perform the reflow step to form a fully soldered connection. Therefore, the aforementioned chilling problem can be overcome or at least improved by the method provided by the present invention. Further, Figures 5-7 disclose the main steps of a method of fabricating a flip chip package structure in accordance with another embodiment of the present invention. Referring to FIG. 5, before the step of applying the flux, a screen printing process can be used to connect the center of the substrate 110 using another printing screen (whose structure such as a printing screen 100 or 400). A solder paste (s〇1 derpaste) 5 0 2 is formed on the pad 1 1 2 and the peripheral pads 1 1 4 . The screen printing process includes placing the printing screen on the substrate 110 such that the central opening of the printing screen is aligned with the central pad of the substrate and the peripheral opening of the printing screen is aligned with the substrate Peripheral pads. Next, a solder paste 500 is applied to the substrate 110 via the central opening of the printed screen and a peripheral opening such that the amount of solder paste on any of the peripheral pads 1 1 4 is more than in any central portion. The amount of solder paste 50 2 on pad 1 1 2 is less than or equal to twice the amount of solder paste on any of the center pads 112. In general, since the difference in thermal expansion coefficient between the semiconductor wafer and the substrate is relatively large, when the flip chip package structure is heated, stress is generated due to a thermal expansion coefficient mismatch, and the peripheral portion of the flip chip package structure is most affected by the stress, so that The flip chip package structure is prone to bending deformation at the peripheral portion. According to the present invention, since the peripheral pad 1 1 4 of the substrate 110 has more solder paste 520 than the center pad 112, the flip chip package structure is deformed and bent in, for example, the reflow step. (warpage) phenomenon, still

00709.ptd Page 12 1253153 V. Description of the Invention (7) A sufficient amount of solder is used to connect the substrate 110 and the semiconductor wafer, thereby ensuring the connection between the semiconductor wafer 130 and the substrate 110 reliability. Generally, the difference between the thermal expansion coefficients of the wafer 130 and the substrate 110 is quite large (the coefficient of thermal expansion (CTE) of the semiconductor wafer is about 2-5 ppm t: -1, and the thermal expansion coefficient (CTE) of the substrate. Preferably, the wafer 130 and the substrate 1 10 have an adhesive (underfi 1 1 ) 140 for sealing the gap between the wafer 130 and the substrate 110 (eg, the third). Figure and Figure 7). The filler 1 40 can reduce the stress caused by the inconsistent coefficient of thermal expansion between the wafer 130 and the substrate 110. In general, the fill 110 utilizes an automated underfill dispense system to spot the fill material at the edge of the wafer 130. The glue material is then sucked under the wafer 130 by capillary action to complete the filling process. The product of the previous step is then transferred to an underfill curing oven and the fill 110 is then cured. In addition, the amount of flux on the peripheral pads 1 14 should not be excessive. The amount of flux on the outer pad 1 14 is preferably no more than twice the amount of flux on the center pad 112. As described above, the flux suitable for the above-described flip chip process is a low-residue no-clean flux (η 〇 - c 1 e a n t y p e f 1 u X ). "Low residue" means that the residue remaining on any surface of the flux after a subsequent reflow step is less than a certain value. In general, the no-clean flux contains a high proportion of volatile components (v ο 1 a t i 1 e i n g r e d i e n t ) thereby reducing residue after reflow. However, this volatile

00709.ptd Page 13 1253153 V. INSTRUCTIONS (8) The composition easily interacts with the rubber material at high temperatures to generate gas. Therefore, in the process of curing the filler 140, if there is too much flux, there is still residual flux after the reflow, and the residual flux is heated together to about 200 ° C, so the residual flux The volatile component contained therein reacts with the filler material to generate a gas to generate a void (vo id ) in the filler 140. These voids will result in reduced reliability of the mechanical and electrical connection between the wafer 130 and the base 110 (i.e., tin-lead connection 4 04 ). While the present invention has been described in its preferred embodiments, it is not intended to limit the scope of the invention, and various modifications and changes can be made without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention is defined by the scope of the appended claims.

00709.ptd Page 14 1253 153 Brief Description of the Drawings [Simplified Description of the Drawings] In order to make the above and other objects, features and advantages of the present invention more obvious, the preferred embodiments of the invention The illustration is described in detail below. 1 to 3: a main section of a method of manufacturing a flip chip package structure according to an embodiment of the present invention is shown in a sectional view; FIG. 4 is a view showing a printing stencil for forming the flux according to an embodiment of the present invention. Top View, and Figures 5-7: The main steps of a method of fabricating a flip chip package construction in accordance with another embodiment of the present invention are illustrated in cross-section. Description of the drawing: 100 Printing stencil 102 Central opening V 104 Peripheral opening 110 Substrate 112 Central interface 114 Peripheral pad 120 Flux 130 Semiconductor wafer 132 Bump 140 Filling 400 Printing stencil 402 Central opening α 404 Peripheral opening α 502 Solder paste

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Claims (1)

1253153 VI. Patent Application No. 1, a method for manufacturing a flip chip package 4, comprising the following steps; providing a substrate 1 having a plurality of central pads (ce η tra 1 con tact pa d) and a plurality of A peripheral pad (per i ph era 1 C 0 ntact pad) δ further provides a semiconductor wafer on the periphery of the central pad having a plurality of bumps formed thereon 9 having a plurality of first - central opening a (C en Tra 1 〇pe ni ng) and a plurality of first printing stencils of 第 eri ph era 1 〇P e η in g are placed on the substrate such that the first central portion of the first printing stencil Opening σ is aligned with the central pad of the substrate and the first stencil of the first printed stencil is aligned with the peripheral pad of the substrate. The flux passes through the first central opening of the first printed stencil And the first - periphery The opening α is applied to the substrate such that the amount of flux on any of the peripheral pads is greater than the amount of flux on any of the center pads, but less than or equal to twice the amount of flux on any of the center pads. Removing the first printing screen 9 after the first printing screen is removed, placing the semiconductor wafer on the substrate such that the bumps on the semiconductor wafer are aligned with the central pads of the substrate and the peripheral pads And re-welding the bump y to electrically and mechanically connect the semiconductor wafer to the substrate 〇2, and the method 1 for fabricating a flip chip package structure according to the first aspect of the invention, wherein the first periphery opens a radius Is R and the first - central opening 00709.ptd Page 16 1253153 VI. Scope of Application The radius is Γ, and r < r . 3. The method of manufacturing a flip chip package structure according to claim 1, wherein the first peripheral opening has a depth D and the first central opening has a depth d, and d <D^2 d. 4. The method of manufacturing a flip chip package structure according to claim 1, further comprising forming a solder paste on each of the central and peripheral pads before the step of applying the flux. a step wherein the amount of solder paste on any of the peripheral pads is greater than the amount of solder paste on any of the center pads, but less than or equal to twice the amount of solder paste on any of the center pads. 5, as claimed in the patent application The method for manufacturing a flip chip package structure according to Item 4, wherein the solder paste forming step is achieved by a screen printing process using a second printing screen The second printing screen has a central pad having a plurality of second central openings corresponding to the substrate and a plurality of second peripheral openings corresponding to the peripheral pads of the substrate. 6. The method of fabricating a flip chip package structure according to claim 5, wherein the second peripheral opening radius is r2 and the second central opening radius is 1"2, and r2 < R2^V5 F2. 00709.ptd Page 17 1253153 00709.ptd第18页