TW445618B - Manufacturing method of flip-chip package - Google Patents
Manufacturing method of flip-chip package Download PDFInfo
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- TW445618B TW445618B TW089103105A TW89103105A TW445618B TW 445618 B TW445618 B TW 445618B TW 089103105 A TW089103105 A TW 089103105A TW 89103105 A TW89103105 A TW 89103105A TW 445618 B TW445618 B TW 445618B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Wire Bonding (AREA)
Abstract
Description
:，4 456 1 8_________ 五、發明說明（1) 發明領域： 本發明係有關於一種半導體晶片封裝構造之製造方 法，特別有關於—種覆晶封裝構造（flip-chip package) 之製造方法。 先前技術： 隨著更輕更複雜電子裝置需求的曰趨強烈，晶片的速 度及複雜性相對越來越高’因此需要更高之封裝效率 (packaging efficiency)。微型化（miniaturization)是 使用先進封裝技術（例如晶片尺寸級封裝（c h i p s c a 1 e package)以及覆晶（flip chip))的主要驅動力。相較於 球格陣列封裝或薄小輪廓封裝（thin smaii outiine package, TS0P)而言，晶片尺寸級封裝以及覆晶這兩種技 術均大幅增加封裝效率，藉此減少所需之基板空間。一般 而言，一個晶片尺寸級封裝大約比晶片本身大百分之二 十，然而覆晶被描述為終極之封裝技術因為其大約與晶片 本身一樣大。該晶片本身係直接利用固設於晶片上之錫鉛 凸塊（solder bump)與基板（substrate)進行接合。 第一圖揭示一覆晶技術之流程圖。第一圖揭示一晶片 10利用第一圖之覆晶技術安裝於一基板20。 在步驟110，該基板預烘烤製程係用以去除基板2〇多餘 之水分。不像其他的表面接著裝置，覆晶需要在安放前施 加助銲劑（flux)，其具有兩大功能：（A)做為在回銲前將 晶片保持在位置上之機制；以及（β )做為回銲時之潤濕劑 (wetting agent)。在步驟120，助銲剤的施加一般係利用:, 4 456 1 8_________ 5. Description of the invention (1) Field of the invention: The present invention relates to a method for manufacturing a semiconductor wafer package structure, and more particularly to a method for manufacturing a flip-chip package. Prior technology: With the increasing demand for lighter and more complex electronic devices, the speed and complexity of the chip are relatively higher and higher, therefore higher packaging efficiency is required. Miniaturization is the main driving force behind the use of advanced packaging technologies, such as chip scale packaging (c h i p s c a 1 e package) and flip chip. Compared with the ball grid array package or thin smaii outiine package (TS0P), the two technologies of wafer-scale package and flip chip greatly increase the packaging efficiency, thereby reducing the required substrate space. In general, a wafer-scale package is approximately 20% larger than the wafer itself, but flip chip is described as the ultimate packaging technology because it is approximately as large as the wafer itself. The wafer itself is directly bonded to the substrate using a tin-lead bump fixed on the wafer. The first figure shows a flowchart of a flip chip technology. The first figure discloses that a wafer 10 is mounted on a substrate 20 using the flip-chip technology of the first figure. In step 110, the substrate pre-baking process is used to remove excess moisture from the substrate. Unlike other surface bonding devices, flip-chips need to apply flux before placement, which has two major functions: (A) as a mechanism to hold the wafer in position before reflow; and (β) do It is a wetting agent during reflow. In step 120, the application of the soldering flux is generally performed by using
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4456 1 S 五、發明說明（2) 配送（dispensing)法達成，其係利用—配送閥 (dispenser)施加定量之助銲劑到基板2〇上之預先設定位 置。在步驟130 ’ 一自動化選取及安放的機器將覆晶晶片 10精確置放在基板上之預先設定位置，使得晶片上之錫鉛 凸塊精確地對齊基板20上相對應的焊墊22 «在步驟140， 該步驟130之產物被移至一回焊爐（refi〇w 〇ven)内，並且 經由該回烊製程形成踢船連接（solder joint)12。由於該 晶片10與基板20熱膨服係數差異相當大（半導體晶片之熱 膨脹係數（coefficient of thermal expansion, CTE)約 為3-5ppra°C-l ’基板之熱膨脹係數（CTE)約為20-30ppm°C -1 )，因此該晶片1 0與基板1 2間較佳具有一填膠 (u n d e r f i 1 1 ) 3 0用以密封該錫鉛連接1 2間之空隙》該填膠 30可以減輕在錫錯連接12上的熱膨脹係數不一致所導致的 應力。在步驟1 50，填膠30係利用一自動化點膠系統 (automated underfill dispense system)將填膠材料點 在該晶片丨0之邊緣。然後該填膝材料經由毛細作用吸到晶 片10之下而完成填膠製程。在步驟160，該步驟150之產物 被移至一填膠固化爐（underfill curing oven)内，然後 固化該填膠30。 一般而言，適合於前述覆晶製程之助銲劑為低殘留物 之免清洗式助銲劑（no-clean type flux)。 「低殘留物」 係指助銲劑在經過後續的回銲步驟後，其殘存在任何表面 之殘餘物係小於一定之數值° 一般而言，該免清洗式助銲 劑係含有高比例之易揮發性成分（volatile ingredient)4456 1 S V. Description of the Invention (2) The distribution method is achieved by applying a quantitative amount of flux to a preset position on the substrate 20 using a dispenser. At step 130 ', an automated selection and placement machine accurately positions the flip-chip wafer 10 at a predetermined position on the substrate, so that the tin-lead bumps on the wafer are precisely aligned with the corresponding pads 22 on the substrate 20 «In step 140. The product of step 130 is moved to a refiow furnace and a solder joint 12 is formed through the reflow process. Because the thermal expansion coefficient of the wafer 10 is significantly different from that of the substrate 20 (the coefficient of thermal expansion (CTE) of the semiconductor wafer is about 3-5 ppra ° Cl ', the coefficient of thermal expansion (CTE) of the substrate is about 20-30 ppm ° C -1), so the chip 10 and the substrate 12 preferably have an underfill 1 (underfi 1 1) 3 0 to seal the gap between the tin-lead connection 12 and the filling 30 can reduce the wrong connection in the tin Stress caused by inconsistent thermal expansion coefficients at 12. In step 1 50, the glue filling 30 uses an automated underfill dispense system to place the glue filling material on the edge of the wafer. The knee filler is then sucked under the wafer 10 by capillary action to complete the glue filling process. In step 160, the product of step 150 is moved into an underfill curing oven, and then the underfill 30 is cured. Generally speaking, the flux suitable for the aforementioned flip-chip process is a low-residue no-clean type flux. "Low residue" means that the flux residue on any surface after the subsequent reflow step is less than a certain value. Generally speaking, the no-clean flux contains a high proportion of volatile Ingredients (volatile ingredient)
4456 1 8 五、發明說明（3) ------- 藉此減少㈣後之殘餘物。#而該易揮發性成分容易在高 溫^與填膠材料產生交互作用而產生氣體。因此在前述之 覆晶接合製程中’由於在步驟160固化該填膠30的過程 中’該回焊後殘餘之助銲劑係一起被加熱至約200 1，因 此該殘餘助銲劑所含之易揮發性成分會與填膠材料反應而 產生氣體而在填膠30中產生孔隙（v〇id)32。而這些孔隙32 將會導致晶片1 〇及基板2 〇之間的機械以及電性連接（即錫 錯連接1 2 )的可靠性降低。 此外，該基板2 0經步驟1 1 〇預烘烤後仍會漸漸吸收水 氣，因此需要小心控制後續處理步驟（即步驟1 2 0至1 5 0 ) 之時間’以減少水氣之再吸收。否則，在步驟1 6 0中，該 基板20再吸收之水氣也會由該基板20揮發而在填膠30中產 生孔隙。 發明概要： 本發明之主要目的係提供一種覆晶封裝構造之製造方 法，其可解決前述先前技術的孔隙（v 〇 i d)問題。 根據本發明之覆晶封裝構造製造方法，其包含下列步 驟：（A)施加助辟劍’其可利用配送（dispensing)法達 成，或浸潰法（dip fluxing)達成；（B) 將一晶片置放在 基板上之預先設定位置，使得該晶片之複數個錫鉛凸塊 (solder bump)對齊該基板上相對應的焊墊；（C)回焊該 錫鉛凸塊，藉此將該晶片固定於基板並且電性連接該晶片 至基板；（D)烘烤該基板以及回焊後殘餘之助銲劑，藉此 去除該基板多餘之水分以及大致除去助銲劑含有之易揮發4456 1 8 V. Description of the invention (3) ------- By this way, the remaining residues are reduced. #And the volatile component is likely to interact with the filling material at high temperature ^ to generate gas. Therefore, in the aforementioned flip-chip bonding process, 'the residual flux after reflow is heated to about 200 1 together during the process of curing the filler 30 in step 160, so the residual flux contained in the flux is volatile. The sexual component reacts with the filler material to generate a gas and generates voids 32 in the filler 30. And these pores 32 will cause the reliability of the mechanical and electrical connection (that is, the tin connection 12) between the wafer 10 and the substrate 20 to decrease. In addition, the substrate 20 will gradually absorb water vapor after pre-baking in step 110, so it is necessary to carefully control the time of subsequent processing steps (ie steps 120 to 150) to reduce the reabsorption of water vapor. . Otherwise, in step 160, the water vapor reabsorbed by the substrate 20 will also be volatilized from the substrate 20 and voids will be generated in the filler 30. SUMMARY OF THE INVENTION: The main object of the present invention is to provide a manufacturing method of a flip-chip package structure, which can solve the aforesaid prior art void (v o i d) problem. The method for manufacturing a flip-chip package structure according to the present invention includes the following steps: (A) applying a helper blade, which can be achieved by using a dispensing method, or by dip fluxing; (B) applying a wafer Placed in a predetermined position on the substrate so that the solder bumps of the wafer are aligned with the corresponding solder pads on the substrate; (C) resoldering the solder bumps to the wafer Fixed on the substrate and electrically connecting the wafer to the substrate; (D) baking the substrate and the residual flux after reflow, thereby removing excess moisture from the substrate and roughly removing the volatile content of the flux
4456 1 8 五、發明說明（4) 性成分；（E)形成一填膠於I片輿墓板間；（F)固化該填 膠。 根據本發明之覆晶封裝構造製造方法，由於該基板多 餘之水分以及殘餘助銲劑所含之易揮發性成分係在填膠前 一步驟利用烘烤的方式除去，藉此大幅減少由基板蒸發之 水氣以及殘餘助銲劑所含之易揮發性成分。因此大幅降低 填膠固化後發生孔隙之機率。 圖示說明： 為了讓本發明之上述和其他目的、特徵、和優點能更 明顯，下文特舉本發明較佳實施例，並配合所附圖示，作 詳細說明如下。 第1圖：習用覆晶技術之流程圖； 第2圖：利用第一圖之覆晶技術製造而得之覆晶封裝 構造之剖面圖； 第3圖：根據本發明一較佳實施例之覆晶封裝構造製 造方法之流程圖；及 第4圖：利用根據本發明第3圖之覆晶技術製造而得 之覆晶封裝構造之剖面圖。 圖號說明： 10 晶片 12 錫鉛連接 20 基板 22 焊墊 30 填膠 32 孔隙 110 預烘烤基板 120 施加助銲劑 130 裝上覆晶晶片 140 回銲 150 填膠 160 固 匕4456 1 8 V. Description of the invention (4) Sexual ingredients; (E) Forming a glue filling between the I grave boards; (F) Curing the glue filling. According to the manufacturing method of the flip-chip package structure of the present invention, since the excess moisture of the substrate and the volatile components contained in the residual flux are removed by baking in a step before filling, thereby greatly reducing the evaporation of Moisture and volatile components in residual flux. Therefore, the probability of voids occurring after the filler is cured is greatly reduced. Illustrative illustration: In order to make the above and other objects, features, and advantages of the present invention more apparent, the following describes the preferred embodiments of the present invention in detail with the accompanying drawings. Figure 1: Flow chart of conventional flip-chip technology; Figure 2: Cross-sectional view of a flip-chip package structure manufactured using the flip-chip technology of the first figure; Figure 3: A flip-chip according to a preferred embodiment of the present invention A flowchart of a method for manufacturing a chip package structure; and FIG. 4: a cross-sectional view of a chip package structure manufactured by using the chip-on-chip technology according to FIG. 3 of the present invention. Description of drawing number: 10 chip 12 tin-lead connection 20 substrate 22 solder pad 30 filling 32 hole 110 pre-baking substrate 120 applying flux 130 mounting chip on chip 140 re-soldering 150 filling 160 adhesive
4 456 1 8 五、發明說明 (5) 210 提供 墓板 220 230 裝 上 覆 晶晶 片 240 250 烘 烤 260 270 固 化 發明 說明： 第三 圖 揭 示一 根據 本發明 回銲 -較佳實施例之覆晶封裝構 造製造方法之流程圖。第四圖揭示一晶片10利用第三圖之 覆晶技術安裝於一基板20。 在步驟210 ’該基板2〇可以利用任一種增層法 (build-up)製程技術形成。此外，該基板20亦可以是一 多層陶究基板（multi-layer ceramic substrate)。該基 板20具有複數個燁整（contact pad)22設於該基板20上之 預先設定位置。 在步驟2 2 0 ’助銲劑的施加一般係利用配送 (dispensing)法達成，其係在基板20送入晶片安放機器前 利用一配送閥（dispenser)施加定量之助銲劑到基板20上 之預先設定位置。在步驟2 30，一自動化選取及安放的機 器將晶片1 0精確置放在基板上之預先設定位置，使得晶片 上之錫錯凸塊（solder bump)精確地對齊基板20上相對應 的焊墊22。該晶片上之錫鉛凸塊可利用習知的C4 (Controlled Collapse Chip Connection)製程形成，其 包含步驟（A)在晶片之晶片銲墊（bonding pad)上形成一錫 球突起下冶金（under bump metallurgy, UBM);以及步驟 (B)在UBM上形成錫球突起《4 456 1 8 V. Description of the invention (5) 210 Provide grave board 220 230 Put on flip chip 240 250 Bake 260 270 Curing Description of the invention: The third figure shows a reflow soldering according to the present invention-the flip chip of the preferred embodiment Flow chart of packaging structure manufacturing method. The fourth figure shows that a wafer 10 is mounted on a substrate 20 using the flip-chip technology of the third figure. In step 210 ', the substrate 20 can be formed using any build-up process technology. In addition, the substrate 20 may also be a multi-layer ceramic substrate. The substrate 20 has a plurality of contact pads 22 provided at predetermined positions on the substrate 20. The application of the flux in step 2 2 0 'is generally achieved by a dispensing method, which is a predetermined setting of applying a predetermined amount of flux to the substrate 20 by a dispenser before the substrate 20 is fed into the wafer placement machine. position. In steps 2 to 30, an automated picking and placing machine accurately places the wafer 10 on a predetermined position on the substrate, so that solder bumps on the wafer are precisely aligned with corresponding solder pads on the substrate 20. twenty two. The tin-lead bumps on the wafer can be formed by the conventional C4 (Controlled Collapse Chip Connection) process, which includes step (A) forming an under bump on the wafer's bonding pad. metallurgy, UBM); and step (B) forming solder ball protrusions on UBM
4 4 5 6 1 3 五、發明說明（6) 此外，助銲劑的施加亦可利用浸潰法（dip fluxing)遠 成。浸潰器（dip fluxer) —般係設計在晶片安放機器内’ 其包含一平坦的旋轉平台以預備一層助銲劑。由於助銲劑 有點黏稠，因此需要利用一稱為「刮刀（doctor blade)」 的表面處理工具將助銲劑平整至所需深度（一般為20至60 mm)。此實施例中，在步驟2 2 0，該晶片1 0會先移至該浸 漬器，浸入助銲劑。在步驟230，當助銲劑施加完成後， 該晶片10會先被提高移出該層助銲劑，然後精確置放在基 板上之預先設定位置，使得晶片上之錫鉛凸塊精確地對齊 基板20上相對應的焊墊22。 適合的助銲劑為構自The Kester Solder Division of Litton Systems， Inc·的免清洗式助銲劑（n〇_ciean type flux) ° 在步驟240 ’該步驟23 0之產物被移至一回焊 oven)内，並且經由該回焊製程形成錫鉛連接（s〇lder j〇in〇22。該錫鉛連接22係用以將該晶片1〇固定於基板2〇 並且電性連接該晶片10至基板20。 各驟!50 ’該步驟240之產物係被供烤以去除該基板 及大致除去回焊後殘餘之助銲劑所含有之易 Ti ft分。該烘烤製程之條件一般為11 0 C加私至 時。該烘烤製程較佳係在一旲有迪f c加…約4 ^ (convection oven)中進行，以抽氣系統之對流爐 從烘烤環境移除。 以允井水分及易揮發性成分4 4 5 6 1 3 V. Description of the invention (6) In addition, the application of flux can also be achieved by dip fluxing. A dip fluxer—generally designed in a wafer placement machine ’which contains a flat rotating platform to prepare a layer of flux. Because the flux is a little sticky, a surface treatment tool called a "doctor blade" is required to level the flux to the required depth (typically 20 to 60 mm). In this embodiment, in step 220, the wafer 10 is first moved to the dipper and immersed in flux. In step 230, after the application of the flux is completed, the wafer 10 is first lifted out of the layer of flux, and then accurately placed on a predetermined position on the substrate, so that the tin-lead bumps on the wafer are accurately aligned on the substrate 20. Corresponding welding pad 22. A suitable flux is a no-clean flux (n0_ciean type flux) constructed from The Kester Solder Division of Litton Systems, Inc. ° At step 240 'the product of step 230 is moved to a back solder oven) And a tin-lead connection (solder jinin 22) is formed through the re-soldering process. The tin-lead connection 22 is used to fix the wafer 10 to the substrate 20 and electrically connect the wafer 10 to the substrate 20 Each step! 50 'The product of step 240 is used for baking to remove the substrate and roughly remove the easy Ti ft content of the residual flux after reflow. The conditions of the baking process are generally 11 0 C plus private At that time, the baking process is preferably performed in a convection oven with about 4 ^ (convection oven), and is removed from the baking environment by a convection oven of an extraction system. To allow well moisture and easy volatility ingredient
4 4 5 6 1 五、發明說明（7) 在步驟2 6 0，填膠30係利用一自動化點膠系統 (automated underfill dispense system)將填膠材料點 在該晶片1 0之邊緣。然後該填膠材料經由毛細作用吸到晶 片10之下而完成填膠製程。 在步驟2 7 0，該步驟2 6 0之產物被移至一填躁固化爐 (underfill curing oven)内’然後固 4匕該填膠 30 。 根據本發明之覆晶接合製程，在步驟250的烘烤製程 中’該基板多餘之水分已被移除，並且該回焊後殘餘助銲 劑所含之易揮發性成分已大致被去除。因此，在步驟260 固化該填膠的過程中，孔隙（void)之發生機率大幅降低， 因而增進晶片及基板之間的機械以及電性連接（即錫鉛連 接1 2 )的可靠性。此外，由於該基板烘烤去除多餘水分後 之下一步驟即為填膠固化製程，因此可以去除基板在中間 步驟進行時再吸收水氣之干擾，而進一步降低孔隙（v〇id) 之發生機率。 雖然本發明已以前述較佳實施例揭示，然其並非用以 限^本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍内，當可作各種之更動與修改。因此本發明之保護 範圍當視後附之申請專利範圍所界定者為準。4 4 5 6 1 V. Description of the invention (7) In step 2 60, the filling 30 uses an automated underfill dispense system to place the filling material on the edge of the wafer 10. The glue-filling material is then sucked under the wafer 10 by capillary action to complete the glue-filling process. At step 270, the product of step 260 is moved into an underfill curing oven 'and then the glue 30 is cured. According to the flip-chip bonding process of the present invention, in the baking process of step 250, the excess moisture of the substrate has been removed, and the volatile components contained in the residual flux after the reflow have been substantially removed. Therefore, during the curing process of step 260, the occurrence of voids is greatly reduced, thereby improving the reliability of the mechanical and electrical connection (ie, the tin-lead connection 12) between the wafer and the substrate. In addition, since the next step after the substrate is baked to remove excess water is the glue-filling curing process, it can remove the interference of moisture absorption when the substrate is in the middle step, and further reduce the probability of occurrence of pores. . Although the present invention has been disclosed in the foregoing preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope of the attached patent application.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW089103105A TW445618B (en) | 2000-02-21 | 2000-02-21 | Manufacturing method of flip-chip package |
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| Application Number | Priority Date | Filing Date | Title |
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| TW089103105A TW445618B (en) | 2000-02-21 | 2000-02-21 | Manufacturing method of flip-chip package |
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| TW445618B true TW445618B (en) | 2001-07-11 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
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2000
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7902679B2 (en) | 2001-03-05 | 2011-03-08 | Megica Corporation | Structure and manufacturing method of a chip scale package with low fabrication cost, fine pitch and high reliability solder bump |
| US8158508B2 (en) | 2001-03-05 | 2012-04-17 | Megica Corporation | Structure and manufacturing method of a chip scale package |
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