CN103137611A - 晶片堆迭构造及其制造方法 - Google Patents

晶片堆迭构造及其制造方法 Download PDF

Info

Publication number
CN103137611A
CN103137611A CN2013100216586A CN201310021658A CN103137611A CN 103137611 A CN103137611 A CN 103137611A CN 2013100216586 A CN2013100216586 A CN 2013100216586A CN 201310021658 A CN201310021658 A CN 201310021658A CN 103137611 A CN103137611 A CN 103137611A
Authority
CN
China
Prior art keywords
wafer
lower wafer
substrate
several
stacked structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN2013100216586A
Other languages
English (en)
Inventor
王琇如
许哲铭
唐和明
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Semiconductor Engineering Inc
Original Assignee
Advanced Semiconductor Engineering Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Semiconductor Engineering Inc filed Critical Advanced Semiconductor Engineering Inc
Priority to CN2013100216586A priority Critical patent/CN103137611A/zh
Publication of CN103137611A publication Critical patent/CN103137611A/zh
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152—Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10165—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/118—Post-treatment of the bump connector
    • H01L2224/11848—Thermal treatments, e.g. annealing, controlled cooling
    • H01L2224/11849—Reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81007—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a permanent auxiliary member being left in the finished device, e.g. aids for holding or protecting the bump connector during or after the bonding process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/8114—Guiding structures outside the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81191—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81194—Lateral distribution of the bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/8122—Applying energy for connecting with energy being in the form of electromagnetic radiation
    • H01L2224/8123—Polychromatic or infrared lamp heating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81234—Applying energy for connecting using means for applying energy being within the device, e.g. integrated heater
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81868—Infrared [IR] curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81885—Combinations of two or more hardening methods provided for in at least two different groups from H01L2224/81855 - H01L2224/8188, e.g. for hybrid thermoplastic-thermosetting adhesives
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8192—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)

Abstract

本发明公开一种晶片堆迭构造及其制造方法，所述晶片堆迭构造包含一基板、一下晶片、一下底部填充胶、一上晶片、一上底部填充胶及数个第一接合胶块。所述第一接合胶块设置在所述下晶片与上晶片之间及所述上晶片的数个角隅处且分别接合所述下晶片与所述上晶片。通过将所述第一接合胶块分别贴附在所述上晶片底面的角隅处，并通过加热使所述第一接合胶块固定接合于所述上晶片的角隅及下晶片之间，进而在填充上底部填充胶的过程中，避免所述上晶片的角隅或边缘处发生翘曲而造成接触不良的情形。

Description

晶片堆迭构造及其制造方法
技术领域
本发明是有关于一种晶片堆迭构造及其制造方法，特别是有关于一种晶片堆迭构造及其制造方法。
背景技术
现今，携带式个人电脑、智慧手机及数码相机等半导体装置皆具有多功能化及高性能化的设计，且有朝向轻薄短小的趋势，因而使半导体封装构造(semiconductor package)在许多电子装置的使用上越来越普遍，在半导体封装过程中，翘曲的问题也日
Figure BDA00002759515000011
受到重视，在以往研究中，造成封装构造翘曲原因主要为材料热膨胀系數不同所造成的不均匀翘曲，或是烘烤后本身固化收缩的材料特性。
例如，现有封装构造在制造过程中，先将倒装型的晶片覆设在基板上并以回流焊(reflow)工艺方式进行接合，接着，对晶片以底部填充胶(underfill)进行充填，并且进行烘烤的工艺。不过，基板与晶片受热时会因为热膨胀系数(coefficient of thermal expansion，CTE)的差异而有弯曲的情况，因而在晶片的角隅处产生所谓的翘曲(warpage)现象。
另一种现有堆迭式封装构造则是将两颗晶片上下堆迭在基板上，并利用直通硅晶穿孔(Through-Silicon Via)在下晶片形成导电穿孔，使上晶片与下晶片电性连接，不过，堆迭在上面的晶片（例如：记忆体晶片，Memory Die）与堆迭在下面的晶片（例如：逻辑晶片，Logic Die）的厚度越薄，晶片角隅翘曲的现象会更加明显，特别是上晶片的角隅翘曲会造成其凸块没有确实与下晶片的重布线层有效的结合，因此不利于堆迭式封装构造的薄型化趋势。
故，有必要提供一种晶片堆迭构造，以解决现有技术所存在的问题。
发明内容
有鉴于此，本发明提供一种晶片堆迭构造及其制造方法，以解决现有的堆迭晶片于封装过程中角隅产生翘曲的现象。
本发明的主要目的在于提供一种晶片堆迭构造，其可以通过在于上、下晶片之间设置胶块，以避免上晶片在角隅或边缘处发生翘曲。
本发明的次要目的在于提供一种晶片堆迭构造的制造方法，其可以通过在于上、下晶片之间设置胶块，以避免造成上晶片与下晶片接触不良的情形。
为达成本发明的前述目的，本发明一实施例提供一种晶片堆迭构造，其中所述晶片堆迭构造包含︰一基板、一下晶片、一下底部填充胶、一上晶片、一上底部填充胶及数个第一接合胶块。所述基板包含一基板表面，所述基板表面具有多个第一导电端子，所述下晶片包含一下晶片第一表面及一下晶片第二表面，其中所述下晶片第一表面面对所述基板表面及所述下晶片第二表面远离所述基板所述下晶片第一表面具有数个第二导电端子，所述下晶片第二表面具有数个下第三导电端子，其中所述下晶片的第二导电端子电性连接所述基板的第一导电端子，所述下底部填充胶设置在所述基板与下晶片之间且包覆所述第二导电端子，所述上晶片包含一上晶片表面其中所述上晶片表面具有数个第四导电端子，其中所述上晶片的第四导电端子电性连接所述下晶片第二表面的第三导电端子，所述第一接合胶块设置在所述下晶片与上晶片之间及所述上晶片的数个角隅处且分别接合所述下晶片与所述上晶片，所述上底部填充胶设置在所述下晶片与上晶片之间且包覆所述第四导电端子及所述第一接合胶块。
再者，为达成本发明的前述目的，本发明另一实施例提供一种晶片堆迭构造的制造方法，其中所述晶片堆迭构造的制造方法包含步骤︰提供一具有一下晶片的基板，所述下晶片位于所述基板之上，所述下晶片包含一下晶片第一表面及一下晶片第二表面，其中所述下晶片第一表面面对所述基板及所述下晶片第二表面远离所述基板，所述下晶片第二表面具有数个下第三导电端子；将数个第一接合胶块设置在所述下晶片上；提供一上晶片，所述上晶片包含一上晶片表面；其中所述上晶片表面具有数个第四导电端子；将所述上晶片设置在所述下晶片上，使所述第一接合胶块分别接合于所述上晶片底面的数个角隅处；提供一能量，使所述第一接合胶块产生固化；热压所述上晶片，使所述下晶片的第三导电端子与所述上晶片的第四导电端子焊接结合在所述上晶片与下晶片之间；及在所述上晶片与下晶片之间填充一上底部填充胶。
如上所述，所述第一接合胶块分别贴附在所述上晶片底面的角隅处，并通过加热使所述第一接合胶块固定接合于所述上晶片的四个角隅及下晶片之间，进而在填充上底部填充胶的过程中，避免所述上晶片的角隅或边缘处发生翘曲而造成所述第四导电端接触不良的情形。
附图说明
图1A是本发明一实施例的晶片堆迭构造的剖视图。
图1B是本发明图1A实施例的晶片堆迭构造的上视图。
图2是本发明另一实施例的晶片堆迭构造的剖视图。
图3A是本发明又一实施例的晶片堆迭构造的剖视图。
图3B是本发明图3A实施例的晶片堆迭构造的上视图。
图4A、4B、4C、4D及4E是本发明图1A实施例的晶片堆迭构造的制造方法的流程图。
图5A、5B、5C、5D及5E是本发明图3A实施例的晶片堆迭构造的制造方法的示意图。
具体实施方式
以下各实施例的说明是参考附加的图式，用以例示本发明可用以实施的特定实施例。再者，本发明所提到的方向用语，例如上、下、顶、底、前、后、左、右、内、外、侧面、周围、中央、水准、横向、垂直、纵向、轴向、径向、最上层或最下层等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本发明，而非用以限制本发明。
请参照图1A、1B所示，本发明一实施例的晶片堆迭构造100主要包含一基板2、一下晶片3、一下底部填充胶4(underfill)、一上晶片5、一上底部填充胶6(underfill)及数个第一接合胶块7。所述基板2包含一基板表面21，所述基板表面21具有多个第一导电端子211，所述下晶片3设置在所述基板2上方，所述上晶片5设置在所述下晶片3上方，在本实施例中，所述上晶片5例如记忆体晶片（Memory Die）的长宽度小于所述下晶片3例如逻辑晶片（Logic Die）。本发明将于下文利用图1A至1B逐一详细说明下实施例上述各元件的细部构造、组装关系及其运作原理。
请参照图1A、1B所示，所述下晶片3包含一下晶片第一表面31及一下晶片第二表面32，其中所述下晶片第一表面31面对所述基板表面21及所述下晶片第二表面32远离所述基板2，所述下晶片第一表面31具有数个第二导电端子311，所述下晶片第二表面32具有数个下第三导电端子321，其中所述下晶片3的第二导电端子311电性连接所述基板2的第一导电端子211，所述下底部填充胶4设置在所述基板2与下晶片3之间且包覆所述第二导电端子311，所述上晶片5包含一上晶片表面51，其中所述上晶片表面51具有数个第四导电端子511，其中所述上晶片5的第四导电端子511电性连接所述下晶片第二表面32的第三导电端子321，在本实施例中，所述第二导电端子311和第四导电端子511为锡凸块（Solder Bump），其利用图案化光刻胶及电镀或印刷技术，先将焊锡直接填置于下晶片31及上晶片5的图案化光刻胶开口内，接着再利用热能将锡凸块熔融成球形或类球形，再去除图案化光刻胶，即可完成锡凸块的制作。
所述第一接合胶块7设置在所述下晶片3与上晶片5之间及所述上晶片5的数个角隅处，且分别接合所述下晶片3与所述上晶片5，所述上底部填充胶6设置在所述下晶片3与上晶片5之间且包覆所述第四导电端子511及所述第一接合胶块7，根据本发明一实施方式，所述第一接合胶块7包覆至少一个所述第四导电端子511，在本发明一实施例中，所述第一接合胶块7为非导电胶膜（Noncon-ductive Film，NCF）或非导电性粘着剂（Noncon-ductivePaste，NCP），并包覆位于所述上晶片5的四个角隅处的四个第四导电端子511，再者，所述下底部填充胶4及上底部填充胶6可以是环氧树脂，其可在受热后固化，用以保护所述第二导电端子32与上导电端子42不受外力影响而损害。
另外，在本发明另一实施例中，请参照图2所示，所述第二导电端子311和第四导电端子511也可以为铜柱凸块(Copper Pillar Bump)，铜柱凸块不同于传统的锡凸块，但制作方式类似于锡凸块，但因铜的熔点极高，故铜柱凸块的底面(焊接面)必需另外预先设置预焊料(如锡合金)，所述铜柱凸块具有导电、导热和抗电子迁移能力等功能。
依据上述的结构，将图1A、1B所述四个第一接合胶块7分别贴附在所述上晶片5底面的四个角隅处，并通过加热使所述第一接合胶块7固定接合于所述上晶片5的四个角隅及下晶片3之间，进而在填充上底部填充胶6的过程中，避免所述上晶片5的角隅或边缘处发生翘曲而造成所述第四导电端子511接触不良（bumps non-contact）的情形。每一所述第一接合胶块7对应于所述上晶片5的一个角隅处的至少一个第四导电端子511，例如1个、2个、4个或以上，但其数量并不限于此。
请参照图3A、3B所示，本发明再一实施例的晶片堆迭构造100相似于本发明图1A、1B实施例，并大致沿用相同元件名称及图号，但本实施例的差异特征在于：所述晶片堆迭构造100还包含至少一个第二接合胶块8（本实施例为四个），所述第二接合胶块8设置在所述基板2上且分别接合于所述下晶片3底面的四个角隅处。在本实施例中，所述第二接合胶块8为非导电胶膜（Noncon-ductive Film，NCF）或非导电性粘着剂（Noncon-ductive Paste，NCP）。
依据上述的结构，将所述四个第二接合胶块8分别设置在所述下晶片3底面的四个角隅处，并通过加热使所述第二接合胶块8固定接合于所述下晶片3的四个角隅及基板2之间，进而在填充下底部填充胶4的过程中，避免所述下晶片3的角隅或边缘处翘曲而造成所述第二导电端子311接触不良的情形。每一所述第二接合胶块8对应于所述下晶片3的一个角隅处的至少一个第二导电端子311，例如1个、2个、4个或以上，但其数量并不限于此。
请参照图4A至图4D并配合图1A及1B，其显示依照本发明的一实施例的流程图。本实施例的的晶片堆迭构造的制造方法可包括如下步骤：
如图4A所示，提供一具有一下晶片3的基板2，所述下晶片3位于所述基板2之上，所述下晶片3包含一下晶片第一表面31及一下晶片第二表面32，其中所述下晶片第一表面31面对所述基板2及所述下晶片第二表面32远离所述基板2，所述下晶片第二表面32具有数个下第三导电端子321，利用一活塞加压的筒体91填充一下底部填充胶4于所述下晶片3及基板2之间，且使所述下底部填充胶4包覆数个第二导电端子311，其中所述下底部填充胶4为环氧树脂，具有表面张力低及卓越的毛细渗透效果，可带来平坦、快速和完全的扩散。
如图4B所示，将数个第一接合胶块7设置在所述下晶片3上，提供一上晶片5，所述上晶片5包含一上晶片表面51；其中所述上晶片表面51具有数个第四导电端子511，将所述上晶片5设置在所述下晶片3上，使所述第一接合胶块7分别接合于所述上晶片5底面的数个角隅处，而位于所述上晶片5与下晶片3之间，并利用一乘载具92预先对所述上晶片5顶面施予一向下压力，而增加所述第一接合胶块7于所述上晶片5及下晶片3的附合度。
如图4C所示，提供一能量93（例如红外线光源）投射于所述上晶片5上表面的四个角隅，红外线光源的热会传导至所述上晶片5下表面的四个角隅，使所述第一接合胶块7遇热产生固化，并同时间使包覆在所述第一接合胶块7内的数个第四导电端子511受热熔化而可预先焊接结合在所述上晶片5与下晶片3之间，此方式可称为穿透式加热结合(transmission bonding)工艺。
如图4D所示，热压所述上晶片5，使所述下晶片3的第三导电端子321与所述上晶片5的第四导电端子511焊接结合在所述上晶片5与下晶片3之间，此方式可称为热压结合(thermal press bonding)工艺。再者，为了避免在热压结合时再次熔化角隅处已预先焊接结合到所述第四导电端子511，所述角隅处的第四导电端子511可以使用相对较高熔点的锡凸块(或使用具有相对较高熔点预焊料的铜柱凸块)，而除所述四个角隅外的其余区域的第四导电端子511则可以使用相对较低熔点的锡凸块(或使用具有相对较低熔点预焊料的铜柱凸块)。
如图4E所示，利用所述活塞加压的筒体91在所述上晶片5与下晶片3之间填充一上底部填充胶6，所述上底部填充胶6同样为环氧树脂，通过毛细渗透效果扩散且包覆所述第四导电端子511，以完成本实施例的晶片堆迭构造。
请参照图5A至图5E并配合图3A及3B，其显示依照本发明的又一实施例的流程图。本实施例的晶片堆迭构造的制造方法可包括如下步骤：
如图5A所示，将数个第二接合胶8设置在一基板2的上，将所述下晶片3设置在所述基板2上，使所述第二接合胶块8分别接合于所述下晶片3底面的数个角隅处，而位于所述下晶片3与基板2之间，并利用一乘载具92预先对所述下晶片3顶面施予一向下压力，而增加所述第二接合胶8于所述下晶片3与基板2的附合度。
如图5B所示，提供一能量93（例如红外线光源）投射于所述下晶片3的四个角隅，红外线光源的热会传导至所述下晶片3下表面的四个角隅，使所述第二接合胶8遇热产生固化，并使包覆在所述第二接合胶8内的数个第二导电端子311先焊接结合在所述下晶片3与基板2之间。
如图5C所示，热压所述下晶片3，使所述下晶片3除所述四个角隅外的其余区域的数个第二导电端子311焊接结合在所述下晶片3与所述基板2之间。
如图5D所示，利用所述活塞加压的筒体91在所述下晶片3与基板2之间填充一下底部填充胶4，使所述下底部填充胶4包覆除所述四个角隅外的其余区域的数个第二导电端子311。
接着，如图4A至图4D的过程，将数个第一接合胶块7及一上晶片5设置在所述下晶片3上，在经过红外线光源照射及热压将数个第四导电端子511先焊接结合在所述上晶片5与下晶片3之间，
最后，如图5E所示，利用所述活塞加压的筒体91于上晶片5与下晶片3之间填充一上底部填充胶6，以完成如图3A所示的晶片堆迭构造，其中所述第一接合胶块7及第二接合胶块8可分别预防所述上晶片5与下晶片3的角隅或边缘处发生翘曲。
本发明已由上述相关实施例加以描述，然而上述实施例仅为实施本发明的范例。必需指出的是，已公开的实施例并未限制本发明的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本发明的范围内。

Claims (10)

1.一种晶片堆迭构造，其特征在于：所述晶片堆迭构造包含︰
一基板，包含一基板表面，所述基板表面具有多个第一导电端子；
一下晶片，所述下晶片包含一下晶片第一表面及一下晶片第二表面，其中所述下晶片第一表面面对所述基板表面及所述下晶片第二表面远离所述基板，所述下晶片第一表面具有数个第二导电端子，所述下晶片第二表面具有数个下第三导电端子，其中所述下晶片的第二导电端子电性连接所述基板的第一导电端子；
一下底部填充胶，设置在所述基板与下晶片之间且包覆所述第二导电端子；
一上晶片，所述上晶片包含一上晶片表面，其中所述上晶片表面具有数个第四导电端子，其中所述上晶片的第四导电端子电性连接所述下晶片第二表面的第三导电端子；
数个第一接合胶块，设置在所述下晶片与上晶片之间及所述上晶片的数个角隅处且分别接合所述下晶片与所述上晶片；及
一上底部填充胶，设置在所述下晶片与上晶片之间且包覆所述第四导电端子及所述第一接合胶块。
2.如权利要求1所述的晶片堆迭构造，其特征在于：所述第一接合胶块包覆至少一个所述第四导电端子。
3.如权利要求1所述的晶片堆迭构造，其特征在于：所述第二电端子及第四电端子为铜柱凸块或锡凸块。
4.如权利要求1所述的晶片堆迭构造，其特征在于：所述第一接合胶块为非导电胶膜或非导电性粘着剂。
5.如权利要求1所述的晶片堆迭构造，其特征在于：所述晶片堆迭构造还包含数个第二接合胶块，设置在所述基板与所述下晶片之间的数个角隅处且分别接合于所述基板与所述下晶片。
6.一种晶片堆迭构造的制造方法，其特征在于：所述制造方法包含步骤︰提供一具有一下晶片的基板，所述下晶片位于所述基板之上，所述下晶片包含一下晶片第一表面及一下晶片第二表面，其中所述下晶片第一表面面对所述基板及所述下晶片第二表面远离所述基板，所述下晶片第二表面具有数个下第三导电端子；
将数个第一接合胶块设置在所述下晶片上；
提供一上晶片，所述上晶片包含一上晶片表面；其中所述上晶片表面具有数个第四导电端子；
将所述上晶片设置在所述下晶片上，使所述第一接合胶块分别接合于所述上晶片底面的数个角隅处；
提供一能量，使所述第一接合胶块产生固化；
热压所述上晶片，使所述下晶片的第三导电端子与所述上晶片的第四导电端子焊接结合在所述上晶片与下晶片之间；及
在所述上晶片与下晶片之间填充一上底部填充胶。
7.如权利要求6所述的晶片堆迭构造的制造方法，其特征在于：在填充所述下底部填充胶的步骤之前，所述制造方法还包含步骤︰
将数个第二接合胶块设置在所述基板上；
将所述下晶片设置在所述基板上，使所述第二接合胶块分别接合于所述下晶片底面的数个角隅处；
提供另一能量，使所述第二接合胶块产生固化，并使包覆在所述第二接合胶块内的数个第二导电端子先焊接结合在所述下晶片与基板之间；及
热压所述下晶片，使所述下晶片数个第二导电端子焊接结合在所述下晶片与基板之间。
8.如权利要求6所述的晶片堆迭构造的制造方法，其特征在于：在所述能量于所述上晶片之前，预先对所述上晶片顶面施予一向下压力。
9.如权利要求7所述的晶片堆迭构造的制造方法，其特征在于：在所述另一能量于所述下晶片之前，预先对所述下晶片顶面施予一向下压力。
10.如权利要求6或7所述的晶片堆迭构造的制造方法，其特征在于：所述能量为红外线光源。
CN2013100216586A 2013-01-22 2013-01-22 晶片堆迭构造及其制造方法 Pending CN103137611A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN2013100216586A CN103137611A (zh) 2013-01-22 2013-01-22 晶片堆迭构造及其制造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN2013100216586A CN103137611A (zh) 2013-01-22 2013-01-22 晶片堆迭构造及其制造方法

Publications (1)

Publication Number Publication Date
CN103137611A true CN103137611A (zh) 2013-06-05

Family

ID=48497218

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2013100216586A Pending CN103137611A (zh) 2013-01-22 2013-01-22 晶片堆迭构造及其制造方法

Country Status (1)

Country Link
CN (1) CN103137611A (zh)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108780790A (zh) * 2017-01-04 2018-11-09 华为技术有限公司 一种堆叠封装结构及终端
CN113161242A (zh) * 2021-02-23 2021-07-23 青岛歌尔微电子研究院有限公司 芯片封装工艺

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080017969A1 (en) * 2006-07-20 2008-01-24 Junichi Kimura Module and method of manufacturing the same
US20080093739A1 (en) * 2006-10-18 2008-04-24 Junichi Kimura Semiconductor mounting substrate and method for manufacturing the same
CN101336044A (zh) * 2007-06-29 2008-12-31 株式会社东芝 印刷电路板、电子部件的安装方法以及电子设备
CN102683330A (zh) * 2011-03-11 2012-09-19 株式会社东芝 半导体装置以及半导体装置的制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20080017969A1 (en) * 2006-07-20 2008-01-24 Junichi Kimura Module and method of manufacturing the same
US20080093739A1 (en) * 2006-10-18 2008-04-24 Junichi Kimura Semiconductor mounting substrate and method for manufacturing the same
CN101336044A (zh) * 2007-06-29 2008-12-31 株式会社东芝 印刷电路板、电子部件的安装方法以及电子设备
CN102683330A (zh) * 2011-03-11 2012-09-19 株式会社东芝 半导体装置以及半导体装置的制造方法

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN108780790A (zh) * 2017-01-04 2018-11-09 华为技术有限公司 一种堆叠封装结构及终端
CN108780790B (zh) * 2017-01-04 2020-10-27 华为技术有限公司 一种堆叠封装结构及终端
CN113161242A (zh) * 2021-02-23 2021-07-23 青岛歌尔微电子研究院有限公司 芯片封装工艺
CN113161242B (zh) * 2021-02-23 2022-03-25 青岛歌尔微电子研究院有限公司 芯片封装工艺
WO2022179296A1 (zh) * 2021-02-23 2022-09-01 青岛歌尔微电子研究院有限公司 芯片封装工艺

Similar Documents

Publication Publication Date Title
US9263426B2 (en) PoP structure with electrically insulating material between packages
JP5814859B2 (ja) 半導体装置とその製造方法
JP5579402B2 (ja) 半導体装置及びその製造方法並びに電子装置
JP4023159B2 (ja) 半導体装置の製造方法及び積層半導体装置の製造方法
US8034660B2 (en) PoP precursor with interposer for top package bond pad pitch compensation
US20070246811A1 (en) Stack structure of semiconductor packages and method for fabricating the stack structure
US8274153B2 (en) Electronic component built-in wiring substrate
TW201511209A (zh) 半導體裝置及半導體裝置之製造方法
US9985013B2 (en) Package-on-package structure and methods for forming the same
KR101299852B1 (ko) 비대칭적으로 배열된 다이 및 몰딩을 포함하는 멀티패키지 모듈
WO2014034691A1 (en) Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack
JP2008258522A (ja) 半導体装置の製造方法
KR20170016550A (ko) 반도체 패키지의 제조 방법
JP2013021058A (ja) 半導体装置の製造方法
US8617923B2 (en) Semiconductor device manufacturing apparatus and method for manufacturing semiconductor device
TW201923985A (zh) 具有多層囊封物之半導體裝置及相關系統、裝置及方法
JP2012146853A (ja) 半導体装置の製造方法
CN101853835A (zh) 倒装芯片封装及其制造方法
KR20120058118A (ko) 적층 패키지의 제조 방법, 및 이에 의하여 제조된 적층 패키지의 실장 방법
CN103137611A (zh) 晶片堆迭构造及其制造方法
CN107342237A (zh) 制造半导体封装件的方法和制造PoP半导体装置的方法
CN104934379A (zh) 封装堆栈结构及其制法
JP6792322B2 (ja) 半導体装置及び半導体装置の製造方法
CN102956547A (zh) 半导体封装结构及其制作方法
TWI416641B (zh) 製造一半導體結構之方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C02 Deemed withdrawal of patent application after publication (patent law 2001)
WD01 Invention patent application deemed withdrawn after publication

Application publication date: 20130605