CN106922087A - 半导体安装设备及其头部以及用于制造叠层芯片的方法 - Google Patents

半导体安装设备及其头部以及用于制造叠层芯片的方法 Download PDF

Info

Publication number
CN106922087A
CN106922087A CN201611088242.6A CN201611088242A CN106922087A CN 106922087 A CN106922087 A CN 106922087A CN 201611088242 A CN201611088242 A CN 201611088242A CN 106922087 A CN106922087 A CN 106922087A
Authority
CN
China
Prior art keywords
semiconductor chip
terminal
semiconductor
head
osculating element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201611088242.6A
Other languages
English (en)
Other versions
CN106922087B (zh
Inventor
吉良秀彦
增山卓己
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of CN106922087A publication Critical patent/CN106922087A/zh
Application granted granted Critical
Publication of CN106922087B publication Critical patent/CN106922087B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/52Mounting semiconductor bodies in containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75Apparatus for connecting with bump connectors or layer connectors
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67098Apparatus for thermal treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67121Apparatus for making assemblies not otherwise provided for, e.g. package constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6838Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping with gripping and holding devices using a vacuum; Bernoulli devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L24/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657Stacked arrangements of devices
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
    • H01L2021/60007Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process
    • H01L2021/60022Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation involving a soldering or an alloying process using bump connectors, e.g. for flip chip mounting
    • H01L2021/60097Applying energy, e.g. for the soldering or alloying process
    • H01L2021/60172Applying energy, e.g. for the soldering or alloying process using static pressure
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/07Structure, shape, material or disposition of the bonding areas after the connecting process
    • H01L2224/09Structure, shape, material or disposition of the bonding areas after the connecting process of a plurality of bonding areas
    • H01L2224/091Disposition
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16135Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32135Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731Location prior to the connecting process
    • H01L2224/73101Location prior to the connecting process on the same surface
    • H01L2224/73103Bump and layer connectors
    • H01L2224/73104Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/7525Means for applying energy, e.g. heating means
    • H01L2224/753Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/75301Bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/75Apparatus for connecting with bump connectors or layer connectors
    • H01L2224/757Means for aligning
    • H01L2224/75743Suction holding means
    • H01L2224/75745Suction holding means in the upper part of the bonding apparatus, e.g. in the bonding head
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Die Bonding (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Abstract

本发明涉及半导体安装设备及其头部以及用于制造叠层芯片的方法。半导体安装设备包括:存储单元,其存储液体或者气体;接触单元,其在存储单元充满液体或者气体时与半导体芯片相接触;以及吸取单元,其吸取半导体芯片以使半导体芯片与接触单元紧密接触。

Description

半导体安装设备及其头部以及用于制造叠层芯片的方法
技术领域
本发明涉及半导体安装设备及其头部以及用于制造叠层芯片的方法。
背景技术
用于高端服务器等中的处理器和存储器在一些情况下使用叠层半导体芯片,在该叠层半导体芯片中层叠多个半导体芯片以用于性能提高。如图12所示,在半导体芯片101上形成端子(微凸块)104。端子104包括铜柱(铜桩或铜墩)102以及在铜柱102的顶部上形成的焊料103。因此,使用了以下方法:其中多个半导体芯片101的端子104被接合以层叠多个半导体芯片101。
如图13所示,为了保证层叠多个半导体芯片101之后的接合的可靠性,在每个半导体芯片101上提供膏状或膜状增强型树脂105。膏状增强型树脂105又被称作NCP(非导电膏),而膜状增强型树脂105又被称作NCF(非导电膜)。如图14所示,从半导体安装设备例如倒装芯片焊接机(flip-chip bonder)的头部201的吸取孔202吸取半导体芯片101A。半导体芯片101B被布置在半导体芯片101A下面,在半导体芯片101B上形成多个端子104B。接下来,如图15所示,在加热半导体芯片101A的同时,通过头部201来对半导体芯片101A加压,以通过半导体芯片101A的端子104A来冲破增强型树脂105。从而,使半导体芯片101A的端子104A与半导体芯片101B的端子104B接合以保证半导体芯片101A与半导体芯片101B之间的电传导以及芯片的刚性。
[现有技术文献]
[专利文献]
[专利文献1]第2015-18897号日本专利特许公开
[专利文献2]第2011-66027号日本专利特许公开
[专利文献3]第2000-332390号日本专利特许公开
[专利文献4]第2001-230528号日本专利特许公开
发明内容
通过本发明要解决的问题
在半导体芯片101A中存在厚度的变化以及弯曲。因此,当用头部201对半导体芯片101A加压时,难以向半导体芯片101A施加均匀的压力。当向半导体芯片101A施加任何不均匀的压力时,半导体芯片101A的端子104A可能不能冲破增强型树脂105。因此,在半导体芯片101A的端子104A与半导体芯片101B的端子104B之间的接合中可能出现失败。
鉴于上述问题而提出的本申请的目的是提供一种向半导体芯片施加均匀的压力的技术。
解决问题的手段
根据本申请的一方面,一种半导体安装设备包括:存储单元,其存储液体或气体;接触单元,其在存储单元充满液体或气体时与半导体芯片相接触;以及吸取单元,其吸取半导体芯片以使半导体芯片与接触单元紧密接触。
根据本申请的一方面,一种用于制造叠层芯片的方法包括:在第一半导体芯片上布置头部,该头部包括:存储单元,其存储液体或气体;以及接触单元,其在存储单元充满液体或气体时与第一半导体芯片相接触;用液体或气体来填充存储单元;吸取第一半导体芯片以使第一半导体芯片与接触单元紧密接触;在第一半导体芯片上布置第二半导体芯片,以便第一半导体芯片的多个第一端子与第二半导体芯片的多个第二端子面向彼此;以及加热第二半导体芯片并且利用头部对第一半导体芯片加压,以使多个第一端子与多个第二端子接合。
发明效果
根据本申请,可以向半导体芯片施加均匀的压力。
附图说明
[图1]图1是半导体安装设备的配置图。
[图2]图2是头部的剖视图。
[图3]图3是临时放置台的剖视图。
[图4]图4是临时放置台的剖视图。
[图5]图5是临时放置台的剖视图。
[图6]图6是头部和临时放置台的剖视图。
[图7]图7是头部和临时放置台的剖视图。
[图8]图8是头部的剖视图。
[图9]图9是用于制造叠层芯片的方法的处理图。
[图10]图10是用于制造叠层芯片的方法的处理图。
[图11]图11是用于制造叠层芯片的方法的处理图。
[图12]图12是用于接合半导体芯片的方法的说明视图。
[图13]图13是用于接合半导体芯片的方法的说明视图。
[图14]图14是用于接合半导体芯片的方法的说明视图。
[图15]图15是用于接合半导体芯片的方法的说明视图。
[图16]图16是用于接合半导体芯片的方法的说明视图。
[图17]图17是用于接合半导体芯片的方法的说明视图。
具体实施方式
当半导体芯片101A具有按照设计的光洁度(finish)时,半导体芯片101A的上表面(半导体芯片101A的与形成有端子的表面相反的表面)是平坦的。此外,当在半导体芯片101A上形成的多个端子104A具有按照设计的光洁度时,多个端子104A按高度对齐。如图14所示,当半导体芯片101A的上表面是平坦的并且多个端子104A按照高度对齐时,即使当半导体芯片101A的上表面被吸取到头部201上时,多个端子104A的上表面仍互相平行对齐。半导体芯片101A的端子104A的上表面与半导体芯片101B相对。
如图16所示,存在半导体芯片101A中的厚度变化、端子104A中的高度变化以及半导体芯片101A中的弯曲。如图17所示,当半导体芯片101A的上表面被吸取到头部201上时,半导体芯片101A的上表面变平。然而,多个端子104A的上表面不再互相平行对齐。因此,半导体芯片101A的端子104A与半导体芯片101B的端子104B之间的距离在半导体芯片101A的中心部分与外周部分之间不同。
当半导体芯片101A的外部尺寸为10平方毫米或者更小时,在半导体芯片101A的端子104A与半导体芯片101B的端子104B之间的距离方面,半导体芯片101A的中心部分与外周部分之间的差别较小。因此,作为端子104A的焊料103A坍塌(collapse)的结果,可以使半导体芯片101A的端子104A与半导体芯片101B的端子104B接合。
另一方面,当半导体芯片101A的外部尺寸是20平方毫米或者更大时,在半导体芯片101A的端子104A与半导体芯片101B的端子104B之间的距离方面,半导体芯片101A的中心部分与外周部分之间的差别较大。因此,只要头部201吸附半导体芯片101A,其中半导体芯片101A的上表面保持平坦,则即使当半导体芯片101A上的压力(负荷)增加时,半导体芯片101A的多个端子104A中的所有端子也不可以接合至半导体芯片101B的多个端子104B。此外,用于使半导体芯片101A的端子104A与半导体芯片101B的端子104B接合的压力与半导体芯片101A的尺寸成比例地增加。因此,简单地增加压力可能引起对半导体芯片101A的物理性破坏。
在下文中,将参照附图来详细描述实施方式。实施方式的配置仅是示例,并且因此,本申请不限于实施方式的这些配置。
图1是半导体安装设备1的配置图。半导体安装设备1又被称作倒装芯片焊接机。半导体安装设备1包括:头部2;临时放置台3;保持台4;结合(bond)工具5;以及控制单元6。头部2附接至结合工具5,并且例如通过结合工具5来升高、降低以及平行移动头部2。临时放置台3是在以头部2支持上侧半导体芯片时临时放置有上侧半导体芯片的台体。当层叠多个半导体芯片时,通过头部2来支持被层叠的半导体芯片的最上面,而通过支持台4来支持被层叠的半导体芯片的最下面。此外,支持台4加热最下面的半导体芯片。
控制单元6包括未示出的中央处理单元(CPU)和存储器,以根据可执行地部署在该存储器中的计算机程序来控制由头部2、临时放置台3、支持台4以及结合工具5承担的操作和处理。CPU又被称作处理器。然而,CPU不限于单个处理器,也可以是多处理器。存储器例如包括ROM(只读存储器)和RAM(随机存取存储器)。
图2是头部2的剖视图。头部2包括支持单元21、加热器22、隔膜23、弹性体24以及吸取孔25。支持单元21支持加热器22、隔膜23和弹性体24。在头部2的底面和侧面上形成开口。吸取孔25穿过支持单元21、加热器22、隔膜23和弹性体24,以连接至头部2的底面和侧面上形成的开口。吸取单元(吸取机构)26连接至头部2的侧面上形成的开口。于是,吸取孔25连接至吸取单元26。驱动吸取单元26以从吸取孔25吸取半导体芯片11A,从而使得半导体芯片11A吸附至头部2的底面上。吸取单元26例如是真空吸取泵。
在图2中示出的头部2的结构示例中,头部2包括一个吸取孔25。然而,头部2不限于图2中示出的结构示例。头部2可以包括多个吸取孔25。在该情况下,多个吸取孔25中的每一个连接至吸取单元26。例如,位于头部2的中心部分中的至少一个吸取孔25可以吸取半导体芯片11A的中心部分,并且位于头部2的外周部分中的至少一个吸取孔25可以吸取半导体芯片11A的外周部分。在图2中示出的头部2的结构示例中,吸取单元26被布置在头部2的外部。然而,头部2不限于图2中示出的结构示例。吸取单元26可以被布置在头部2的内部。因此,头部2可以包括吸取单元26。
加热器22是加热单元(加热机构)。加热器22加热半导体芯片11A。由加热器22产生的热量通过隔膜23和弹性体24传递至半导体芯片11A。因此,隔膜23和弹性体24优选地具有高的耐热性。例如,隔膜23和弹性体24可以具有200℃或者更高的耐热性。
通过布置在隔膜23的侧表面上的阀27将液体或气体从供给单元(馈给机构)28提供到隔膜23中。隔膜23因此存储液体或者气体。存储(填充)在隔膜23内的液体例如是易熔合金或者油。存储(填充)在隔膜23内的气体例如是空气。隔膜23由弹性材料形成。弹性体24位于隔膜23的底部上。弹性体24例如是硅橡胶。隔膜23根据填充在隔膜23内的液体或者气体的量(体积、压力等)而变形。弹性体24根据隔膜23的变形而变形。即,隔膜23根据填充在隔膜23内的液体或气体的量来变形,并且弹性体24同样如此。隔膜23是存储单元的一个示例。弹性体24是接触单元的一个示例。
<对半导体芯片的支持>
将参考图3至图8来描述通过头部2对半导体芯片11A的支持。图3和图4是临时放置台3的剖视图。临时放置台3是在通过头部2来支持半导体芯片11A之前临时放置半导体芯片11A的台体。临时放置台3包括台体(板体)31、支持单元32以及吸取孔33。支持单元32支持台体31。临时放置台3还包括安装表面3A,在该安装表面3A上放置半导体芯片11A。在安装表面3A和临时放置台3的侧面上形成开口。吸取孔33穿过台体31和支持单元32,以连接至安装表面3A和临时放置台3的侧面上形成的开口。吸取单元(吸取机构)34连接至临时放置台3的侧面上形成的开口。因此,吸取孔33连接至吸取单元34。吸取单元34例如是真空吸取泵。
在半导体芯片11A上形成端子(微凸块)14A。端子14A包括铜柱(铜桩或铜墩)12A以及在铜柱12A的顶部上形成的焊料13A。半导体芯片11A包括:多个端子14A;表面(端子形成表面)15A,在其上形成多个端子14A;以及与端子形成表面15A相反的表面(背面)16A。图3中示出的半导体芯片11A的背面16A具有凹圆弧形,并且半导体芯片11A的多个端子14A未按照高度对齐。因此,半导体芯片11A的多个端子14A的上表面17A未互相平行对齐。半导体芯片11A的端子14A的上表面17A和端子形成表面15A面向相同的方向,并且与图3中的临时放置台3的安装表面3A相对。驱动吸取单元34以从吸取孔33吸取半导体芯片11A的端子形成表面15A,从而使得半导体芯片11A被吸附至临时放置台3的安装表面3A上。可以在半导体芯片11A被放置在临时放置台3的安装表面3A上之前通过吸取单元34来执行吸取。替选地,可以在半导体芯片11A被放置在临时放置台3的安装表面3A上之后通过吸取单元34来执行吸取。
吸取单元34从半导体芯片11A的端子形成表面15A侧吸取半导体芯片11A,以便多个端子14A的上表面17A中的每一个与临时放置台3的安装表面3A之间的距离相同。通过控制单元6来控制通过吸取单元34的吸取的力量。如图4所示,作为半导体芯片11A从半导体芯片11A的端子形成表面15A侧被吸取的结果,多个端子14A的上表面17A互相平行对齐。在图4中,由于多个端子14A的上表面互相平行对齐,因此多个端子14A中的所有端子均与临时放置台3的安装表面3A相接触。
图3和图4图示了未在半导体芯片11A的端子形成表面15A上形成增强型树脂的示例。替选地,如图5所示,可以在半导体芯片11A的端子形成表面15A上形成增强型树脂18A。图5是临时放置台3的剖视图。增强型树脂18A是膜NCF。吸取单元34从半导体芯片11A的端子形成表面15A侧吸取半导体芯片11A和增强型树脂18A,以便多个端子14A的上表面17A中的每一个与临时放置台3的安装表面3A之间的距离相同。通过控制单元6来控制通过吸取单元34的吸取的力量。如图5所示,作为半导体芯片11A和增强型树脂18A从半导体芯片11A的端子形成表面15A侧被吸取的结果,多个端子14A的上表面17A互相平行对齐。
在图3至图5中所示的临时放置台3的结构示例中,临时放置台3包括一个吸取孔33。然而,临时放置台3不限于图3至图5中所示的结构示例。临时放置台3可以包括多个吸取孔33。在该情况下,多个吸取孔33中的每一个连接至吸取单元34。例如,位于临时放置台3的中心部分中的至少一个吸取孔33可以吸取半导体芯片11A的中心部分,并且位于临时放置台3的外周部分中的至少一个吸取孔33可以吸取半导体芯片11A的外周部分。在图3至图5中所示的临时放置台3的结构示例中,吸取单元34被布置在临时放置台3的外部。然而,临时放置台3不限于图3至图5中示出的结构示例。吸取单元34可以被布置在临时放置台3的内部。因此,临时放置台3可以包括吸取单元34。
通过结合工具5来降低头部2,同时直到头部2马上与半导体芯片11A相接触之前一直保持半导体芯片11A被吸附到临时放置台3的安装表面3A上这一状况。如图6所示,降低头部2以将头部2布置在半导体芯片11A上。因此,隔膜23和弹性体24被布置在半导体芯片11A的背面16A上。应该注意的是,可以在半导体芯片11A的端子形成表面15A上形成增强型树脂18A。
接下来,打开布置在隔膜23的侧面上的阀27以将液体或气体从供给单元28提供到隔膜23中,以便向隔膜23填充液体或者气体。如图7所示,当隔膜23充满液体或者气体时,隔膜23的中心部分向半导体芯片11A隆起。因此,弹性体24的中心部分向半导体芯片11A弯曲,从而使得弹性体24与半导体芯片11A的背面16A相接触。如上所述,当隔膜23充满液体或者气体时,隔膜23和弹性体24变形,从而使得弹性体24与半导体芯片11A的背面16A相接触。当弹性体24与半导体芯片11A的背面16A相接触时,隔膜23和弹性体24根据半导体芯片11A的背面16A的形状而变形。例如,当半导体芯片11A的背面16A具有凹圆弧形时,隔膜23和弹性体24变形成与半导体芯片11A的背面16A相符的凹圆弧形。
当弹性体24根据半导体芯片11A的背面16A的形状而变形时,关闭布置在隔膜23的侧面上的阀27,以防止填充在隔膜23内的液体或者气体的量变化。通过控制单元6来控制阀27的打开和闭合。例如,当达到目标填充量时,可以调整填充在隔膜23内的液体或者气体的量,以关闭布置在隔膜23的侧面的阀27。替选地,可以将隔膜23和弹性体24根据半导体芯片11A的背面16A的形状而变形时的填充量限定为目标填充量。关于目标填充量的数据被存储于控制单元6中。
接下来,吸取单元26执行吸取,以从吸取孔25吸取半导体芯片11A。因此,半导体芯片11A的背面16A吸附至弹性体24,并且因此,弹性体24与半导体芯片11A的背面16A彼此紧密接触。因此,在隔膜23和弹性体24已经根据半导体芯片11A的背面16A的形状而变形的情况下,半导体芯片11A的背面16A与弹性体24紧密接触。吸取单元26是吸取单元的一个示例。尽管图3至图7中示出的半导体芯片11A的背面16A具有凹圆弧形,但是在一些情况下,每个半导体芯片11A的背面16A可以具有凸圆弧形。即使当半导体芯片11A的背面16A具有凸圆弧形时,隔膜23和弹性体24也会根据半导体芯片11A的背面16A的形状而变形。因此,弹性体24和半导体芯片11A的背面16A彼此紧密接触。例如,当半导体芯片11A的背面16A具有凸圆弧形时,隔膜23和弹性体24变形成与半导体芯片11A的背面16A相符的凸圆弧形。
随后,通过结合工具5来升高头部2,以提升放置在临时放置台3上的半导体芯片11A。如图8所示,即使当将从临时放置台3移开半导体芯片11A时,弹性体24和半导体芯片11A的背面16A仍保持彼此紧密接触。作为结果,半导体芯片11A的背面16A在多个端子14A的上表面17A彼此平行对齐的情况下吸附至弹性体24。应该注意的是,当提升半导体芯片11A时,可以停止通过吸取单元34的吸取处理。
半导体芯片11A的厚度和弯曲针对每个晶片批次(lot)可能出现变化。此外,每个端子14A的高度可能变化。根据按照实施方式的半导体安装设备1和头部2,弹性体24在形状方面依照半导体芯片11A的背面16A的形状而变化,其中多个端子14A的上表面17A互相平行对齐。因此,可以在保持多个端子14A的上表面17A互相平行对齐的状况的同时保持弹性体24和半导体芯片11A的背面16A彼此紧密接触的状况。因此,即使当晶片批次或者芯片规格变化时,头部2也可以使半导体芯片11A保持在多个端子14A的上表面17A互相平行对齐的状况下,而无需替换头部2、结合工具5等。
在图2以及图6至图8中示出的头部2的结构示例中,弹性体24被布置在隔膜23的底部。然而,头部2不限于图2以及图6至图8中示出的结构示例。不需要将弹性体24布置在头部2中。即使在该情况下,隔膜23仍根据半导体芯片11A的背面16A的形状而变形,并且因此,隔膜23和半导体芯片11A的背面16A彼此紧密接触。从而,头部2可以使半导体芯片11A保持在多个端子14A的上表面17A互相平行对齐的状况下。可以使隔膜23和弹性体24彼此成为整体。
<用于制造叠层芯片的方法>
将参照图9至图11来描述用于制造叠层芯片(半导体装置)的方法。在用于制造叠层芯片的方法中,头部2支持半导体芯片11A的处理与参照图3至图8所描述的处理是相同的,并且因此,将不会在此处讨论。因此,在此处将讨论在头部2支持半导体芯片11A的处理之后的处理。
如图9所示,半导体芯片11B被放置在支持台4上。图9是支持台4的剖视图。支持台4包括台体(板体)41、加热器42、支持单元43以及吸取孔44。支持台4是加热台的一个示例。支持单元43支持台体41和加热器42。支持台4还包括安装表面4A,在该安装表面4A上放置半导体芯片11B。在安装表面4A和支持台4的侧面上形成开口。吸取孔44穿过台体41、加热器42和支持单元43,以连接至安装表面4A和支持台4的侧面上形成的开口。吸取单元(吸取机构)45连接至支持台4的侧面上形成的开口。因此,吸取孔44连接至吸取单元45。吸取单元45例如是真空吸取泵。
在半导体芯片11B上形成端子(微凸块)14B。端子14B包括铜柱12B以及在铜柱12B的顶部上形成的焊料13B。此外,在半导体芯片11B上形成增强型树脂18B。增强型树脂18B可以是膜NCF或者膏NCP。当在半导体芯片11A上形成增强型树脂18A时,不需要在半导体芯片11B上形成增强型树脂18B。半导体芯片11B包括:多个端子14B;表面(端子形成表面)15B,在其上形成多个端子14B;以及与端子形成表面15B相反的表面(背面)16B。在支持台4上支持半导体芯片11B,以便半导体芯片11B的背面16B与支持台4的安装表面4A面向彼此。
驱动吸取单元45以从吸取孔44吸取半导体芯片11B,从而使得半导体芯片11B吸附到支持台4的安装表面4A上。可以在半导体芯片11B被放置在支持台4的安装表面4A上之前执行通过吸取单元45的吸取。替选地,可以在半导体芯片11B被放置在支持台4的安装表面4A上之后执行通过吸取单元45的吸取。应该注意的是,可以在支持半导体芯片11A的处理之前实施图9中示出的支持半导体芯片11B的处理。
接下来,通过结合工具5来移动头部2以将半导体芯片11A定位于半导体芯片11B的上面。在该情况下,如图10所示,定位半导体芯片11A以便半导体芯片11A的端子形成表面15A与半导体芯片11B的端子形成表面15B面向彼此。随后,使用未示出的识别摄像机来使半导体芯片11A与半导体芯片11B对齐。作为半导体芯片11A与半导体芯片11B被对齐的结果,半导体芯片11A的多个端子14A与半导体芯片11B的多个端子14B面向彼此。之后,通过结合工具5来降低头部2。当降低头部2时,载荷被施加于半导体芯片11A以对半导体芯片11A执行加压处理。由于弹性体24和半导体芯片11的背面16A彼此紧密接触,因此可以对半导体芯片11A施加均匀的压力。
当通过头部2对半导体芯片11A执行加压处理时,加热器22和加热器42开始加热处理。升高加热器42的加热温度以对半导体芯片11B执行加热处理。即,由加热器42产生的热量传递至台体41以加热半导体芯片11B。作为半导体芯片11B被加热的结果,热量从半导体芯片11B传递至增强型树脂18B。作为增强型树脂18B被加热的结果,增强型树脂18B软化。作为在增强型树脂18B变软的同时半导体芯片11A被加压的结果,半导体芯片11A的端子14A埋入(bury)增强型树脂18B中,以冲破增强型树脂18B。由于弹性体24和半导体芯片11A的背面16A彼此紧密接触,所以可以对半导体芯片11A施加均匀的压力。作为结果,半导体芯片11A的端子14A可以轻松地冲破增强型树脂18B。如图11所示,作为半导体芯片11A的端子14A冲破增强型树脂18B的结果,半导体芯片11A的端子14A与半导体芯片11B的端子14B彼此接触。
升高加热器22的加热温度以对半导体芯片11A执行加热处理。通过加热器22来对半导体芯片11A执行加热处理,以防止从加热器42传递至半导体芯片11B和增强型树脂18B的热量通过半导体芯片11A被消散。即,加热器22对半导体芯片11A执行热量保持。通过加热器22对半导体芯片11A执行的加热处理可能引起填充在隔膜23中的液体或气体的量发生变化。在该情况下,可以打开或者关闭布置在隔膜23的侧面上的阀27以调整填充在隔膜23中的液体或者气体的量。替选地,可以在支持单元21与隔膜23之间布置隔热材料以代替加热器22。
可以在半导体芯片11A和11B的加热处理开始之后开始半导体芯片11A的加压处理。替选地,可以在半导体芯片11A的加压处理开始之后开始半导体芯片11A和11B的加热处理。这样,可以使半导体芯片11A和11B的加热处理的起始点与半导体芯片11A的加压处理的起始点彼此不同。又替选地,可以同时开始半导体芯片11A的加压处理和半导体芯片11B的加热处理。再替选地,可以使半导体芯片11A的加热处理的起始点与半导体芯片11B的加热处理的起始点彼此不同。再替选地,可以同时开始半导体芯片11A的加热处理和半导体芯片11B的加热处理。
加热器42将焊料13A和13B的加热温度提高到焊料13A和13B的熔化温度。通过使焊料13A和13B因此熔化来将焊料13A和13B接合在一起。作为结果,半导体芯片11A的端子14A与半导体芯片11B的端子14B被接合,从而保证半导体芯片11A与半导体芯片11B之间的电传导以及芯片的刚性。以这种方式来制造设置有半导体芯片11A和11B的叠层芯片。
不需要形成增强型树脂18A和18B。在该情况下,在半导体芯片11A的端子14A与半导体芯片11B的端子14B被接合之后,使用分配器来在半导体芯片11A与半导体芯片11B之间填充底层填料(underfill)。
在图9和图10中示出的支持台4的结构示例中,支持台4包括一个吸取孔44。然而,支持台4不限于图9和图10中示出的支持台4的结构示例。支持台4可以包括多个吸取孔44。在该情况下,多个吸取孔44中的每一个连接至吸取单元45。例如,位于支持台4的中心部分中的至少一个吸取孔44可以吸取半导体芯片11B的中心部分,并且位于支持台4的外周部分中的至少一个吸取孔44可以吸取半导体芯片11B的外周部分。在图9和图10中示出的支持台4的结构示例中,吸取单元45被布置在支持台4的外部。然而,支持台4不限于图9和图10中示出的结构示例。吸取单元45可以被布置在支持台4的内部。从而,支持台4可以包括吸取单元45。
根据按照实施方式的半导体安装设备1,调整填充在隔膜23中的液体或气体的量,以使得隔膜23和弹性体24根据半导体芯片11A的背面16A的形状而变形。即,隔膜23和弹性体24在形状方面依据半导体芯片11A的背面16A的形状而变化。因此,弹性体24和半导体芯片11A的背面16A彼此紧密接触。作为结果,当头部2对半导体芯片11A执行加压处理时,可以对半导体芯片11A施加均匀的压力。
根据按照实施方式的半导体安装设备1,可以在半导体芯片11A的多个端子14A的上表面17A互相平行对齐的情况下对半导体芯片11A执行加压处理。因此,即使当在半导体芯片11A、端子14A和半导体芯片11A中分别存在厚度变化、高度变化和弯曲时,也可以将半导体芯片11A的多个端子14A中的全部端子接合至半导体芯片11B的多个端子14B。如上所述,根据按照实施方式的半导体安装设备1,可以通过使半导体芯片11A的多个端子14A的上表面17A互相平行对齐来消减半导体芯片11A的厚度变化、端子14A的高度变化以及半导体芯片11A的弯曲。
1 半导体安装设备
2 头部
3 临时放置台
4 支持台
5 结合工具
6 控制单元
11,11A,11B 半导体芯片
14A,14B 端子
21,31,43 支持单元
22,42 加热器
23 隔膜
24 弹性体
25,33,44 吸取孔
26,34,45 吸取单元
27 阀
28 供给单元
31,41 台体

Claims (12)

1.一种半导体安装设备,包括:
存储单元,其存储液体或者气体;
接触单元,其在所述存储单元充满所述液体或者所述气体时与半导体芯片相接触;以及
吸取单元,其吸取所述半导体芯片以使所述半导体芯片与所述接触单元紧密接触。
2.根据权利要求1所述的半导体安装设备,
其中,所述半导体芯片包括:多个端子;端子形成表面,在其上形成所述多个端子;以及相反表面,其位于所述端子形成表面的相反侧上,并且
在所述接触单元根据所述相反表面的形状而变形的情况下,所述相反表面与所述接触单元紧密接触。
3.根据权利要求2所述的半导体安装设备,
其中,所述接触单元按照所述相反表面变形成凹圆弧形或者凸圆弧形。
4.根据权利要求1至3中任一项所述的半导体安装设备,包括:
吸取单元,其从所述半导体芯片的形成有多个端子的端子形成表面侧吸取所述半导体芯片,以使所述多个端子的上表面互相平行对齐。
5.根据权利要求1至3中任一项所述的半导体安装设备,包括:
加热台,在其上安装有与所述半导体芯片相对的第二半导体芯片,并且所述加热台加热所述第二半导体芯片。
6.一种半导体安装设备的头部,包括:
存储单元,其存储液体或者气体;
接触单元,其在所述存储单元充满所述液体或者所述气体时与半导体芯片相接触;以及
吸取单元,其吸取所述半导体芯片以使所述半导体芯片与所述接触单元紧密接触。
7.根据权利要求6所述的半导体安装设备的头部,
其中,所述半导体芯片包括:多个端子;端子形成表面,在其上形成所述多个端子;以及相反表面,其位于所述端子形成表面的相反侧上,并且
在所述接触单元根据所述相反表面的形状而变形的情况下,所述相反表面与所述接触单元紧密接触。
8.根据权利要求7所述的半导体安装设备的头部,
其中,所述接触单元按照所述相反表面变形成凹圆弧形或者凸圆弧形。
9.一种用于制造叠层芯片的方法,包括:
在第一半导体芯片上布置头部,所述头部包括:存储单元,其存储液体或者气体;以及接触单元,其在所述存储单元充满所述液体或所述气体时与所述第一半导体芯片相接触;
用所述液体或所述气体来填充所述存储单元;
吸取所述第一半导体芯片以使所述第一半导体芯片与所述接触单元紧密接触;
在所述第一半导体芯片上布置第二半导体芯片,以便所述第一半导体芯片的多个第一端子与所述第二半导体芯片的多个第二端子面向彼此;以及
加热所述第二半导体芯片并且利用所述头部来对所述第一半导体芯片加压,以使所述多个第一端子与所述多个第二端子接合。
10.根据权利要求9所述的用于制造叠层芯片的方法,
其中,所述第一半导体芯片包括:端子形成表面,在其上形成所述多个第一端子;以及相反表面,其位于所述端子形成表面的相反侧上,并且在所述接触单元按照所述相反表面的形状而变形的情况下,所述相反表面与所述接触单元紧密接触。
11.根据权利要求10所述的用于制造叠层芯片的方法,
其中,所述接触单元按照所述相反表面变形成凹圆弧形或凸圆弧形。
12.根据权利要求9至11中任一项所述的用于制造叠层芯片的方法,包括:
在布置之前,从所述第一半导体芯片的形成有所述多个第一端子的端子形成表面侧吸取所述第一半导体芯片,以使所述多个第一端子的上表面互相平行对齐。
CN201611088242.6A 2015-12-28 2016-11-30 半导体安装设备及其头部以及用于制造叠层芯片的方法 Expired - Fee Related CN106922087B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2015-256807 2015-12-28
JP2015256807A JP6582975B2 (ja) 2015-12-28 2015-12-28 半導体実装装置、半導体実装装置のヘッド及び積層チップの製造方法

Publications (2)

Publication Number Publication Date
CN106922087A true CN106922087A (zh) 2017-07-04
CN106922087B CN106922087B (zh) 2019-08-09

Family

ID=59088457

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201611088242.6A Expired - Fee Related CN106922087B (zh) 2015-12-28 2016-11-30 半导体安装设备及其头部以及用于制造叠层芯片的方法

Country Status (5)

Country Link
US (1) US9905528B2 (zh)
JP (1) JP6582975B2 (zh)
KR (1) KR101877135B1 (zh)
CN (1) CN106922087B (zh)
TW (1) TWI644370B (zh)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN107106437B (zh) 2014-12-05 2020-12-04 宝洁公司 用于减少毛发卷曲的组合物
WO2017096156A1 (en) 2015-12-04 2017-06-08 The Procter & Gamble Company Composition for hair frizz reduction
DE112016007464B4 (de) * 2016-11-21 2021-06-24 Mitsubishi Electric Corporation Halbleitervorrichtung
US11062933B2 (en) * 2018-07-17 2021-07-13 Intel Corporation Die placement and coupling apparatus
JP2021090030A (ja) * 2019-12-06 2021-06-10 富士電機株式会社 半導体装置及び半導体装置の製造方法
WO2024062921A1 (ja) * 2022-09-20 2024-03-28 株式会社村田製作所 プレスヘッド、プレス装置、半導体製造装置、および電子部品製造装置
TWI841311B (zh) * 2023-03-22 2024-05-01 致伸科技股份有限公司 觸控板模組

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02158150A (ja) * 1988-12-12 1990-06-18 Toshiba Corp リードフォーミング装置
JP2002016108A (ja) * 2000-06-30 2002-01-18 Toshiba Corp 半導体装置及びその製造装置
KR20120054758A (ko) * 2010-11-22 2012-05-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 칩 이송 장치
TWI395253B (zh) * 2004-12-28 2013-05-01 Mitsumasa Koyanagi 使用自我組織化功能之積體電路裝置的製造方法及製造裝置

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3955659B2 (ja) * 1997-06-12 2007-08-08 リンテック株式会社 電子部品のダイボンディング方法およびそれに使用されるダイボンディング装置
JP4356137B2 (ja) 1999-05-19 2009-11-04 パナソニック株式会社 半導体装置の製造方法
JP3372511B2 (ja) * 1999-08-09 2003-02-04 ソニーケミカル株式会社 半導体素子の実装方法及び実装装置
JP2001230528A (ja) * 2000-02-15 2001-08-24 Sony Corp 実装装置及び実装方法
DE10147789B4 (de) * 2001-09-27 2004-04-15 Infineon Technologies Ag Vorrichtung zum Verlöten von Kontakten auf Halbleiterchips
EP1321966B8 (de) * 2001-12-21 2007-05-23 Oerlikon Assembly Equipment AG, Steinhausen Greifwerkzeug zum Montieren von Halbleiterchips
US6975016B2 (en) * 2002-02-06 2005-12-13 Intel Corporation Wafer bonding using a flexible bladder press and thinned wafers for three-dimensional (3D) wafer-to-wafer vertical stack integration, and application thereof
JP4233802B2 (ja) 2002-04-26 2009-03-04 東レエンジニアリング株式会社 実装方法および実装装置
JP2005322815A (ja) * 2004-05-11 2005-11-17 Matsushita Electric Ind Co Ltd 半導体製造装置および半導体装置の製造方法
JP4516354B2 (ja) * 2004-05-17 2010-08-04 パナソニック株式会社 部品供給方法
JP4616719B2 (ja) * 2005-07-20 2011-01-19 富士通株式会社 Icチップ実装方法
JP4750492B2 (ja) * 2005-07-20 2011-08-17 富士通株式会社 Icチップ実装方法
TWI463580B (zh) * 2007-06-19 2014-12-01 Renesas Electronics Corp Manufacturing method of semiconductor integrated circuit device
WO2009128206A1 (ja) * 2008-04-18 2009-10-22 パナソニック株式会社 フリップチップ実装方法とフリップチップ実装装置およびそれに使用されるツール保護シート
JP2009289959A (ja) * 2008-05-29 2009-12-10 Elpida Memory Inc ボンディング装置およびボンディング方法
JP2011066027A (ja) 2009-09-15 2011-03-31 Nec Corp 矯正キャップ
JP2012221989A (ja) * 2011-04-04 2012-11-12 Elpida Memory Inc 半導体装置製造装置、及び半導体装置の製造方法
KR101801264B1 (ko) * 2011-06-13 2017-11-27 삼성전자주식회사 반도체 제조 장치 및 이를 이용한 반도체 패키지 방법
JP2015018897A (ja) 2013-07-10 2015-01-29 マイクロン テクノロジー, インク. 半導体装置の製造方法
JP2015126035A (ja) * 2013-12-25 2015-07-06 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
DE102014117020A1 (de) * 2014-11-20 2016-05-25 Infineon Technologies Ag Verfahren zum herstellen einer stoffschlüssigen verbindung zwischen einem halbleiterchip und einer metallschicht

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02158150A (ja) * 1988-12-12 1990-06-18 Toshiba Corp リードフォーミング装置
JP2002016108A (ja) * 2000-06-30 2002-01-18 Toshiba Corp 半導体装置及びその製造装置
TWI395253B (zh) * 2004-12-28 2013-05-01 Mitsumasa Koyanagi 使用自我組織化功能之積體電路裝置的製造方法及製造裝置
KR20120054758A (ko) * 2010-11-22 2012-05-31 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제조용 칩 이송 장치

Also Published As

Publication number Publication date
JP2017120835A (ja) 2017-07-06
US20170186721A1 (en) 2017-06-29
JP6582975B2 (ja) 2019-10-02
TW201735194A (zh) 2017-10-01
KR101877135B1 (ko) 2018-07-10
CN106922087B (zh) 2019-08-09
TWI644370B (zh) 2018-12-11
KR20170077782A (ko) 2017-07-06
US9905528B2 (en) 2018-02-27

Similar Documents

Publication Publication Date Title
CN106922087B (zh) 半导体安装设备及其头部以及用于制造叠层芯片的方法
TWI652743B (zh) 半導體晶片的封裝裝置以及半導體裝置的製造方法
US8377745B2 (en) Method of forming a semiconductor device
CN109103117B (zh) 结合半导体芯片的设备和结合半导体芯片的方法
TWI670776B (zh) 半導體裝置的製造方法以及封裝裝置
JP6234277B2 (ja) 圧着ヘッド、それを用いた実装装置および実装方法
JP2008547205A5 (zh)
CN110024095B (zh) 半导体装置的制造方法以及封装装置
US6365435B1 (en) Method for producing a flip chip package
KR102087683B1 (ko) 반도체 장치의 제조 방법
TWI746888B (zh) 封裝裝置
CN111383953B (zh) 用于制造半导体装置的方法和系统
US20110115099A1 (en) Flip-chip underfill
JP5098939B2 (ja) ボンディング装置及びボンディング方法
JP7317354B2 (ja) 実装装置
JP3973615B2 (ja) 半導体装置の製造方法
JP2006229106A (ja) 半導体装置の実装方法と実装装置および半導体装置
JP2008034571A (ja) 半導体キャリア、装着ツール、半導体装置の製造方法、および半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20190809

Termination date: 20211130