TWI607514B - Semiconductor device manufacturing method - Google Patents

Semiconductor device manufacturing method Download PDF

Info

Publication number
TWI607514B
TWI607514B TW103123047A TW103123047A TWI607514B TW I607514 B TWI607514 B TW I607514B TW 103123047 A TW103123047 A TW 103123047A TW 103123047 A TW103123047 A TW 103123047A TW I607514 B TWI607514 B TW I607514B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
bump electrode
semiconductor
bump
semiconductor device
Prior art date
Application number
TW103123047A
Other languages
English (en)
Other versions
TW201519337A (zh
Inventor
Satoshi Tsukiyama
Masatoshi Fukuda
Yukifumi Oyama
Shinya Fukayama
Original Assignee
Toshiba Memory Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Memory Corp filed Critical Toshiba Memory Corp
Publication of TW201519337A publication Critical patent/TW201519337A/zh
Application granted granted Critical
Publication of TWI607514B publication Critical patent/TWI607514B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
    • H01L25/074—Stacked arrangements of non-apertured devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54473—Marks applied to semiconductor devices or parts for use after dicing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012—Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10122—Auxiliary members for bump connectors, e.g. spacers being formed on the semiconductor or solid-state body to be connected
    • H01L2224/10135—Alignment aids
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/11334—Manufacturing methods by local deposition of the material of the bump connector in solid form using preformed bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13012—Shape in top view
    • H01L2224/13014—Shape in top view being circular or elliptic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13075—Plural core members
    • H01L2224/1308—Plural core members being stacked
    • H01L2224/13082—Two-layer arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13155—Nickel [Ni] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/13164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/1319—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/1401—Structure
    • H01L2224/1403—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1412—Layout
    • H01L2224/1415—Mirror array, i.e. array having only a reflection symmetry, i.e. bilateral symmetry
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/145—Material
    • H01L2224/14505—Bump connectors having different materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1705—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1751—Function
    • H01L2224/17515—Bump connectors having different functions
    • H01L2224/17517—Bump connectors having different functions including bump connectors providing primarily mechanical support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81121—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors
    • H01L2224/8113—Active alignment, i.e. by apparatus steering, e.g. optical alignment using marks or sensors using marks formed on the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8112—Aligning
    • H01L2224/81136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H01L2224/81138—Aligning involving guiding structures, e.g. spacers or supporting members the guiding structures being at least partially left in the finished device
    • H01L2224/81139—Guiding structures on the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81193—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81194—Lateral distribution of the bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812—Applying energy for connecting
    • H01L2224/81201—Compression bonding
    • H01L2224/81203—Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/8185—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/81855—Hardening the adhesive by curing, i.e. thermosetting
    • H01L2224/81862—Heat curing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81905—Combinations of bonding methods provided for in at least two different groups from H01L2224/818 - H01L2224/81904
    • H01L2224/81907—Intermediate bonding, i.e. intermediate bonding step for temporarily bonding the semiconductor or solid-state body, followed by at least a further bonding step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06517—Bump or bump-like direct electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06568—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices decreasing in size, e.g. pyramidical stack
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

半導體裝置之製造方法 [相關申請案]
本申請案享有以日本專利申請案2013-230650號(申請日：2013年11月6日)作為基礎申請案之優先權。本申請案藉由參照該基礎申請案而包含基礎申請案之全部內容。
本發明之實施形態係關於一種半導體裝置之製造方法。
為了實現半導體裝置之小型化或高功能化，於1個封裝體內積層複數個半導體晶片並密封而成之SiP(System in Package，系統級封裝)構造之半導體裝置不斷被實用化。於SiP構造之半導體裝置中，要求高速地收發半導體晶片間之電信號。於此種情形時，半導體晶片間之電性連接係使用微凸塊。微凸塊具有例如5~50μm左右之直徑，且以10~100μm左右之間距藉由焊料而形成於半導體晶片之表面。
此種半導體裝置中，期望謀求抑制微凸塊之接合不良。
本發明之一個實施形態提供一種可抑制凸塊之接合不良之半導體裝置之製造方法。
根據本發明之一個實施形態，於第1半導體晶片之第1面形成第1凸塊電極，於第2半導體晶片之第2面形成第2凸塊電極與突起，以上述第1面與上述第2面對向之方式，使用上述突起將上述第1半導體晶片與上述第2半導體晶片固定，在高於上述第1凸塊電極與上述第2凸 塊電極中所含之金屬之至少一部分金屬之熔點之溫度環境下將上述第1半導體晶片與上述第2半導體晶片電性連接，於上述第1半導體晶片與上述第2半導體晶片之電性連接之後，在低於上述第1凸塊電極與上述第2凸塊電極中所含之金屬之熔點之溫度環境下使上述突起硬化。
2、21‧‧‧第1半導體晶片
2a‧‧‧第1面
3、22‧‧‧第2半導體晶片
3a‧‧‧第2面
5‧‧‧連接體(凸塊連接部)
5a‧‧‧第1凸塊電極
5b‧‧‧第2凸塊電極
6‧‧‧突起
7‧‧‧底部填充樹脂
8‧‧‧表面電極
10、30‧‧‧半導體裝置
11‧‧‧平台
12‧‧‧接合頭
20‧‧‧晶片積層體
23‧‧‧第3半導體晶片
31‧‧‧外部連接端子
32‧‧‧內部連接端子
33‧‧‧配線基板
36‧‧‧樹脂密封層
37‧‧‧第4半導體晶片
38‧‧‧第3凸塊電極
39‧‧‧第4凸塊電極
圖1係第1實施形態之半導體裝置之剖面圖。
圖2係沿圖1所示之A-A線之箭線剖面圖。
圖3係表示半導體裝置之製造步驟之流程圖。
圖4係表示半導體裝置之製造步驟之剖面圖。
圖5係表示半導體裝置之製造步驟之剖面圖。
圖6係表示圖1所示之半導體裝置之製造步驟之流程圖，且係表示作為比較例之製造步驟之流程圖。
圖7係第2實施形態之半導體裝置之剖面圖。
以下，參照隨附圖式對實施形態之半導體裝置進行詳細說明。再者，並非由該等實施形態限定本發明。例如，本實施形態之表示上下左右等方向之說明係指將圖式上之上方向設為上之情形時之相對方向。即，存在本實施形態中所示之方向與以重力加速度方向為基準之方向不同之情形。
(第1實施形態)
首先，對半導體裝置之構成進行說明。圖1係第1實施形態之半導體裝置之剖面圖。圖2係沿圖1所示之A-A線之箭線剖面圖。半導體裝置10包含第1半導體晶片2與第2半導體晶片3。第1半導體晶片2之上表面(第1面)2a具有第1連接區域，且於第1連接區域內形成有第1凸塊電極5a。第2半導體晶片3之下表面(第2面)3a具有與第1連接區域對向之第2連接區域，且於第2連接區域內形成有第2凸塊電極5b。具有第1 面2a之第1半導體晶片2、與具有第2面3a之第2半導體晶片3係以使第1面2a與第2面3a對向之方式積層。又，第2半導體晶片3使第2凸塊電極5b與第1凸塊電極5a連接，且積層於第1半導體晶片2上。即，第1半導體晶片2與第2半導體晶片3係經由第1凸塊電極5a與第2凸塊電極5b之連接體(凸塊連接部)5而電性及機械地連接。所謂連接區域，意指半導體晶片2、3之表面2a、3a上之第1凸塊電極5a、第2凸塊電極5b之形成區域。所謂第1凸塊電極5a、第2凸塊電極5b，意指形成將第1半導體晶片2與第2半導體晶片3電性及機械地連接之凸塊連接部之電極。
第1凸塊電極5a與第2凸塊電極5b中所使用之材料係例示焊料、金(Au)等。作為第1凸塊電極5a與第2凸塊電極5b之組合，可例示焊料/焊料、金(Au)/焊料、焊料/金(Au)、金(Au)/金(Au)等組合。作為形成第1凸塊電極5a與第2凸塊電極5b之焊料，可例示使用於錫(Sn)中添加有銅(Cu)、銀(Ag)、鉍(Bi)、銦(In)等之錫(Sn)合金的無鉛(Pb)焊料。作為無鉛(Pb)焊料之具體例，可列舉錫(Sn)-銅(Cu)合金、錫(Sn)-銀(Ag)合金、錫(Sn)-銀(Ag)-銅(Cu)合金等。形成第1凸塊電極5a與第2凸塊電極5b之金屬亦可代替金(Au)而使用銅(Cu)、鎳(Ni)、錫(Sn)、鈀(Pd)、銀(Ag)等。該等金屬並不限於單層膜，亦可使用複數層之金屬積層膜。作為第1凸塊電極5a、第2凸塊電極5b之形狀，可列舉半球狀或柱狀等突起形狀，但亦可為如焊墊之平坦形狀。作為第1凸塊電極5a與第2凸塊電極5b之組合，可列舉突起體彼此之組合、突起體與平坦體之組合等。此處，本實施形態係採取如下之例進行說明，即，對第1凸塊電極5a使用自第1半導體晶片2側起為鎳(Ni)與金(Au)之積層膜，對第2凸塊電極5b使用自第2半導體晶片3側起為鎳(Ni)與無鉛(Pb)焊料之積層膜。第1半導體晶片2與第2半導體晶片3係經由凸塊連接部5而電性連接。經由凸塊連接部5在第1半導體晶片2與第2半導體晶片3之間收發電信號。
於第1半導體晶片2之上表面2a上之除第1連接區域以外之區域(第1非連接區域)、及第2半導體晶片3之下表面3a上之除第2連接區域以外之區域(第2非連接區域)之至少一區域設置有突起6。突起6係由使用例如環氧樹脂、聚醯亞胺樹脂、丙烯酸系樹脂、酚系樹脂等之熱固性樹脂形成。突起6係以第1半導體晶片2與第2半導體晶片3之間之間隙(間距)成為所設定之凸塊電極5a、5b之連接高度(凸塊連接部5之設定高度)之方式設置。於壓接第1半導體晶片2與第2半導體晶片3時，其等之間隙(間距)由突起6界定，故而可抑制凸塊連接部5之過度壓扁或凸塊電極5a、5b間之連接不良(開路不良)等之產生。
突起6之前端與第1非連接區域及第2非連接區域之另一區域接著。突起6於將第1凸塊電極5a與第2凸塊電極5b連接時，強化第1半導體晶片2與第2半導體晶片3之連接狀態。於經由凸塊連接部5而連接之第1半導體晶片2之第1面2a與第2半導體晶片3之第2面3a之間隙填充有底部填充樹脂7。藉由在第1半導體晶片2之第1非連接區域與第2半導體晶片3之第2非連接區域之間設置突起6，可提高填充底部填充樹脂7之前之第1半導體晶片2與第2半導體晶片3之連接強度。即，第1半導體晶片2與第2半導體晶片3於填充底部填充樹脂7之前，除了藉由第1凸塊電極5a與第2凸塊電極5b之凸塊連接部5連接以外，亦藉由突起6而連接。因此，可提高填充底部填充樹脂7之前之連接強度。
設置於第1半導體晶片2之第1凸塊電極5a與設置於第2半導體晶片3之第2凸塊電極5b係藉由例如一面加熱一面進行壓接而連接。於半導體晶片2、3之表面設置有如聚醯亞胺樹脂膜之未圖示之有機絕緣膜(絕緣膜)作為通常保護膜。構成半導體晶片2、3之矽基板之熱膨脹係數為3ppm左右，相對於此，聚醯亞胺樹脂之熱膨脹係數較大為35ppm左右。因此，於半導體晶片2、3易產生翹曲，尤其是有半導體晶片2、3之厚度變得越薄則翹曲量變得越大之傾向。此處，藉由突起6 強化與半導體晶片2、3之連接狀態，可抑制於將凸塊電極5a、5b連接時、或連接之後因半導體晶片2、3之翹曲而導致凸塊電極5a、5b之凸塊連接部5破斷之情況。
突起6係於半導體晶片2、3間局部地設置。因此，可提高第1半導體晶片2與第2半導體晶片3之位置對準精度或第1凸塊電極5a與第2凸塊電極5b之連接性。例如於將如NCF(Non Conductive Film，非導電性膜)之兼具接著功能與密封功能之絕緣樹脂層配置於半導體晶片間之整個間隙之方法中，於將第1半導體晶片2與第2半導體晶片3位置對準時，對準標記之檢測精度會下降。凸塊電極5a、5b之間距變得越窄，越要求更進一步提高位置對準精度。將突起6以不覆蓋對準標記之方式局部地設置而提高對準標記之檢測精度，藉此可使半導體晶片2、3間之位置對準精度提昇。
配置於半導體晶片2、3間之整個間隙之絕緣樹脂層有進入至第1凸塊電極5a與第2凸塊電極5b之間而使連接性下降之虞，相對於此，局部地設置之突起6由於不會進入至凸塊電極5a、5b間，故而不存在使凸塊電極5a、5b間之連接性下降之虞。因此，可使第1凸塊電極5a與第2凸塊電極5b之連接性提昇。進而，於存在配置於半導體晶片2、3間之整個間隙之絕緣樹脂層之情形時，在半導體晶片2、3間之連接時或接著時易產生夾帶空隙。產生於連接區域之空隙會產生凸塊連接部5未被樹脂覆蓋之狀態之情況，故而有於電極間產生短路之虞。於本實施形態中，使用突起6提高半導體晶片2、3間之連接強度，並且將凸塊電極5a、5b間連接，且於其上填充有底部填充樹脂7。因此，可以凸塊連接部5確實地被覆蓋之狀態密封，而可提高可靠性。
其次，對半導體裝置10之製造步驟進行說明。圖3係表示半導體裝置10之製造步驟之流程圖。圖4係表示半導體裝置10之製造步驟之剖面圖。圖5係表示半導體裝置10之製造步驟之剖面圖。
首先，於第1半導體晶片2之第1面2a形成第1凸塊電極5a，於第2半導體晶片3之第2面3a形成第2凸塊電極5b(步驟S1)。第1凸塊電極5a係形成於第1面2a之表面所形成之表面電極8上。第2凸塊電極5b係形成於第2面3a之表面所形成之表面電極8上。表面電極8電性連接於形成於半導體晶片之貫通電極或內部配線。表面電極8係形成於在使第1半導體晶片2與第2半導體晶片3積層時相互對向之位置。表面電極8使用例如銅(Cu)、鋁(Al)、鎳(Ni)、金(Au)等。該等金屬並不限於單層膜，亦可使用複數層金屬積層膜。亦可省略第1凸塊電極5a、第2凸塊電極5b中之其中一者。
其次，於第2半導體晶片3之第2面3a形成突起6(步驟S2)。突起6係形成於第2半導體晶片3之第2面3a上之第2非連接區域。於本實施形態中，使突起6以柱狀體之形式散佈於第2面3a之非連接區域全域。再者，突起6亦可形成於第1半導體晶片2之第1面2a，或亦可形成於第1面2a與第2面3a之兩者。突起6較佳為設置於與第1凸塊電極5a或第2凸塊電極5b相隔之位置。突起6較佳為由使用例如環氧樹脂、聚醯亞胺樹脂、丙烯酸系樹脂、酚系樹脂等之熱固性樹脂形成。突起6可應用微影技術或者藉由分配器或噴墨之塗佈技術而形成，或者可藉由膜之接著而形成。於塗佈液狀之熱固性樹脂組成物而形成突起6之情形時，較佳為預先設為半硬化狀態。或者，較佳為使用速硬化型之材料縮短半導體晶片2、3之接著、連接時之時間。
其次，進行積層第1半導體晶片2與第2半導體晶片3之積層步驟(步驟S3)。此處，使第1面2a與第2面3a對向，且將第1半導體晶片2與第2半導體晶片3以重疊之狀態暫時固定。如圖4、5所示，將吸附保持於接合頭12之第2半導體晶片3配置於載置在平台11上之第1半導體晶片2。第1半導體晶片2與第2半導體晶片3之位置對準係例如藉由省略圖示之相機等檢測第1及第2半導體晶片2、3之對準標記而進行。再 者，只要以不覆蓋第1面2a或第2面3a之整體而散佈之方式形成突起6即可，故而可於避開對準標記之位置形成突起6。若於避開對準標記之位置形成突起6，則變得易於容易且確實地進行對準標記之檢測。
又，以小於等於第1凸塊電極5a或第2凸塊電極5b中所使用之金屬之熔點、且可使突起6顯現接著性之溫度環境下及時間，進行步驟S3之步驟，藉此第1半導體晶片2與第2半導體晶片3由突起6暫時固定。例如，藉由在150℃之環境下進行1秒之壓接，而利用突起6將第1半導體晶片2與第2半導體晶片3暫時固定。再者，於以下之說明中，將被暫時固定之第1半導體晶片2與第2半導體晶片3亦統稱為晶片積層體。
繼而，進行回焊步驟，使形成於第1面2a與第2面3a之第1凸塊電極5a或第2凸塊電極5b中所含之金屬之至少一部分熔融，而使其等相互接合(步驟S4)。例如，將晶片積層體配置於回焊爐內。例如，於回焊爐內，將大於等於第2凸塊電極5b中所使用之無鉛(Pb)焊料之熔點即250℃設為峰值溫度。繼而，將晶片積層體在回焊爐內於峰值溫度下配置60秒。此處，為了去除第1凸塊電極5a及第2凸塊電極5b之表面氧化膜並且使第1凸塊電極5a與第2凸塊電極5b接合，而例如將回焊爐內設為還原氣氛。藉由利用回焊步驟將第1凸塊電極5a與第2凸塊電極5b接合，而使第1半導體晶片2與第2半導體晶片3經由凸塊連接部5電性連接。
繼而，進行使利用熱固性樹脂之突起6硬化之固化步驟(步驟S5)。例如，將晶片積層體於小於等於第1凸塊電極5a或第2凸塊電極5b中所含之金屬之熔點(於本實施形態之例中為小於等於第1凸塊電極5a或第2凸塊電極5b中所含之金屬中之熔點最低之無鉛(Pb)焊料之熔點)、且熱固性樹脂之硬化進行之180℃之環境下配置2小時。藉由使突起6硬化，而將第1半導體晶片2與第2半導體晶片3較暫時固定之狀態更牢固地固定。
繼而，向第1半導體晶片2之第1面2a與第2半導體晶片3之第2面3a之間填充底部填充樹脂7(步驟S6)。其後，使所填充之底部填充樹脂7硬化(步驟S7)。藉由以上步驟而製造半導體裝置10。此處雖省略了圖示，但半導體裝置1係搭載於具有外部連接端子之配線基板或引線框架等電路基材上而用作SiP構造之半導體裝置等。半導體裝置1與電路基材之連接係藉由覆晶接合或打線接合等而實施。
本實施形態之半導體裝置10於回焊步驟(S4)之前之階段中，藉由突起6將第1半導體晶片2與第2半導體晶片3暫時固定，故而可抑制回焊後之半導體晶片2、3之翹曲。因此，可抑制因半導體晶片2、3之翹曲而導致第1凸塊電極5a與第2凸塊電極5b之凸塊連接部5於底部填充樹脂7之填充前破斷。
又，突起6係以散佈於半導體晶片2、3之第1面2a或第2面3a之方式設置，故而與在第1面2a或第2面3a之整體設置有突起6之情形相比，變得不易產生夾帶空隙。藉此，可謀求半導體裝置10之可靠性之提昇。又，由於底部填充樹脂7之填充步驟(S6)與底部填充樹脂7之硬化步驟(S7)較固化步驟(S5)更靠後，故而可降低底部填充樹脂7滲透至突起6而使突起6膨脹之可能性。突起6之膨脹會導致凸塊連接部5之破斷。根據本實施形態之半導體裝置10，藉由抑制突起6之膨脹，可抑制凸塊連接部5之破斷。
再者，亦可使用具有感光性及熱固性之樹脂形成突起6。作為感光性及熱固性樹脂之具體例，可列舉如感光性接著劑樹脂之含有感光劑之熱固性樹脂。藉由感光性及熱固性樹脂，可於突起6之形成階段，使用光微影技術使突起6以柱狀體之形式散佈於第2面3a之非連接區域全域。進而，由於在後續之成為步驟(S5)之加熱時進行熱硬化，故而可將第1半導體晶片2與第2半導體晶片3更牢固地固定。
圖6係表示圖1所示之半導體裝置之製造步驟之流程圖，且係表 示作為比較例之製造步驟之流程圖。於作為比較例之製造步驟中，在步驟S14中進行固化步驟後，於步驟S15中進行回焊步驟，固化步驟與回焊步驟之順序與本實施形態之製造步驟相反。除此以外之步驟與本實施形態之製造步驟相同。於作為比較例之製造步驟中，藉由在固化步驟中使突起6硬化，而於實現半導體晶片2、3彼此之固定後，於回焊步驟中使第1凸塊電極5a或第2凸塊電極5b中所含之金屬之至少一部分熔融，從而謀求第1凸塊電極5a與第2凸塊電極5b之接合。
此處，有時於半導體晶片2、3之表面設置如聚醯亞胺樹脂膜之有機絕緣膜(絕緣膜)作為保護膜。因構成半導體晶片2、3之矽基板之熱膨脹係數與聚醯亞胺樹脂之熱膨脹係數之差異，而導致於半導體晶片2、3易產生翹曲。尤其是有半導體晶片2、3之厚度變得越薄則翹曲量變得越大之傾向。於半導體晶片2、3之積層步驟(S3)中，由平台11與接合頭12夾入，藉此半導體晶片2、3之翹曲被矯正，但若自平台11與接合頭12之間取出晶片積層體，則於半導體晶片2、3易於再次產生翹曲。於作為比較例之製造步驟中，利用固化步驟(S14)謀求半導體晶片2、3彼此之固定，藉此抑制於半導體晶片2、3再次產生翹曲。
然而，於作為比較例之製造步驟中，存在介存於第1凸塊電極5a與表面電極8之間之鎳或構成表面電極8之銅擴散至第1凸塊電極5a中所使用之無鉛(Pb)焊料內之情形。若鎳或銅等異種金屬擴散至無鉛(Pb)焊料內，則無鉛(Pb)焊料之熔點會上升。於無鉛(Pb)焊料之熔點上升之情形時，若不使回焊步驟(S15)之溫度升高則可能會產生凸塊連接部5之連接不良。另一方面，若使回焊步驟(S15)之溫度升高，則有可能殘留應力會相應地變大。
相對於此，本實施形態之製造步驟係如圖3所示般，於步驟S4中進行回焊步驟，於步驟S5中進行固化步驟。即，在固化步驟之前進行回焊步驟。藉此，可抑制鎳(Ni)或銅(Cu)等異種金屬之擴散，從而可 謀求同時降低凸塊連接部5之連接不良之可能性及降低殘留應力。
又，於本實施形態之製造步驟中，由於在積層步驟中藉由突起6將第1半導體晶片2與第2半導體晶片3暫時固定，故而於半導體晶片2、3不易再次產生翹曲。因此，即便於固化步驟之前進行回焊步驟，亦可抑制因半導體晶片2、3之翹曲而導致凸塊連接部5破斷之情況。
圖7係第2實施形態之半導體裝置30之剖面圖。半導體裝置30包括第1半導體晶片21、第2半導體晶片22、第3半導體晶片23、及第4半導體晶片37。對第1半導體晶片21、第2半導體晶片22、及第3半導體晶片23可使用例如NAND(Not-AND，與非)快閃記憶體。又，對第4半導體晶片37可使用例如NAND控制器。第1半導體晶片21、第2半導體晶片22及第3半導體晶片23成為使用與第1實施形態相同之方法積層所得之晶片積層體20之構成之一部分。半導體裝置30係搭載於包含外部連接端子31與內部連接端子32之配線基板33上。第3半導體晶片23經由第3凸塊電極38與第4半導體晶片37電性連接。配線基板33之內部連接端子32經由設置於第4半導體晶片37之表面電極8及第4凸塊電極39而與第4半導體晶片37電性連接。於配線基板33上形成有將晶片積層體20與第4半導體晶片37等一併密封之樹脂密封層36。
2‧‧‧第1半導體晶片
2a‧‧‧第1面
3‧‧‧第2半導體晶片
3a‧‧‧第2面
5‧‧‧連接體(凸塊連接部)
5a‧‧‧第1凸塊電極
5b‧‧‧第2凸塊電極
6‧‧‧突起
7‧‧‧底部填充樹脂
8‧‧‧表面電極
10‧‧‧半導體裝置

Claims (7)

  1. 一種半導體裝置之製造方法，其係於第1半導體晶片之第1面形成第1凸塊電極；於第2半導體晶片之第2面形成第2凸塊電極與包含熱固化性樹脂之突起；藉由將上述突起熱壓接於上述第1面，以上述第1面與上述第2面對向之方式，使用上述突起將上述第1半導體晶片與上述第2半導體晶片固定；上述固定後，在高於上述第1凸塊電極與上述第2凸塊電極中所含之金屬之至少一部分金屬之熔點之溫度環境下將上述第1半導體晶片與上述第2半導體晶片電性連接；且於上述第1半導體晶片與上述第2半導體晶片之電性連接之後，在低於上述第1凸塊電極與上述第2凸塊電極中所含之金屬之熔點之溫度環境下使上述突起中所含之熱固化性樹脂硬化。
  2. 如請求項1之半導體裝置之製造方法，其包括使上述突起硬化之後，向上述第1面與上述第2面之間填充底部填充樹脂，其後使上述底部填充樹脂硬化之步驟。
  3. 如請求項1或2之半導體裝置之製造方法，其中上述突起係相對於上述第2面以複數個散佈之方式形成。
  4. 如請求項3之半導體裝置之製造方法，其中上述突起係包含柱狀體之形狀。
  5. 如請求項1或2之半導體裝置之製造方法，其中上述突起係在低於上述第1凸塊電極與上述第2凸塊電極中所含之金屬之熔點之溫度環境下熱壓接於上述第1面。
  6. 如請求項5之半導體裝置之製造方法，其中上述突起係包含柱狀 體之形狀。
  7. 如請求項1或2之半導體裝置之製造方法，其中對上述第1半導體晶片與上述第2半導體晶片進行壓接，而將上述第1半導體晶片與上述第2半導體晶片固定。
TW103123047A 2013-11-06 2014-07-03 Semiconductor device manufacturing method TWI607514B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2013230650A JP6189181B2 (ja) 2013-11-06 2013-11-06 半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201519337A TW201519337A (zh) 2015-05-16
TWI607514B true TWI607514B (zh) 2017-12-01

Family

ID=53006439

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103123047A TWI607514B (zh) 2013-11-06 2014-07-03 Semiconductor device manufacturing method

Country Status (4)

Country Link
US (1) US9570414B2 (zh)
JP (1) JP6189181B2 (zh)
CN (1) CN104637826B (zh)
TW (1) TWI607514B (zh)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5876000B2 (ja) * 2012-06-11 2016-03-02 株式会社新川 ボンディング装置およびボンディング方法
JP6479577B2 (ja) 2015-05-29 2019-03-06 東芝メモリ株式会社 半導体装置
KR20160142943A (ko) * 2015-06-03 2016-12-14 한국전자통신연구원 반도체 패키지 및 반도체 패키지의 제조 방법
JP6608640B2 (ja) * 2015-07-28 2019-11-20 新光電気工業株式会社 実装構造体の製造方法
US9837432B2 (en) * 2015-09-09 2017-12-05 Toshiba Memory Corporation Semiconductor memory device
JP6515047B2 (ja) * 2016-03-11 2019-05-15 東芝メモリ株式会社 半導体装置及びその製造方法
CN110462836B (zh) 2017-09-19 2024-01-05 谷歌有限责任公司 作为用于芯片间精确分离的挡块的柱
CN109949703B (zh) * 2019-03-26 2021-08-06 京东方科技集团股份有限公司 柔性显示基板、显示面板、显示装置及制作方法
EP3909078A4 (en) 2019-06-27 2022-12-21 Yangtze Memory Technologies Co., Ltd. MARKING PATTERN IN THREE-DIMENSIONAL MEMORY DEVICE STAIR STRUCTURE FORMING
JP7293056B2 (ja) * 2019-09-12 2023-06-19 キオクシア株式会社 半導体装置およびその製造方法
JP2021129084A (ja) 2020-02-17 2021-09-02 キオクシア株式会社 半導体装置およびその製造方法
CN113223999A (zh) * 2021-04-01 2021-08-06 光华临港工程应用技术研发(上海)有限公司 晶圆键合方法及晶圆键合结构
CN115810620A (zh) * 2021-09-14 2023-03-17 中兴通讯股份有限公司 堆叠封装结构及其封装方法和移动终端设备

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201301464A (zh) * 2011-05-26 2013-01-01 Toshiba Kk 層積型半導體裝置及其製造方法
US20130154076A1 (en) * 2010-09-14 2013-06-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect

Family Cites Families (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06236981A (ja) 1993-02-10 1994-08-23 Fujitsu Ltd 固体撮像素子
JPH07183332A (ja) * 1993-12-22 1995-07-21 Oki Electric Ind Co Ltd 電子部品の半田バンプ実装方法
JP2845847B2 (ja) 1996-11-12 1999-01-13 九州日本電気株式会社 半導体集積回路
JP2001189347A (ja) * 2000-01-05 2001-07-10 Seiko Epson Corp 半導体装置及びその製造方法、並びに電子装置
JP2001298102A (ja) * 2000-04-13 2001-10-26 Nec Corp 機能素子の実装構造およびその製造方法
US7242099B2 (en) * 2001-03-05 2007-07-10 Megica Corporation Chip package with multiple chips connected by bumps
JP2003188210A (ja) * 2001-12-18 2003-07-04 Mitsubishi Electric Corp 半導体装置
JP3914431B2 (ja) 2001-12-26 2007-05-16 松下電器産業株式会社 半導体装置の製造方法
JP3810359B2 (ja) 2002-09-19 2006-08-16 松下電器産業株式会社 半導体装置及びその製造方法
JP4509486B2 (ja) * 2003-03-18 2010-07-21 セイコーエプソン株式会社 半導体装置の製造方法、半導体装置、及び電子機器
US8294279B2 (en) * 2005-01-25 2012-10-23 Megica Corporation Chip package with dam bar restricting flow of underfill
JP4752586B2 (ja) 2006-04-12 2011-08-17 ソニー株式会社 半導体装置の製造方法
JP5017930B2 (ja) * 2006-06-01 2012-09-05 富士通株式会社 半導体装置、はんだバンプ接続用基板の製造方法及び半導体装置の製造方法
JP5311336B2 (ja) 2008-11-28 2013-10-09 セイコーインスツル株式会社 サーマルヘッド、サーマルプリンタ及びサーマルヘッドの製造方法
JP5115524B2 (ja) * 2009-07-08 2013-01-09 パナソニック株式会社 電子部品ユニット及び補強用接着剤
TW201330217A (zh) * 2011-11-11 2013-07-16 Sumitomo Bakelite Co 半導體裝置之製造方法
CN104221480B (zh) * 2012-04-19 2017-09-08 松下知识产权经营株式会社 电子零件安装方法及电子零件安装线

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20130154076A1 (en) * 2010-09-14 2013-06-20 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Leadframe Interposer Over Semiconductor Die and TSV Substrate for Vertical Electrical Interconnect
TW201301464A (zh) * 2011-05-26 2013-01-01 Toshiba Kk 層積型半導體裝置及其製造方法

Also Published As

Publication number Publication date
US9570414B2 (en) 2017-02-14
JP2015090937A (ja) 2015-05-11
CN104637826A (zh) 2015-05-20
JP6189181B2 (ja) 2017-08-30
US20150123270A1 (en) 2015-05-07
CN104637826B (zh) 2018-02-09
TW201519337A (zh) 2015-05-16

Similar Documents

Publication Publication Date Title
TWI607514B (zh) Semiconductor device manufacturing method
JP5814859B2 (ja) 半導体装置とその製造方法
TWI483376B (zh) Semiconductor device and manufacturing method thereof
US8575763B2 (en) Semiconductor device and method of manufacturing the same
JP5847749B2 (ja) 積層型半導体装置の製造方法
US20150214207A1 (en) Chip stack, semiconductor devices having the same, and manufacturing methods for chip stack
US10121774B2 (en) Method of manufacturing a semiconductor package
US8710642B2 (en) Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus
WO2010047006A1 (ja) 半導体装置およびその製造方法
TWI587415B (zh) 半導體裝置之製造方法
CN111095508A (zh) 半导体元件的安装构造以及半导体元件与基板的组合
KR20120058118A (ko) 적층 패키지의 제조 방법, 및 이에 의하여 제조된 적층 패키지의 실장 방법
JP2013021058A (ja) 半導体装置の製造方法
TWI688067B (zh) 半導體裝置及其製造方法
US20130277828A1 (en) Methods and Apparatus for bump-on-trace Chip Packaging
US10854576B2 (en) Semiconductor device and manufacturing method thereof
TW201507097A (zh) 半導體晶片及具有半導體晶片之半導體裝置
JP4703356B2 (ja) 積層型半導体装置
JP2013157363A (ja) 積層型半導体装置
US8703533B2 (en) Semiconductor package and method for manufacturing the same
JP2008300498A (ja) 電子部品内蔵基板とこれを用いた電子機器、およびその製造方法
TW202245559A (zh) 複合配線基板、半導體裝置及複合配線基板的製造方法
JP2014029929A (ja) 半導体装置
JP2008218941A (ja) 電子回路装置とこれを用いた電子機器、およびその製造方法