CN110476236B - 安装装置以及安装系统 - Google Patents
安装装置以及安装系统 Download PDFInfo
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- CN110476236B CN110476236B CN201880020250.8A CN201880020250A CN110476236B CN 110476236 B CN110476236 B CN 110476236B CN 201880020250 A CN201880020250 A CN 201880020250A CN 110476236 B CN110476236 B CN 110476236B
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- 239000004065 semiconductor Substances 0.000 claims abstract description 114
- 238000002788 crimping Methods 0.000 claims abstract description 58
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 230000017525 heat dissipation Effects 0.000 claims abstract description 35
- 238000010438 heat treatment Methods 0.000 claims abstract description 10
- 239000003507 refrigerant Substances 0.000 claims description 6
- 230000005489 elastic deformation Effects 0.000 claims description 3
- 230000006835 compression Effects 0.000 description 30
- 238000007906 compression Methods 0.000 description 30
- 238000000034 method Methods 0.000 description 21
- 230000005855 radiation Effects 0.000 description 18
- 238000010586 diagram Methods 0.000 description 17
- 238000012546 transfer Methods 0.000 description 14
- 238000003825 pressing Methods 0.000 description 10
- 238000001816 cooling Methods 0.000 description 9
- 238000002844 melting Methods 0.000 description 6
- 230000008018 melting Effects 0.000 description 6
- 239000011347 resin Substances 0.000 description 5
- 229920005989 resin Polymers 0.000 description 5
- 238000003466 welding Methods 0.000 description 5
- 230000006870 function Effects 0.000 description 4
- 238000005259 measurement Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 239000012530 fluid Substances 0.000 description 3
- 238000012545 processing Methods 0.000 description 3
- 238000004458 analytical method Methods 0.000 description 2
- 230000003247 decreasing effect Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 239000000155 melt Substances 0.000 description 2
- 239000007787 solid Substances 0.000 description 2
- 229920001187 thermosetting polymer Polymers 0.000 description 2
- 239000004925 Acrylic resin Substances 0.000 description 1
- 229920000178 Acrylic resin Polymers 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004695 Polyether sulfone Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000004100 electronic packaging Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000002427 irreversible effect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 239000013034 phenoxy resin Substances 0.000 description 1
- 229920006287 phenoxy resin Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006393 polyether sulfone Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 230000004044 response Effects 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
- H01L24/75—Apparatus for connecting with bump connectors or layer connectors
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67121—Apparatus for making assemblies not otherwise provided for, e.g. package constructions
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- H01L24/92—Specific sequence of method steps
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0652—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
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- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/07—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L29/00
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- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K13/00—Apparatus or processes specially adapted for manufacturing or adjusting assemblages of electric components
- H05K13/04—Mounting of components, e.g. of leadless components
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- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Abstract
本发明提供一种在基板上的多个部位层叠并安装两个以上的半导体芯片的安装装置及安装系统,安装装置包括:第一安装头,在所述基板上的多个部位,形成以暂时压接状态将两个以上的半导体芯片层叠的暂时层叠体;以及第二安装头(126),将形成于所述多个部位的所述暂时层叠体依序正式压接而形成芯片层叠体。第二安装头(126)包括:压接工具(130),通过将对象的暂时层叠体的上表面一边加热一边加压,而一次性地将构成所述暂时层叠体的两个以上的半导体芯片正式压接;以及一个以上的散热工具(132),具有散热体,散热体通过与位于所述对象的暂时层叠体的周边的其他层叠体的上表面接触而使其他层叠体散热。
Description
技术领域
本发明涉及一种在基板上的多个部位层叠并安装两个以上的半导体芯片的安装装置以及安装系统。
背景技术
以前,要求半导体装置的进一步的高功能化、小型化。因此,一部分提出层叠并安装多个半导体芯片。通常,在半导体芯片的单面设置着凸块(bump)、及覆盖所述凸块的非导电性膜(Non-conductive Film)(以下称作“NCF”)。NCF包含热硬化性树脂,若小于规定的硬化开始温度,则伴随温度上升而可逆地软化,但若超过硬化开始温度,则伴随温度上升而不可逆地硬化。提出有为了将所述半导体芯片层叠安装,将多个半导体芯片一边暂时压接一边层叠,然后,对所述暂时压接状态的层叠体进行加热加压而进行正式压接。另外,以下,将暂时压接状态的层叠体称作“暂时层叠体”,正式压接后的层叠体称作“芯片层叠体”。而且,在无须区分暂时层叠体及芯片层叠体的情况下,可简称作“层叠体”。根据此种技术,能够以小面积安装更多个半导体芯片,因此能够实现进一步的高功能化、小型化。
现有技术文献
非专利文献
非专利文献1:Noboru Asahi(朝日升)及另一名,“Heat Transfer Analysis inthe Thermal compression Bonding for CoW Process(对于晶片上芯片热加压接合的热传递分析)”,电子封装技术国际会议(International Conference on ElectronicsPackaging,ICEP)2016会议记录(Proceedings),p.640-643
发明内容
发明所要解决的问题
且说,一般而言,在一个基板上安装着多个芯片层叠体。一部分提出如下技术,在安装多个芯片层叠体的情况下,在形成了多个暂时层叠体后,将所述多个暂时层叠体依序正式压接。根据所述技术,与一个层叠体的暂时压接及正式压接完成后进行下一个层叠体的暂时压接及正式压接的情况相比,可减少暂时压接处理与正式压接处理的切换次数,因此能够实现安装步骤的进一步的简易化、缩短化。
另一方面,在形成了多个暂时层叠体后进行正式压接的技术的情况下,为了正式压接,附加至一个暂时层叠体的热有时也会传递至周边的其他暂时层叠体。尤其在基板的导热率高的情况下,附加至一个暂时层叠体的正式压接用的热会高效率地传递至周边的其他暂时层叠体,而导致其他暂时层叠体的温度上升。所述情况下,有在其他暂时层叠体中产生NCF的不可逆的硬化之虞。若在正式压接之前产生NCF的硬化,则会妨碍所述半导体芯片与基板的适当的接合。
此处,非专利文献1中提出如下技术:在对一个半导体芯片正式压接时,向其周边的其他半导体芯片吹送冷却风,由此防止所述其他半导体芯片的温度上升,进而,防止NCF的硬化。然而,在利用冷却风进行冷却的情况下,存在不仅冷却效率差,也难以限制冷却范围的问题。结果,冷却风的一部分不仅吹到冷却对象的其他半导体芯片,也吹到位于其附近的正在进行正式压接的半导体芯片,从而有所述正在进行正式压接的半导体芯片的温度降低,而导致安装不良之虞。
因此,本发明的目的在于提供如下的安装装置以及安装系统,即,在形成多个暂时的芯片层叠体后在将这些暂时的芯片层叠体依序正式压接的情况下,可更适当地安装各半导体芯片。
解决问题的技术手段
本发明的安装装置在基板上的多个部位层叠并安装两个以上的半导体芯片,包括:暂时压接头,在所述基板上的多个部位,形成以暂时压接状态将两个以上的半导体芯片层叠的暂时层叠体;以及正式压接头,将形成于所述多个部位的所述暂时层叠体依序正式压接而形成芯片层叠体,所述正式压接头包括:压接工具,通过将对象的暂时层叠体的上表面一边加热一边加压,而一次性地将构成所述暂时层叠体的两个以上的半导体芯片正式压接;以及一个以上的散热工具,具有散热体,所述散热体通过与位于所述对象的暂时层叠体的周边的其他层叠体的上表面接触而使所述其他层叠体散热。
根据所述构成,正式压接时,可利用针点(pin point)将位于其周边的其他层叠体冷却,因此可防止正式压接的层叠体的温度降低,且可防止正式压接前的层叠体中的NCF的硬化。
而且,所述正式压接头可进而包括供所述压接工具及所述散热工具安装的基部,通过所述基部升降,所述压接工具及散热工具联动地升降。
根据所述构成,因可一体地控制压接工具与散热工具的升降,故可使控制简化。
而且,所述情况下,所述散热工具也可经由弹性体而安装于所述基部,可在所述弹性体的弹性变形量的范围内相对于所述基部升降。
通过设为所述构成,因可利用弹性体吸收层叠体的高度的不均,故可使一个以上的散热工具确实地与层叠体接触。
而且,所述情况下,无负载状态下的所述散热工具的底面高度可低于所述压接工具的底面高度。
若设为所述构成,则通过降低可吸收层叠体的高度的不均的散热工具,而可使散热工具及压接工具的双方确实地与层叠体接触。
而且,所述散热体可通过冷媒而冷却。
通过设为所述构成,可更有效果地将位于周边的其他层叠体冷却。
而且,所述正式压接头可具有一个所述压接工具、及8个所述散热工具,所述压接工具与所述散热工具以所述压接工具为中心配设成3行3列。
通过设为所述构成,可将正式压接的层叠体的整个周围的层叠体冷却。
本发明的安装系统在基板上的多个部位层叠并安装两个以上的半导体芯片,包括:暂时压接装置,在所述基板上的多个部位,形成以暂时压接状态将两个以上的半导体芯片层叠的暂时层叠体;以及正式压接装置,通过所述暂时压接装置将形成于所述多个部位的所述暂时层叠体依序正式压接而形成芯片层叠体,所述正式压接装置包括:压接工具,通过将对象的暂时层叠体的上表面一边加热一边加压,而一次性地将构成所述暂时层叠体的两个以上的半导体芯片正式压接;以及一个以上的散热工具,具有散热体,所述散热体通过与位于所述对象的暂时层叠体的周边的其他层叠体的上表面接触而使所述其他层叠体散热。
发明的效果
根据本发明,在进行正式压接时,可利用针点将位于其周边的其他层叠体冷却,因此可防止正式压接的层叠体的温度降低,且可防止正式压接前的层叠体中的NCF的硬化。
附图说明
图1是表示作为本发明的实施方式的安装装置的构成的图。
图2是表示基板的一例的图。
图3是表示半导体芯片的构成的图。
图4是表示半导体装置的构成的图。
图5是表示现有技术中的正式压接的情况的图。
图6是表示第二安装头的构成的图。
图7是表示自底面侧观察第二安装头的图。
图8是表示本实施方式中的正式压接的情况的图。
图9是表示实验条件的图。
图10是表示条件1、条件2中的测定结果的图。
图11是表示条件3、条件4中的测定结果的图。
图12是表示正式压接的进行顺序的一例的图。
图13是表示另一第二安装头的一例的图。
符号的说明
10:半导体芯片
14、16:电极端子
18:凸块
30:基板
34:配置区域
100:安装装置
102:芯片供给单元
104:芯片搬送单元
106:接合单元
110:突起部
114:裸片捡取器
116:移送头
118:旋转台
120:载台
124:第一安装头
126:第二安装头
128:控制单元
130:压接工具
131:加热器
132:散热工具
134:散热体
136:柱体
138:弹性体
139d、139u:凸缘
140:基部
具体实施方式
以下,参照附图对本发明的实施方式进行说明。图1是作为本发明的实施方式的安装装置100的概略构成图。所述安装装置100是在基板30上安装半导体芯片10的装置。所述安装装置100设为尤其适合于层叠并安装多个半导体芯片10的情况的构成。另外,以下的说明中,将层叠多个半导体芯片10而成者称作“层叠体ST”,进而将所述“层叠体ST”中的多个半导体芯片10为暂时压接状态者称作“暂时层叠体STt”,将多个半导体芯片10为正式压接状态者称作“芯片层叠体STc”而加以区分。
安装装置100具备芯片供给单元102、芯片搬送单元104、接合单元106及控制这些的驱动的控制单元128。芯片供给单元102是自芯片供给源取出半导体芯片10并供给至芯片搬送单元104的部位。所述芯片供给单元102具备突起部110及裸片捡取器(die picker)114及移送头116。
芯片供给单元102中,多个半导体芯片10载置于切割胶带(dicing tape)TE上。此时半导体芯片10将凸块18以朝向上侧的面朝上(face up)状态载置。突起部110仅使所述多个半导体芯片10中的一个半导体芯片10保持面朝上状态而向上方突起。裸片捡取器114利用其下端对因突起部110而突起的半导体芯片10进行抽吸保持并接收。已接收半导体芯片10的裸片捡取器114以所述半导体芯片10的凸块18朝向下方的方式,亦即,以半导体芯片10为面朝下(face down)的状态的方式,当场旋转180度。若成为所述状态,则移送头116自裸片捡取器114接收半导体芯片10。
移送头116能够在上下方向及水平方向上移动,可利用其下端吸附保持半导体芯片10。若裸片捡取器114旋转180度,半导体芯片10成为面朝下状态,则移送头116利用其下端吸附保持所述半导体芯片10。然后,移送头116在水平方向及上下方向上移动,向芯片搬送单元104移动。
芯片搬送单元104具有以铅垂的旋转轴Ra为中心而旋转的旋转台118。移送头116将半导体芯片10载置于旋转台118的规定位置。通过载置半导体芯片10的旋转台118以旋转轴Ra为中心旋转,而所述半导体芯片10被搬送至位于芯片供给单元102的相反侧的接合单元106。
接合单元106具备对支持基板30的载台120或半导体芯片10进行暂时压接的第一安装头124(暂时压接头)、及对半导体芯片10进行正式压接的第二安装头126(正式压接头)等。载台120能够在水平方向上移动,对所载置的基板30与安装头124、安装头126的相对位置关系进行调整。而且,所述载台120中内置加热器,可自下侧加热半导体芯片10。
第一安装头124可在其下端保持半导体芯片10,而且,能够进行绕铅垂的旋转轴Rb的旋转、及升降。而且,第一安装头124中内置加热器(未图示),被加热至规定的第一温度T1。第一安装头124作为将半导体芯片10暂时压接至基板或其他半导体芯片10上的暂时压接头发挥功能。
第二安装头126能够升降。而且,第二安装头126中内置加热器(未图示),被加热至高于第一温度T1的第二温度T2。第二安装头126作为正式压接头发挥功能,所述正式压接头通过将经暂时压接的半导体芯片10以第二温度T2一边加热一边加压,而将这些半导体芯片10正式压接。此处,本实施方式的第二安装头126除具有与对象的半导体芯片10(更准确地说暂时层叠体STt)接触而进行加热、加压的一个压接工具130之外,进而具有配置于所述压接工具130的周围的多个散热工具132。关于所述压接工具130或散热工具132的具体构成将在以后进行详细说明。
在第一安装头124、第二安装头126的附近设置着相机(未图示)。对基板30及半导体芯片10分别附上成为定位基准的对准标记。相机对基板30及半导体芯片10进行摄像以使得所述对准标记映出。控制单元128基于所述摄像所获得的图像数据,而掌握基板30及半导体芯片10的相对位置关系,且视需要对第一安装头124的绕轴Rb的旋转角度及载台120的水平位置进行调整。控制单元128控制各单元的驱动,例如具备进行各种运算的中央处理器(Central Processing Unit,CPU)、记忆各种数据或程序的记忆部。
接下来,对利用所述安装装置100制造的半导体装置进行说明。本实施方式中,使用半导体晶片作为基板30,在所述半导体晶片(基板30)上层叠安装多个半导体芯片10。因此,本实施方式的安装工艺是在半导体晶片的电路形成面,层叠安装半导体芯片10的“晶片上芯片(chip on wafer)工艺”。图2是本实施方式中使用的基板30(半导体晶片)的概略概念图。作为半导体晶片的基板30主要包含硅,与包含树脂或玻璃的普通的电路基板相比,热传递系数高。如图2所示,在基板30设定着呈格子状并列的多个配置区域34。各配置区域34层叠安装着多个半导体芯片10。配置区域34以规定的配置间距P配设。所述配置间距P的值可根据安装对象的半导体芯片10的尺寸等而适当设定。而且,本实施方式中,将配置区域34设为大致正方形,但也可适当地设为其他形状,例如大致长方形。
接下来,对半导体芯片10的构成进行简单说明。图3是表示所安装的半导体芯片10的概略构成的图。在半导体芯片10的上下表面形成着电极端子14、电极端子16。而且,在半导体芯片10的单面,与电极端子14相连而形成着凸块18。凸块18包含导电性金属,以规定的熔融温度Tm而熔融。
而且,在半导体芯片10的单面,以覆盖凸块18的方式贴附着非导电性膜(以下称作“NCF”)20。NCF 20作为将半导体芯片10与基板30或其他半导体芯片10粘接的粘接剂而发挥功能,包含非导电性的热硬化性树脂,例如聚酰亚胺树脂、环氧树脂、丙烯酸系树脂、苯氧树脂、聚醚砜树脂等。所述NCF 20的厚度大于凸块18的平均高度,凸块18由所述NCF 20大致完全覆盖。NCF 20在常温下为固体的膜,但若超过规定的软化开始温度Ts,则会逐渐可逆地软化而发挥流动性,若超过规定的硬化开始温度Tt,则会不可逆地开始硬化。
此处,软化开始温度Ts低于凸块18的熔融温度Tm及硬化开始温度Tt。暂时压接用的第一温度T1高于所述软化开始温度Ts,且低于熔融温度Tm及硬化开始温度Tt。而且,正式压接用的第二温度T2高于熔融温度Tm及硬化开始温度Tt。亦即,Ts<T1<(Tm、Tt)<T2。
在将半导体芯片10暂时压接至基板30或下侧的半导体芯片10(以下称作“下层的芯片等”)时,将第一安装头124加热至第一温度T1后将半导体芯片10压抵至下层的芯片等而进行加压。此时,半导体芯片10的NCF 20通过利用来自第一安装头124的传热被加热至软化开始温度Ts以上而软化,从而具有流动性。而且,由此,NCF 20流入至半导体芯片10与下层的芯片等的间隙,从而可确实地填埋所述间隙。
在将半导体芯片10正式压接时,将第二安装头126加热至第二温度T2后,对半导体芯片10进行加压。此时,半导体芯片10的凸块18及NCF 20利用来自第二安装头126的传热而被加热至硬化开始温度Tt及熔融温度Tm以上。由此,凸块18熔融,可熔接至相向的下层的芯片等。而且,利用所述加热,NCF 20以填埋半导体芯片10与下层的芯片等的间隙的状态硬化,因此将半导体芯片10与下层牢固地固定。
图4是表示在基板30上的电极32层叠安装多个半导体芯片10的半导体装置的构成的图。半导体装置在多个配置区域34(图示例中为区域A~区域C)分别配置着层叠安装有目标层叠数的半导体芯片10的芯片层叠体STc。本实施方式中,将目标层叠数设为“4”,在一个配置区域34安装着包含4个半导体芯片10的芯片层叠体STc。
此种半导体装置按照如下的顺序制造。首先,使用第一安装头124,形成多个一边暂时压接半导体芯片10一边层叠而成的暂时层叠体STt。图4的例中,只要可在区域A形成暂时层叠体STt,则继而在区域B形成暂时层叠体STt,进而,然后在区域C形成暂时层叠体STt。
只要可在全部的配置区域34形成暂时层叠体STt,则接下来将所述暂时层叠体STt依序正式压接。亦即,使用已加热至第二温度T2的第二安装头126,将对象的暂时层叠体STt的上表面一边加热一边加压,一次性地对构成所述对象的暂时层叠体STt的多个(本例中4个)半导体芯片10进行正式压接。由此,暂时层叠体STt变为将构成其的半导体芯片10正式压接而成的芯片层叠体STc。只要可正式压接一个暂时层叠体STt(只要变为芯片层叠体STc),则继而会对下一个暂时层叠体STt进行正式压接。然后,只要可将全部的暂时层叠体STt正式压接,则制造工艺结束。
如此,在形成了多个暂时层叠体STt后进行正式压接的方法的情况下,与形成一个暂时层叠体STt后进行正式压接的方法相比,可减少安装头的切换次数等,因此可减少安装处理整体的处理时间。另一方面,在形成了多个暂时层叠体STt后进行正式压接的方法的情况下,存在如下问题,即,在成为正式压接的对象的暂时层叠体STt以外的暂时层叠体STt中,NCF 20不可逆地硬化。关于所述情况将参照图5进行说明。图5是表示现有技术中的正式压接的情况的概念图。
如已述那样,在将一个暂时层叠体STt正式压接而变为芯片层叠体STc的情况下,利用正式压接用的安装头对所述暂时层叠体STt的上表面一边加热一边加压。现有的安装装置中,如图5所示,正式压接用的安装头仅具有对暂时层叠体STt一边加热一边加压的压接工具130,而不具有使周边的暂时层叠体STt散热的散热工具132。
考虑如下情况:使用此种现有的安装装置在区域A、区域B、区域C中形成了暂时层叠体STt后,对正中的区域B的暂时层叠体STt进行正式压接。所述情况下,使用压接工具130对区域B的暂时层叠体STt一边加热一边加压。此时,关于压接工具130的温度即第二温度T2,被设定为最下层的半导体芯片10要高于NCF 20的硬化开始温度Tt及凸块18的熔融温度Tm。而且,通过以所述第二温度T2加热,对象的暂时层叠体STt(图5中的区域B的暂时层叠体STt)的凸块18熔融,而且,NCF 20不可逆地开始硬化。
此处,自压接工具130赋予的热如图5中粗线箭头所示那样,不仅传递至作为正式压接对象的区域B的暂时层叠体STt,也经由基板30传递至邻接的区域A或区域C的暂时层叠体STt。尤其,在如基板30为半导体晶片那样导热性高的情况下,在邻接的暂时层叠体STt中,热被高效率地传递。结果,并非为正式压接对象的邻接的暂时层叠体STt也会被加热至NCF 20的硬化开始温度Tt以上,从而有在正式压接前这些区域A、区域C的暂时层叠体STt的NCF 20不可逆地硬化之虞。若正式压接前NCF 20硬化,则会导致半导体芯片10的安装不良。而且,也充分考虑在未加热至硬化开始温度Tt以上的情况下,NCF 20所含的硬化剂的反应也会开始,所述情况下,难以获得NCF20本来的特性。
因此,本实施方式中,为了防止正式压接对象的暂时层叠体STt以外的其他暂时层叠体STt的NCF 20的硬化,在第二安装头126不仅设置压接工具130,也设置散热工具132。关于所述情况将参照图6、图7进行说明。图6是表示第二安装头126的概略构成的图。而且,图7是自底侧观察第二安装头126的图。
第二安装头126具备基部140、及安装于所述基部140的压接工具130及散热工具132。基部140安装于未图示的升降机构,根据来自控制单元128的指示而升降。
压接工具130压抵至正式压接对象的暂时层叠体STt的上表面,由此,对所述暂时层叠体STt一边加压一边加热。所述压接工具130在内部设置着加热器131,加热至规定的第二温度T2。压接工具130的上端固接于基部140,从而压接工具130对基部140的位置不变。
以压接工具130为中心而向其周围的八个方向设置着散热工具132。图7中,中空的四边形表示散热工具132,附影线的四边形表示压接工具130。如所述图7所示,第二安装头126具有一个压接工具130及八个散热工具132,这些工具以一个压接工具130为中心而呈3行3列排列。压接工具130及散热工具132的配置间距Q与层叠体ST的配置间距P相同。因此,压接工具130与一个层叠体ST接触时,与所述压接工具130邻接的散热工具132会与和一个层叠体ST邻接的其他层叠体ST接触。
散热工具132使正式压接对象以外的其他层叠体ST散热而冷却。所述散热工具132的下端设置着散热体134。散热体134是导热率高的材料,例如是包含铜或铝等的块状构件。所述散热体134作为散热器(heat sink)发挥功能,所述散热器与位于作为正式压接对象的暂时层叠体STt的周围的其他层叠体ST的上表面接触,使所述其他层叠体ST的热释放。自其他层叠体ST传递至散热体134的热向外部气体或后述的柱体136等放出。
另外,图6中,是将散热体134设为单纯的长方体形状,但散热体134的形状也可适当变更。例如,为了提高散热体134的散热效率,也可在所述散热体134的上表面或侧面设置多个翼片(fin)或肋(rib)、突起。而且,为了提高散热体134的冷却性能,也可使用冷媒将所述散热体134冷却。亦即,也可设置与散热体134的内外连通的冷媒路径,使液体或气体的冷媒在所述冷媒路径循环。而且,作为其他形态,也可使用热管等将散热体134的热移送至散热体的外部。而且,作为另一形态,也可使用帕耳帖(Peltier)元件等将散热体134冷却。任一情况下,散热体134的底面,亦即,与层叠体ST的接触面理想的是平面,以能够与层叠体ST的整个上表面接触。另外,为了防止压接工具130的温度降低,理想的是在压接工具130与散热工具132之间设置某些隔热构件(未图示)。
散热体134经由弹性体138而安装于基部140,可在所述弹性体138的弹性变形量的范围内,相对于基部140升降。关于经由所述弹性体138的安装方法可考虑各种方法,本实施方式中,如图6所示,向贯通基部140的贯通孔中插通柱体136,并且在所述柱体136中的隔着基部140的两侧设置着直径比贯通孔大的凸缘139u、凸缘139d。而且,在基部140的底面与下侧的凸缘139d之间配置作为弹性体138的压缩弹簧。压缩弹簧在无负载状态下,将下侧的凸缘139d,进而将散热体134向下方施压。另一方面,在散热体134受到向上的力作为所述散热体134按压层叠体ST时的反作用力的情况下,压缩弹簧压缩变形,由此散热体134向靠近基部140的方向移位。
如此,散热工具132经由弹性体138安装于基部140,由此可吸收每个层叠体ST的高度的差,八个散热体134可全部密接于对应的层叠体ST的上表面。另外,为了使散热体134确实地密接于对应的层叠体ST,无负载状态(无弹性体的变形的状态)下的散热体134的底面高度理想的是低于压接工具130的底面高度(离开基部140)。而且,弹性体138理想的是其弹簧常数被调整,以使得在作为暂时压接用的荷重的第一荷重F1以下能够弹性变形。
接下来,参照图8对使用此种第二安装头126的正式压接进行说明。图8是表示使用本实施方式的第二安装头126进行正式压接的情况的概念图。图8的例中,在区域A~区域C形成暂时层叠体STt后,将正中的区域B的暂时层叠体STt正式压接。所述情况下,使压接工具130下降,压抵至作为正式压接对象的区域B的暂时层叠体STt的上表面。由此,区域B的暂时层叠体STt一边被加热一边被加压。若为了使压接工具130下降,而使基部140下降,则当然安装于所述基部140的散热工具132也与基部140及压接工具130联动地下降。而且,由此,散热工具132与和正式压接对象的暂时层叠体STt邻接的区域A、区域C的暂时层叠体STt的上表面接触。
因此,通常,在多个暂时层叠体STt产生若干的高度的不均。例如,图8的例中,区域A的暂时层叠体STt高于其他暂时层叠体STt。所述情况下,在散热工具132对基部140的位置不变的情况下,亦即,未设置弹性体138的情况下,存在如下问题:在区域A,散热工具132与暂时层叠体STt接触后,区域B、区域C中,压接工具130、散热工具132无法与对应的暂时层叠体STt接触。本实施方式中,各散热工具132经由弹性体138而安装于基部140,能够相对于基部140移位。因此,一个散热工具132与暂时层叠体STt接触后,若使基部140继续下降,所述一个散热工具132的弹性体138变形,容许其他散热工具132、压接工具130的进一步的下降。结果,散热工具132及多个压接工具130可确实地与对应的层叠体ST接触。另外,此时,若弹性体138的弹簧常数大,则弹性体138变形时过大的力施加至区域A的暂时层叠体STt。因此,弹性体138的弹簧常数以其变形所需的荷重为用以暂时压接的荷重F1以下的方式调整。
如此,本实施方式中,在对区域B的暂时层叠体STt进行正式压接时,使散热工具132与和所述区域B邻接的区域A、区域C的暂时层叠体STt接触。所述情况下,压接工具130的热如图8中粗线箭头所示,经由区域B的暂时层叠体STt及基板30而传递至区域A、区域C的暂时层叠体STt。然而,本实施方式中,传热性优异的散热体134与所述区域A、区域C的暂时层叠体STt的上表面接触。已传递至区域A、区域C的暂时层叠体STt的热在向所述散热体134放出后,向外部放出。结果,作为非正式压接对象的区域A、区域C的暂时层叠体STt的温度上升得以有效率地抑制。而且,由此,可防止区域A、区域C的暂时层叠体STt的NCF 20在正式压接前硬化,从而可有效果地防止半导体芯片10的安装不良。
此处,作为层叠体ST的冷却方法,如本实施方式那样,除使高传热性的固体(散热体134)接触的方法之外,也考虑使冷风或液体等流体直接吹到层叠体ST的方法。然而,此种流体难以限制其适用范围,从而有甚至会将本来不欲冷却的正式压接对象的暂时层叠体STt冷却之虞。若正式压接对象的暂时层叠体STt被冷却,则NCF 20会硬化不充分,或凸块18会熔融不充分,仍然有导致安装不良之虞。另一方面,根据使散热体134接触而散热的本实施方式的技术,可确实地仅将欲冷却的层叠体ST冷却,可抑制欲加热的暂时层叠体STt的温度降低。结果,根据本实施方式,可有效果地防止温度不足引起的安装不良或正式压接前的NCF 20硬化引起的安装不良。
接下来,对关于散热体134达成的冷却效果的实验结果进行说明。图9是表示实验条件的图。而且,图10、图11是表示实验结果的图。实验中,使用压接工具130对一个半导体芯片10进行加热加压。然后,测定此时的半导体芯片10的底面的温度TC1、及与所述一个半导体芯片10邻接设置的层叠体ST的最下层的底面温度TC2及最上层的底面温度TC3。条件1及条件2在使用树脂基板作为基板30的方面共通,但条件1中未使用散热工具132,与此相对,条件2中,使用散热工具132将层叠体ST冷却,就所述方面而言不同。条件3及条件4在使用玻璃基板作为基板30的方面共通,但条件3中,未使用散热工具132,与此相对,条件4中,使用散热工具132将层叠体ST冷却,就所述方面而言不同。
图10中的中空条表示条件1中的各测定温度TC1~TC3,涂黑条表示条件2中的各测定温度TC1~TC3。而且,图11中的中空条表示条件3中的各测定温度TC1~TC3,涂黑条表示条件4中的各测定温度TC1~TC3。如根据图10、图11可知,利用压接工具130加热的半导体芯片10的温度TC1在条件1、条件3(中空条)及条件2、条件4(涂黑条)中无较大差异,即便有散热工具132,对正式压接的不良影响也少。另一方面,在使用散热工具132的条件2、条件4(涂黑条)中,与未使用散热工具132的条件1、条件3(中空条)相比,邻接的层叠体ST的温度TC2、温度TC3降低。即,根据使用散热工具132的本实施方式,可知能够抑制与正式压接对象的层叠体ST邻接的层叠体ST的温度上升,所述邻接的层叠体ST即便在正式压接前,也可有效果地防止NCF 20的硬化等。另一方面,即便使用散热工具132,也可防止正式压接对象的半导体芯片10的温度降低,因此可确实地将各半导体芯片10正式压接。
另外,至此说明的构成为一例,只要正式压接用的安装头(第二安装头126)具备将暂时层叠体STt加热加压的压接工具130、及使与所述暂时层叠体STt邻接的其他层叠体ST散热的散热工具132,则其他构成也可适当变更。例如,本实施方式中,设为压接工具130与散热工具132一体地升降的构成,但压接工具130与散热工具132也可彼此独立地升降。
而且,本实施方式中,将散热工具132设置于压接工具130的周围八个方向,但不必设置于八个方向。例如,使暂时层叠体STt的正式压接如图12的箭头A'所示,考虑针对各行交替重复地进行向右方向依序前进的步骤与向左方向依序前进的步骤的情况。所述情况下,在较正式压接的暂时层叠体STt靠附图下侧处无层叠体ST,或者,即便有层叠体ST,正式压接已完成。所述情况下,在较压接工具130靠附图下侧处不需要散热工具132。因此,所述情况下,如图13所示,也可仅在压接工具130的左右两侧及附图上侧的三个部位的合计五处设置散热工具132。
而且,压接工具130与散热工具132的配设间隔也可根据配置区域的配置间距P而适当变更。而且,本实施方式中,分别设置着暂时压接用的安装头(第一安装头124)与正式压接用的安装头(第二安装头126),也可利用一个安装头进行暂时压接及正式压接。亦即,也可无第一安装头124,利用第二安装头126进行暂时压接及正式压接。此处,暂时压接时,不需要散热工具132,因此执行暂时压接时,也可自第二安装头126卸除散热工具132。
而且,至此为止的说明中,是在单个装置内设置暂时压接用的安装头(第一安装头124)及正式压接用的安装头(第二安装头126),但这些也可分别设置于不同的装置。亦即,本申请中公开的技术可应用于如下安装系统中,即,包括具备暂时压接用的安装头的暂时压接装置、及具备正式压接用的安装头的正式压接装置。
Claims (8)
1.一种安装装置,在基板上的多个部位层叠并安装两个以上的半导体芯片,其特征在于,包括:
暂时压接头,在所述基板上的多个部位,形成以暂时压接状态将所述两个以上的半导体芯片层叠的暂时层叠体;以及
正式压接头,将形成于所述多个部位的所述暂时层叠体依序正式压接而形成芯片层叠体;并且
所述正式压接头包括:
压接工具,通过将对象的所述暂时层叠体的上表面一边加热一边加压,而一次性地将构成所述暂时层叠体的两个以上的半导体芯片正式压接;以及
至少五个以上的散热工具,具有散热体,所述散热体通过与位于所述对象的暂时层叠体的周边的其他层叠体的上表面接触而使所述其他层叠体散热,
所述压接工具与所述散热工具配设成3行2列,所述压接工具配设于其中一列的中心。
2.根据权利要求1所述的安装装置,其中,
所述正式压接头进而包括供所述压接工具及所述散热工具安装的基部,
通过所述基部升降,所述压接工具及所述散热工具联动地升降。
3.根据权利要求2所述的安装装置,其特征在于,
所述散热工具经由弹性体而安装于所述基部,可在所述弹性体的弹性变形量的范围内相对于所述基部升降。
4.根据权利要求3所述的安装装置,其特征在于,
无负载状态下的所述散热工具的底面高度低于所述压接工具的底面高度。
5.根据权利要求1至4中任一项所述的安装装置,其特征在于,
所述散热体通过冷媒而冷却。
6.根据权利要求1至4中任一项所述的安装装置,其特征在于,
所述正式压接头具有一个所述压接工具、及8个所述散热工具,
所述压接工具与所述散热工具以所述压接工具为中心配设成3行3列。
7.根据权利要求5所述的安装装置,其特征在于,
所述正式压接头具有一个所述压接工具、及8个所述散热工具,
所述压接工具与所述散热工具以所述压接工具为中心配设成3行3列。
8.一种安装系统,在基板上的多个部位层叠并安装两个以上的半导体芯片,其特征在于,包括:
暂时压接装置,在所述基板上的多个部位,形成以暂时压接状态将所述两个以上的半导体芯片层叠的暂时层叠体;以及
正式压接装置,通过所述暂时压接装置将形成于所述多个部位的所述暂时层叠体依序正式压接而形成芯片层叠体;并且
所述正式压接装置包括:
压接工具,通过将对象的暂时层叠体的上表面一边加热一边加压,而一次性地将构成所述暂时层叠体的两个以上的半导体芯片正式压接;以及
至少五个以上的散热工具,具有散热体,所述散热体通过与位于所述对象的暂时层叠体的周边的其他层叠体的上表面接触而使所述其他层叠体散热,
所述压接工具与所述散热工具配设成3行2列,所述压接工具配设于其中一列的中心。
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