CN101866862A - 半导体集成电路器件的制造方法 - Google Patents

半导体集成电路器件的制造方法 Download PDF

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Publication number
CN101866862A
CN101866862A CN201010155938A CN201010155938A CN101866862A CN 101866862 A CN101866862 A CN 101866862A CN 201010155938 A CN201010155938 A CN 201010155938A CN 201010155938 A CN201010155938 A CN 201010155938A CN 101866862 A CN101866862 A CN 101866862A
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manufacture method
semiconductor device
die
stacks
chip
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CN201010155938A
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牧浩
伊势诚
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Renesas Electronics Corp
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Renesas Electronics Corp
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Publication of CN101866862A publication Critical patent/CN101866862A/zh
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Abstract

本发明涉及一种半导体集成电路器件的制造方法。尽管在管芯键合中在半导体芯片的背表面上提供有粘附剂层，但是层叠处理(主压力键合)需要在管芯键合过程(临时压力键合)之后确保粘附剂层的粘附状态。在这种情况下，通常是通过在加热的同时利用增压部件从上到下按压芯片的背面来进行粘附剂的硬化。显然，由于芯片变得较薄，在通过这种机械增压方法来层叠芯片的层叠处理中，存在各种问题。也即，问题包括悬垂状态下芯片的部分损坏、由弯曲和不均匀增压导致的芯片位置偏移等。本发明是在衬底产品的管芯键合过程中，在对电路衬底上的多个半导体芯片进行层叠和临时压力键合之后，通过静态气压来执行层叠处理。

Description

半导体集成电路器件的制造方法
相关申请的交叉引用
在此通过引用并入提交于2009年4月9日的日本专利申请号2009-94517的全部内容，包括其说明书、附图和摘要。
技术领域
本发明涉及有效地应用于半导体集成电路器件(或称半导体器件)的制造方法中的管芯键合技术的技术。
背景技术
日本专利公开号2009-27054(专利文献1)公开了一种倒装芯片键合方法，其通过在具有半导体芯片的块电极的器件表面上方提供粘附膜的状态中、以及在芯片被键合到布线衬底上从而使器件表面朝向布线衬底主表面的状态下，施加静态气压和加热来固化粘附膜。
发明内容
近来，在诸如存储器器件和SIP(系统级封装)产品等半导体器件中，在多层有机布线衬底(所谓的“衬底产品”)的器件安装表面上的矩阵中，提供有器件区域(单位器件区域)。继而，采用了在每个器件区域中将半导体芯片层叠和管芯键合为类似台阶的形状(例如，2到16层)的方法，以便实现较高的集成。
在这种管芯键合中，尽管在半导体芯片的背面提供有诸如DAF(管芯附接膜)的粘附剂层，但是在上述管芯键合过程或者随后的过程中，需要确保粘附剂层的粘附状态。这是因为，下层中的小空隙可能影响上层，从而产生大空隙，这将导致压力键合失败，最终导致回流断裂。因此，需要执行临时压力键合，并继而执行层叠处理(主压力键合)以抑制空隙。在这种情况下，通常加热芯片，同时利用增压部件从上向下挤压芯片，从而增进粘附剂的硬化。
然而，根据本申请发明人的分析，通过这种机械增压方法，由于芯片在层叠芯片的层叠处理中变得较薄，显然会出现各种问题。也即，问题包括：芯片在悬垂状态中的部分损坏、由弯曲和不均匀增压导致的芯片位置偏移等。此外，还存在另一问题，即压力没有有效地作用，并且无法在没有上层芯片的情况下对下层芯片执行安全的层叠处理。在仅执行键合的情况下，类似地，无法对悬垂状态中的芯片施加大压力。此外，需要抑制由夹头吸附孔导致的空隙。
本发明已经实现了解决这些问题。
本发明是根据上述情况进行的，其提供用于高质量半导体集成电路器件的制造工艺。
通过本说明书的描述以及附图，本发明的其他目的和新特征将变得易见。
下文简要阐释了本申请中公开的发明的典型发明的要点。
也即，本申请的一个发明是：在衬底产品的管芯键合过程中，在对电路衬底上的多个半导体芯片进行层叠和临时压力键合之后，通过静态气压来执行层叠处理。
下文简要阐释了通过本申请中公开的发明中的典型发明所取得的效果。
也即，由于层叠处理是在衬底产品的管芯键合过程中对电路衬底上的多个半导体芯片进行层叠和临时压力键合之后通过静态气压来执行的，因此可以施加均匀的压力，即使顶层芯片和下层芯片彼此偏移地被键合也是如此。
附图说明
图1是示出在本申请实施方式中的半导体集成电路器件制造方法中的整体组装过程的流程的工艺流程图；
图2是示出作为本申请实施方式中的半导体集成电路器件制造方法的重要部分的管芯键合过程的细节的工艺流程图；
图3是本申请实施方式中的半导体集成电路器件制造方法中所使用的管芯键合器的示意性前视图；
图4是示出图3的管芯键合器中的管芯键合头的底部部分中提供的吸附夹头的结构的剖面图；
图5是图3的管芯键合器的静态压力施加部分(主热压键合部分)的侧剖面图；
图6是图3的管芯键合器的静态压力施加部分(主要热压键合部分)中的静态压力施加舱(层叠处理舱)的外围的前剖面图；
图7是示出图2的主压力键合处理(层叠处理)的工艺序列的示例的详细工艺序列图；
图8是示出图3的管芯键合器中的芯片分离部分的晶片级(芯片分离级)上的分离过程的器件和设备示意性剖面流程图(吸附夹头就位以用于剥离)；
图9是示出图3的管芯键合器中的芯片分离部分的晶片级(芯片分离级)上的分离过程的器件和设备的示意性剖面流程图(分离完成)；
图10是示出图3的管芯键合器中的临时压力键合部分的临时压力键合级上的临时压力键合过程的器件和设备的示意性剖面流程图(吸附夹头下降以用于管芯键合)；
图11是示出图3的管芯键合器中的临时压力键合部分的临时压力键合级上的临时压力键合过程的器件和设备的示意性剖面流程图(吸附夹头就位以用于管芯键合)；
图12是示出图3的管芯键合器中的临时压力键合部分的临时压力键合级上的临时压力键合过程的电路衬底的顶视图(当芯片被层叠和固定在第一器件区域中时)；
图13是示出图3的管芯键合器中的临时压力键合部分的临时压力键合级上的临时压力键合过程的电路衬底的顶视图(当芯片被层叠和固定在所有器件区域中时)；
图14是图13中每个器件区域的放大视图(省略了电路衬底上的图案)；
图15是示出图3的管芯键合器中的临时压力键合部分的临时压力键合级上的临时压力键合过程的器件和设备的示意性剖面流程图(当针对第一层叠单元完成了芯片层叠之后)；
图16是图15之后的器件和设备的示意性剖面流程图(在针对第一层叠单元的芯片层叠之后完成了布线键合)，其示出了布线键合器中的布线键合级上的布线键合过程；
图17是图16之后的器件的示意性剖面流程图，其示出了利用树脂密封设备中的树脂来密封的状态；
图18是在更多步的层叠情况下与图15相对应的器件和设备的示意性剖面流程图(当针对第二层叠单元完成了芯片层叠时)；
图19是在更多步的层叠情况下与图16相对应的器件和设备的示意性剖面流程图(当在针对第二层叠单元的芯片层叠之后完成了布线键合时)；以及
图20是在更多步的层叠的情况下对应于图17的器件和设备的示意性剖面流程图(树脂密封)。
具体实施方式
[实施方式概述]
首先，将描述在本申请中公开的代表性实施方式。
1.一种半导体集成电路器件的制造方法，包括步骤：(a)将电路衬底引入管芯键合设备，所述电路衬底在其第一主表面上具有多个器件区域；(b)在管芯键合设备中，将多个芯片层叠体固定在每个器件区域中，每个芯片层叠体具有在其上层中的半导体芯片以及后侧上的粘附剂层，从而将芯片层叠体层叠在彼此偏移的相应位置中；以及(c)在步骤(b)之后，在管芯键合设备中，在将每个芯片层叠体加热到第一温度的状态下，在每个芯片层叠体的暴露表面上施加均匀的静态气压。
2.按照段落1的半导体集成电路的制造方法，进一步包括步骤：(d)在步骤(b)之后、步骤(c)之前，在管芯键合设备中，在芯片层叠体温度处于低于第一温度的第一温度范围的状态下，在每个芯片层叠体的暴露表面上施加均匀的静态气压。
3.按照段落1或者段落2的半导体集成电路器件的制造方法，其中所述粘附剂层是DAF。
4.按照段落1到3中任一段落的半导体集成电路器件的制造方法，其中，在将芯片层叠体置于单个密封舱的状态下，执行步骤(c)。
5.按照段落2到4中任一段落的半导体集成电路器件的制造方法，其中，在将芯片层叠体置于单个密封舱的状态下，执行步骤(d)。
6.按照段落5的半导体集成电路器件的制造方法，其中，在将芯片层叠体置于与步骤(c)相同的密封舱的状态下，执行步骤(d)。
7.按照段落1到3中任一段落的半导体集成电路器件的制造方法，其中，在将芯片层叠体与电路衬底一起置于单个密封舱的状态下，执行步骤(c)。
8.按照段落1到3中任一段落的半导体集成电路器件的制造方法，其中，在将芯片层叠体与电路衬底一起置于单个密封舱的状态下，执行步骤(d)。
9.按照段落8的半导体集成电路器件的制造方法，其中，在将芯片层叠体置于与步骤(c)相同的密封舱的状态下，执行步骤(d)。
10.按照段落1到9中任一段落的半导体集成电路器件的制造方法，其中所述芯片层叠体累积为类似台阶的形状。
11.按照段落1到10中任一段落的半导体集成电路器件的制造方法，其中所述静态气压是静态大气压。
12.按照段落1到11中任一段落的半导体集成电路器件的制造方法，其中每个半导体芯片的厚度是79微米或更小以及5微米或更多。
13.按照段落1到11中任一段落的半导体集成电路器件的制造方法，其中每个半导体芯片的厚度是50微米或更少以及5微米或更多。
14.按照段落1到11中任一段落的半导体集成电路器件的制造方法，其中每个半导体芯片的厚度是30微米或更少以及5微米或更多。
15.按照段落1到14中任一段落的半导体集成电路器件的制造方法，其中所述电路衬底是有机电路衬底。
16.按照段落1到15中任一段落的半导体集成电路器件的制造方法，其中所述粘附剂层包含可热固化的树脂作为主要组分。
17.按照段落1到16中任一段落的半导体集成电路器件的制造方法，其中，在半导体芯片的温度处于第一温度范围的状态下，执行步骤(b)。
18.按照段落1到17中任一段落的半导体集成电路器件的制造方法，其中所述第一温度从70℃到160℃。
19.按照段落1到18中任一段落的半导体集成电路器件的制造方法，其中所述第一温度范围是从室温到100℃。
20.按照段落1到18中任一段落的半导体集成电路器件的制造方法，其中所述第一温度范围是从60℃到100℃。
[本申请的描述格式以及基本术语和使用的说明]
1.在本申请中，尽管有时为了方便起见而将对实施方式的描述分为多个部分，但是这些分开的描述并非独立的或者彼此不同，相反，它们是一个例子的代表性部分、其中一个是另一个的部分细节、或者它们是对实施方式的部分或整体的修改等，除非特别明确地指出不是这样。此外，原则上，省去针对相同部分的重复描述。而且，实施方式的每个构成不是必不可少的，除非特别明确地指明不是这样、构成的数目是理论上确定的、或者从上下文看来明显不是这样。
此外，在本申请中，“半导体集成电路器件”表示主要在半导体芯片等上特别是与电阻器、电容器等一起集成有各种晶体管(有源元件)的器件(例如，单晶硅衬底)。
2.类似地，在对实施方式的描述中，即使在将材料、化合物等描述为“X包括A”等时，包括除了A之外的元素作为其组成的材料、化合物等也不是所排除的，除非特别明确地指出不是这样或是从上下文看来很明显不是这样。例如，对于化合物来说，上面的表述意味着“X包括A作为主要成分”。显然，例如“硅材料”等并不限于单纯的硅，而是还包括包含硅作为主要成分的SiGe合金以及多成分合金，并且还包括包含其他添加物等的硅材料。
3.类似地，对于形状、位置、属性等，尽管利用相应的优选示例来描述它们，但是显然，其每一个并非严格限于优选示例，除非特别明确地指出不是这样或者从上下文来看显然不是这样。
4.此外，在提及具体的数值或数量时，该数值或数量可以是超过该具体数值的数值，或者是小于该具体数值的数值，除非特别地指明不是这样、该数值在理论上限于该具体数值、或者从上下文看来很明显不是这样。
5.尽管通常“晶片”表示半导体集成电路器件(而且还有半导体器件和电子器件)形成于其上的单晶硅晶片，但是“晶片”显然包括外延晶片、SOI衬底、诸如LCD玻璃衬底的绝缘衬底、半导体层的合成晶片等。在本申请中，不仅将分割为个体芯片之前的晶片称为“晶片”，而且已经通过切割等而被分割并且附接至切割带等的晶片有时也称为“晶片”。
6.大气压是基于标准大气压，也即1.013×105Pa来表示的。
[实施方式的细节]
将进一步描述实施方式的细节。在每个附图中，相同或相似的部分由相同或类似的符号或参考标号来表示，并且原则上将不会重复说明。
此外，当剖面线等将使附图不希望地复杂化或者剖面与空白空间明显分开时，在附图中省略剖面线等，即使对于剖面也是如此。有关的问题是，即使从平面视图中封闭的孔来看，有时也省略了后面的轮廓线，只要这在说明上是清楚的。而且，为了示出不是空白空间的部分，即使对于不是剖面的部分也提供剖面线。
注意，管芯键合中的芯片分离，也即拾取过程等的细节，在本发明人以及其他人的专利文献中有所描述：日本专利申请号2008-299643(申请于2008年11月25日)、日本专利申请号2008-137631(申请于2008年5月27日)、日本专利申请号2008-099965(2008年4月8日申请)以及相应的美国专利公开号2008-0318346(公开于2008年12月25日)，并且本申请原则上将不会重复关于这些部分的说明，除非特别需要。
1.对用于本申请实施方式中的半导体集成电路器件的制造方法的管芯键合器等的说明(主要从图3到图6)
图3是用于本申请实施方式中的半导体集成电路器件的制造方法的管芯键合器51的示意性前视图。
首先，将使用图3来描述用于本发明实施方式中的半导体集成电路器件的制造方法的管芯键合器的重要部分的轮廓。如图3中所示，管芯键合器51的壳体(管芯分离和键合设备)配置有较低基体63、较高基体64、连接基体的支撑柱65等。在该较低基体63上的芯片分离部分66中提供有晶片保持器X-Y台69，并且在X-Y台69上安装有保持晶片1(通常，晶片已经被分为个体芯片)的晶片保持器70。
同时，在较高基体64的较低平面上提供管芯键合头X-Y台69，并且管芯键合头73附接至该X-Y台69。此外，在管芯键合头73的下端，提供有吸附夹头74(芯片保持部分)，用于对半导体芯片2的真空吸附等。
此外，提供有一对衬底传送路径71，用于传送较低基体52的上表面上的后部处的电路衬底3；并且在其之间的临时压力键合部分67处提供管芯键合级72，用于执行管芯关键(临时压力键合)。
此外，提供静态压力施加部分(主热压键合部分)68，其具有静态压力施加舱(层叠处理舱)54，其是将要打开和关闭的密封盒。
图4是示出图3的管芯键合器中的管芯键合头的下端处提供的吸附夹头74的结构的剖面图。如图4中所示，吸附夹头74配置有：橡胶芯片保持器76，其例如包括较高部分金属等；以及附接至其较低部分的橡胶片75；并且在其相应内侧提供有真空吸附孔77和78，用于真空吸附半导体芯片2的上表面2a(器件表面)。该橡胶芯片75的示例可以是包含热弹性体(诸如，具有shore A硬度约为50的热硬化橡胶)作为其主要成分的材料。(可以使用热塑橡胶。然而，可热固的材料更不易受到热效应的影响)。此外，优选硬度范围的示例是从30到70。注意，几乎整个吸附夹头74可以由硬金属等构成。然而，对于诸如空隙等管芯键合特性而言，使用在此所示的橡胶片75通常是优选的。
在半导体芯片2的下表面上形成粘附剂层5，也即DAF(管芯附接膜)，并且通过半导体芯片2、粘附剂层5(例如，厚度约为20微米)等配置芯片层叠体11。
图5是图3的管芯键合器中的静态压力施加部分(主要热压键合部分)的侧剖视图，并且图6是图3的管芯键合器的静态压力应用部分68(主热压键合部分)中的静态压力施加舱54(层叠处理舱)的前剖面图。如图5和图6所示，在静态压力施加舱54中，提供有电路衬底级55，其用于保持电路衬底(有机多层布线衬底)3，从而引导其器件表面3a向上。此外，对于加热电路衬底3(更具体的，半导体芯片2)的机制而言，远红外加热器62a、62b中的任意一个具有速度上的优势，尽管可以存在其他变形。对于这些加热器的安置，存在一种方法将远红外加热器62a安置在静态压力施加舱54的上部平面上提供的透明窗口61之外作为外部远红外加热器62a，以及一种方法将远红外加热器62b安置在静态压力施加舱54之内作为内部远红外加热器62b。对于这些远红外加热器，外部远红外加热器62a具有降温速度上的优势。而且，存在一种简单的方法将加热块62c安置在电路衬底级55之内或较低部分等中。
静态压力施加舱54可以通过静态压力施加舱打开/关闭机制56而被打开和关闭，并且可以输入和弹出电路衬底3；并且可以通过与增压空气供给57(高压空气供给)、电磁开关阀59(电动控制打开和关闭)、电气压调节器(具有压力传感器的自动压力调节电磁阀)60等耦合的气压调节器58(用于设置所需的最大气压)，来将静态压力施加舱打开/关闭机制56内部设置为期望的气压。这里，电气压调节器60通过按照输出侧上的压力传感器来重复开/关，来将操作静态压力应用舱54内部维持在预定的增压状态。
2.对本申请实施方式中的半导体集成电路器件的制造方法中的组装过程概况的说明(主要为图1、图2以及图8到图17)
图8到图17等示出了微SD的示例，其约为29.1毫米长，19.2毫米宽，并且当该微SD被层叠为类似台阶的形状时，芯片安置误差倾向于与层叠层的数目成比例地积聚。目前，层叠层的数目已经增加，并且具有约16个层叠层的高积聚结构已经变得普遍，因此进一步需要改进的管芯键合精度。对于MAP(模塑阵列工艺)等同样存在对此位置精度改进的需要，并不限于微SD。此外，对于层叠产品而言这通常是重要的问题，并不限于类似台阶的层叠。
这里，将使用图1、图2以及图8到图17来描述包括管芯键合过程的组装工艺。首先，将描述图1中的管芯键合过程101。该过程在图3所说明的管芯键合设备51中执行。
首先，如图2所示，将电路衬底3加载到管芯键合设备51中(衬底加载步骤110)。接下来，如图2中所示，将电路衬底3移动到临时压力键合级72上，并且执行临时压力键合处理111。也即，如图8所示，使吸附夹头74(更准确地，图4中的橡胶片75的下平面)就位在目标芯片2的器件表面2a上，以便将目标芯片从粘附在切割带12上的多个芯片2上分离，其中切割带12被真空吸附在管芯键合设备51的芯片分离部分66中的晶片级(芯片分离级)70上。注意，例如，芯片2的器件表面2a提供有基于铝等的键合焊盘7。
接下来，如图9所示，提升吸附夹头74，并且芯片2完全从切割带12分离。更准确地，包括半导体芯片2、粘附剂层5等的芯片层叠体11完全从切割带12分离。
接下来，如图10所示，保持有芯片层叠体11的吸附夹头74随同管芯键合头73(图3)的移动，而向布置在临时压力键合部分67的临时压力键合级72上的布线衬底3降低。在布线衬底3的器件表面3a上的各器件区域4(单位器件区域)中提供有多个外部引线6等。注意，临时压力键合级72的较低部分或者内部提供有诸如加热块81的加热机制，并且可以被加热并维持在从室温到大约160℃的温度范围内(温度由加热块的设定温度来指示)。通常，从粘附剂层5等的加热历史的角度看，临时压力键合过程优选地在从室温范围(15℃到35℃)到100℃的温度范围中执行。此外，当温度超过100℃时，温度变得接近作为通用衬底材料(在有机电路衬底的情况下)的玻璃环氧的玻璃化(glass transition)温度(约130℃)，并由此导致了诸如热应力增加等问题。此外，为了灵活地适应各类粘附剂材料，有时将临时压力键合的温度范围的下限适当地设置为60℃到70℃。这里，例如将加热块81的设定温度设为约80℃(优选范围是约从60℃到100℃的范围)。显然，当这些问题不太大时，可以将温度设置在约从室温到160℃的较宽范围内。
接下来，如图11所示，保持有芯片层叠体11的吸附夹头74就位在由加热块81加热并维持在约80℃温度的临时压力键合级72上的布线衬底3的器件表面3a上，并且将键合负荷维持在该状态下达一定的时间。键合负荷例如是约0.1兆帕(优选范围是从0.05到0.2兆帕)，并且维持时间(负荷施加时间)例如约为1秒(优选范围约从0.05到2秒)。
如图12所示，通过重复这样的分离和管芯键合过程，预定数目(这里是4个，但是通常是按照需要选择的约从2到10的数目)的层叠层被层叠到第一器件区域4中；继而如图13所示，预定数目的层叠层的临时压力键合顺序位移到另一器件区域4(通常是相邻的器件区域)，并且通过重复分离和管芯键合过程而类似地执行；最终，针对要处理的所有器件区域4完成层叠和临时压力键合。
图14是图13中每个器件区域的放大视图(省略了电路衬底)，并且图15是对应于图14的剖面X-X’的器件和设备的示意性剖面图。显然，属于第一层叠单元15的半导体芯片2(芯片层叠体11)层叠为类似台阶的形状。在完成了对属于第一层叠单元15的半导体芯片2(芯片层叠体11)的层叠时，过程移动到主压力键合处理(层叠处理)112(图2)，但是主压力键合处理(层叠处理)112将在部分3中描述，而后续过程将在此描述。
在完成了主压力键合处理(层叠处理)112之后(管芯键合过程101已经完成)，如图1所示，布线衬底3被卸载(图2中的衬底卸载步骤119)并且被转移至布线键合设备52。执行如图16所示的布线键合过程102。在此，例如，布线8是基于金的键合布线。注意，键合布线也可以是基于铜或者基于铝的键合布线。
在布线键合过程102完成之后，如图1所示，布线衬底3被转移至树脂密封设备53，并且执行如图17所示的密封过程103。这里，例如，树脂密封体(密封树脂部分)9包含环氧基树脂作为主要成分。
3.对作为本申请实施方式中的半导体集成电路器件制造方法的重要部分的管芯键合过程的详细说明(主要是图1、图2、图3、图5到图7、图15和图18)
图2是示出作为本申请实施方式中的半导体集成电路器件制造方法的重要部分的管芯键合过程的细节的过程流程图。图7是示出图2的主压力键合处理(层叠处理)中的过程序列的示例的详细过程序列图。该部分将描述在部分2中描述的图1的管芯键合过程101中的主压力键合处理(层叠处理)112(图2)。
如图2、图5、图6(这里，将针对仅存在外部远红外加热器62a和加热块62c作为加热机制的情况来提供说明)和图7中所示，在临时压力键合处理111完成之后，静态压力施加舱54打开，以便将电路衬底3接受到其电路衬底级55上，并且静态压力施加舱54在时刻t1关闭。例如，从t1到随后的t2的时间约为5秒。
接下来，在时刻t2，静态压力施加舱54中的增压变为“打开”状态，并且维持该状态直到时刻t3(通过气相静态压力的增压的步骤115)。此时，例如，将电路衬底级55的设定温度(气相静态压力增压温度T2或者主热压键合预处理温度)设置为室温(约25℃)。从t2到t3的这一时间例如约为2秒(优选范围的示例可以是约从1秒到10秒的范围)。注意，例如，在“打开”状态中，静态压力施加舱54的用于增压的气压约为0.2兆帕(对于下文的“打开”状态也是同样)。优选范围的示例可以是约从0.05到0.6兆帕的范围。注意，尽管从粘附剂层5的热学历史的角度看，气相静态压力增压温度T2优选地在室温范围(也即，约从15℃到35℃的温度范围)内，但是通常，气相静态压力增压优选地在约从60℃或70℃到100℃的第一温度范围R1’(相对较高的温度范围)中执行，以适应各种粘附剂。相应地，在充分考虑粘附剂特性的情况下，适用于气相静态压力增压温度T2的第一温度范围R1的示例可以是约从15℃到100℃的范围。
接下来，在时刻t3，外部远红外加热器62a变为“打开”状态，以开始升高电路衬底3上的每个半导体芯片2的温度，并且使每个半导体芯片2的温度在时刻t4达到第一温度T1(层叠温度或主压力键合温度)。例如，从t3到t4的这一时间约为5秒。例如，层叠温度约为150℃。优选范围的示例可以是约从70℃到160℃。
接下来，维持该状态，直到时刻t5(通过气相静态压力的热压键合的步骤116)。例如，从t4到t5的这一时间(主热压键合处理时间)约为8秒。此主热压键合处理时间的优选范围的示例可以是约从2秒到60秒的范围。
接下来，在时刻t5，关闭外部远红外加热器62a，并且每个半导体芯片2中的温度开始下降，并且在时刻t6降低到与气相静态压力增压温度(主热压键合预处理温度)T2相同的温度。例如，从t5到t6的这一时间约为3秒。
继而，约在与时刻t6相同的时刻，静态气压施加舱54中的增压变为“关闭”状态(正常压力)(压力释放117)，并且在时刻t7，静态压力施加舱54打开，并且开始将电路衬底3卸载到静态压力施加舱54的外部。例如，从t6到t7的这一时间约为2秒。
接下来，在时刻t8，电路衬底3从静态压力施加舱54的卸载完成。例如，从t7到t8的这一时间约为5秒。
在包括诸如通过气相静态压力的热压键合步骤116(图2)的管芯键合方法中，如图15和图18所示，还从上方和下方在芯片2的悬垂部分上施加近似均匀的压力，并且不会发生弯曲或者损坏。此外，尽管芯片形成了类似台阶的形状，但是在上层中不具有其他芯片的部分也被从上施加了近似相同的均匀压力，并且在该部分中也执行了均匀键合。此外，尽管因为偏移力容易施加在水平方向上而使得有可能会在机械增压中发生芯片的水平偏移，但是在这种情况下不会发生水平位置偏移，因为水平压力在芯片2(芯片层叠体11)的前后之间和左右之间是平衡的。
此外，如图2和图7中所示，当在通过气相静态压力的热压键合处理步骤116之前执行通过气相静态压力的增压处理(主热压键合预处理)步骤115时，可以在通过气相静态压力的增压处理步骤115将粘附剂层5内部以及粘附剂层与用于粘附的表面之间的空气层、气泡以及类似物进行充分释放之后，在通过气相静态压力的热压键合处理步骤116中对粘附剂层5的进行硬化，从而有可能实现没有空隙等的强管芯键合(在粘附剂层5包含可热固化的树脂作为主要成分的情况下)。尽管这种通过气相静态压力的增压处理步骤115并非总是必须的，但是增加该处理有助于改进管芯键合属性。此外，通过气相静态压力的增压处理步骤115未必是独立步骤，而是可以作为与图7的温度提升步骤(t3到t4)集成的步骤而被引入。
如图2和图15所示，在通过气相静态压力的增压中(或者具有额外加热的相同处理中)，针对多层层叠芯片(其具有仅仅通过临时压力键合处理而获得的相对较弱的粘附状态)执行主压力键合处理112(层叠处理)，由此使均匀的增压成为可能，而无需依赖于芯片面积或者特定的积聚结构，即使对于相对不稳定的结构也是如此。
此外，可以针对批量的芯片来执行主压力键合处理112(层叠处理)，并且与机械地针对多个部分的一个部分或单元逐个执行主压力键合处理112(层叠处理)的过程相比，这可以极大地改进生产量。
注意，利用通过气相静态压力的增压处理(或者具有额外极热的相同处理)来执行这种主压力键合处理112(层叠处理)的方法对于薄膜芯片(也即，厚度为75微米或更小的芯片)而言是有效的。而且，该过程对于厚度为50微米或更小的芯片尤为有效，并且该过程对于确保厚度为30微米或更小的芯片的可靠性来说是有效的。注意，对于通常的集成电路来说，芯片厚度的下限被认为是5微米，同时下限依赖于器件的类型。
4.对示出在本申请实施方式中的半导体集成电路器件制造方法中提供进一步更多层的情况的示例的组装过程的概括的说明(主要是图18到图20)
该部分描述在部分2中所描述的组装过程中提供更多层叠层的情况的处理序列的示例。在提供更多积聚层的情况下，如图16所示，在布线键合过程102完成时(当被定义为集合图1的管芯键合过程101以及布线键合过程102的过程的键合过程104完成时)，将电路衬底3再次返回到相同或者其他类似的管芯键合设备51，并且执行管芯键合过程101。也即，如图18所示，例如，通过反转芯片的方向，以及如针对上面的第一层叠层15的半导体芯片2(芯片层叠体11)的上述过程那样，将芯片键合在属于第一层叠单元15的顶层中的半导体芯片2(顶层中的芯片层叠体)之上，来针对属于第二层叠单元16的预定数目的半导体芯片2(芯片数目与第一层叠单元15的芯片数目相同)执行管芯键合过程101(临时压力键合和主压力键合)。
接下来，如图19所示，将电路衬底3转移至相同或者其他类似的布线键合设备52，并且执行布线键合过程102。也即，按照需要重复该键合过程104，并且对所有需要的半导体芯片2(芯片层叠体11)进行层叠和管芯键合，以形成锯齿形的类似台阶的形状。此后，如图20所示，执行树脂封装过程103。
5.小结
尽管已经通过使用上述实施方式特别地描述了发明人所实现的发明，但是本发明不限于该描述，并且显然可以在不脱离其精神的情况下在一定范围内进行各种修改。
例如，尽管上述实施方式是针对在作为示例的将芯片层叠为类似台阶的形状的特定情况而说明的，但是本申请的发明不限于这种情况，并且显然可以应用于层叠方法的其他情况。

Claims (20)

1.一种半导体集成电路器件的制造方法，包括步骤：
(a)将在其第一主表面上具有多个器件区域的电路衬底引入管芯键合设备；
(b)在所述管芯键合设备中，将多个芯片层叠体固定在每个所述器件区域中，每个所述芯片层叠体具有在其上层中的半导体芯片以及其后侧上的粘附剂层，从而将所述芯片层叠体层叠在彼此偏移的相应位置中；以及
(c)在步骤(b)之后，在所述管芯键合设备中，在将每个所述芯片层叠体加热到第一温度的状态下，在每个所述芯片层叠体的暴露表面上施加均匀的静态气压。
2.按照权利要求1的半导体集成电路的制造方法，进一步包括步骤：
(d)在步骤(b)之后、步骤(c)之前，在所述管芯键合设备中，在芯片层叠体温度处于低于所述第一温度的第一温度范围的状态下，在每个所述芯片层叠体的所述暴露表面上施加均匀的静态气压。
3.按照权利要求2的半导体集成电路器件的制造方法，其中：所述粘附剂层是DAF。
4.按照权利要求3的半导体集成电路器件的制造方法，其中：在将所述芯片层叠体置于单个密封舱的状态下，执行步骤(c)。
5.按照权利要求4的半导体集成电路器件的制造方法，其中：在将所述芯片层叠体置于单个密封舱的状态下，执行步骤(d)。
6.按照权利要求5的半导体集成电路器件的制造方法，其中：在将所述芯片层叠体置于与步骤(c)相同的所述密封舱的状态下，执行步骤(d)。
7.按照权利要求3的半导体集成电路器件的制造方法，其中：在将所述芯片层叠体与所述电路衬底一起置于单个密封舱的状态下，执行步骤(c)。
8.按照权利要求7的半导体集成电路器件的制造方法，其中：在将所述芯片层叠体与所述电路衬底一起置于单个密封舱的状态下，执行步骤(d)。
9.按照权利要求8的半导体集成电路器件的制造方法，其中：在将所述芯片层叠体置于与步骤(c)相同的所述密封舱的状态下，执行步骤(d)。
10.按照权利要求7的半导体集成电路器件的制造方法，其中：所述芯片层叠体被层叠为类似台阶的形状。
11.按照权利要求1的半导体集成电路器件的制造方法，其中：所述静态气压是静态大气压。
12.按照权利要求1的半导体集成电路器件的制造方法，其中：每个所述半导体芯片的厚度是79微米或更小以及5微米或更多。
13.按照权利要求1的半导体集成电路器件的制造方法，其中：每个所述半导体芯片的厚度是50微米或更少以及5微米或更多。
14.按照权利要求1的半导体集成电路器件的制造方法，其中：每个所述半导体芯片的厚度是30微米或更少以及5微米或更多。
15.按照权利要求1的半导体集成电路器件的制造方法，其中：所述电路衬底是有机电路衬底。
16.按照权利要求1的半导体集成电路器件的制造方法，其中：所述粘附剂层包含可热固化的树脂作为其主要成分。
17.按照权利要求12的半导体集成电路器件的制造方法，其中：在所述半导体芯片的温度处于所述第一温度范围内的状态下，执行步骤(b)。
18.按照权利要求12的半导体集成电路器件的制造方法，其中：所述第一温度从70℃到160℃。
19.按照权利要求12的半导体集成电路器件的制造方法，其中：所述第一温度范围是从室温到100℃。
20.按照权利要求12的半导体集成电路器件的制造方法，其中：所述第一温度范围是从60℃到100℃。
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US20130330879A1 (en) 2013-12-12
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JP2010245412A (ja) 2010-10-28
US8450150B2 (en) 2013-05-28

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