WO2009014087A1 - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法 Download PDF

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Publication number
WO2009014087A1
WO2009014087A1 PCT/JP2008/063020 JP2008063020W WO2009014087A1 WO 2009014087 A1 WO2009014087 A1 WO 2009014087A1 JP 2008063020 W JP2008063020 W JP 2008063020W WO 2009014087 A1 WO2009014087 A1 WO 2009014087A1
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WO
WIPO (PCT)
Prior art keywords
chip
wafer
adhesive film
bonding
bonded
Prior art date
Application number
PCT/JP2008/063020
Other languages
English (en)
French (fr)
Inventor
Jun Maeda
Keiko Tanaka
Osamu Yamazaki
Original Assignee
Lintec Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lintec Corporation filed Critical Lintec Corporation
Priority to KR1020107000403A priority Critical patent/KR101133892B1/ko
Priority to US12/670,127 priority patent/US8003441B2/en
Publication of WO2009014087A1 publication Critical patent/WO2009014087A1/ja

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    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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Abstract

　本発明に係る半導体装置の製造方法は、ウエハ（１）の回路表面に、接着フィルム（３）が接着され、かつ該回路毎に区画する溝（６）が形成されてなるウエハの回路表面側に表面保護シート（７）を貼着する工程、上記ウエハの裏面研削をすることでウエハ（１）の厚みを薄くするとともに、最終的には個々のチップ（１０）への分割を行う工程、個別のチップ（１０）を接着フィルム（３）とともにピックアップする工程、個別のチップを該接着フィルムを介して、チップ搭載用基板（１１）の所定位置にダイボンドする工程、およびダイボンドされた接着フィルム付きチップを加熱し、チップをチップ搭載用基板に固着する工程を含み、かつ接着フィルムをウエハに接着した後、チップをチップ搭載用基板に固着するまでの何れかの段階で、接着フィルムを含む積層体を、常圧に対し０．０５ＭＰａ以上の静圧により加圧する工程を１回以上含むことを特徴としている。
PCT/JP2008/063020 2007-07-23 2008-07-18 半導体装置の製造方法 WO2009014087A1 (ja)

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US12/670,127 US8003441B2 (en) 2007-07-23 2008-07-18 Manufacturing method of semiconductor device

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