JP5579879B2 - オフセットダイスタッキングを用いたマルチチップパッケージ - Google Patents
オフセットダイスタッキングを用いたマルチチップパッケージ Download PDFInfo
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- JP5579879B2 JP5579879B2 JP2012557360A JP2012557360A JP5579879B2 JP 5579879 B2 JP5579879 B2 JP 5579879B2 JP 2012557360 A JP2012557360 A JP 2012557360A JP 2012557360 A JP2012557360 A JP 2012557360A JP 5579879 B2 JP5579879 B2 JP 5579879B2
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- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
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- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
- H01L2924/1435—Random access memory [RAM]
- H01L2924/1438—Flash memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Description
本出願は、米国特許仮出願番号第61/315,111号の優先権を主張するものであり、その内容はそのまま参照により本明細書中に組み込まれている。
Δi=(i−1)d (式1)
Δj=[m+(n−j)]d (式2)
102、102A、102B、102C、102D ダイ
104、104A、104B、104C、104D ボンディングパッド
106、106A、106B、106C、106D ボンドワイヤ
108 基板
110 はんだボール
112 インターポーザ
200 MCP
202、202A、202B、202C、202D ダイ
204 ボンディングパッド
206 ボンドワイヤ
208 基板
210 はんだボール
300 MCP
302、302A、302B、302C、302D ダイ
304、304A、304B、304C、304D ボンディングパッド
306 ボンドワイヤ
308 基板
310 はんだボール
400 MCP
402 ダイ
404 ボンディングパッド
406 ボンドワイヤ
408 基板
600 MCP
602、602A、602B、602C、602D ダイ
604、604A、604B、604C、604D ボンディングパッド
606、606A、606B、606C、606D ボンドワイヤ
608 基板
610 はんだボール
700 MCP
702、702A、702B、702C、702D ダイ
704、704A、704B、704C、704D ボンディングパッド
706、706A、706B、706C、706D ボンドワイヤ
708 基板
900 MCP
902、902A、902B、902C、902D、902E、902F ダイ
1000 MCP
1002、1002A、1002B、1002C、1002D、1002E、1002F ダイ
1100 MCP
1102、1102A、1102B、1102C、1102D、1102E、1102F、1102G、1102H ダイ
1114、1116 サブスタック
1200 MCP
1202、1202A、1202B、1202C、1202D ダイ
1204、1204A、1204B、1204C、1204D ボンディングパッド
1206 ボンドワイヤ
1208 基板
1300 MCP
1302、1302A、1302B、1302C、1302D ダイ
1304 ボンディングパッド
1306 ボンドワイヤ
1308 基板
ΔB、ΔC、ΔD オフセット距離
d 距離
Claims (7)
- 平坦な基板と、
前記基板上にマウントされた複数のスタックした半導体ダイであって、前記複数のダイの各ダイが類似の寸法を有し、各ダイが前記ダイの第1のボンディング端に沿って配列した第1の複数のボンディングパッドを有し、前記複数のダイが、
前記基板にマウントされた第1のダイの第1のグループであって、第1の方向に配向した各第1のダイの前記第1のボンディング端を有している第1のグループと、
前記基板にマウントされた第2のダイの第2のグループであって、前記第1の方向と反対の第2の方向に配向した各第2のダイの前記第1のボンディング端を有している第2のグループと、を含み、
各ダイの前記ボンディングパッドが前記基板に垂直な方向において前記基板と残りのダイのいずれかの部分との間に配置されないように、前記複数のダイの各ダイがそれぞれの横方向オフセット距離だけ前記複数のダイの前記残りのダイに対して前記第2の方向に横方向にオフセットされる、複数のスタックした半導体ダイと、
前記基板に前記第1の複数のボンディングパッドを接続する複数のボンディングワイヤと
を備えた、半導体デバイス。 - 前記複数の半導体ダイが、
前記基板にマウントされた第3のダイの第3のグループであって、前記第1の方向および前記第2の方向とは異なる第3の方向に配向した各第3のダイの前記第1のボンディング端を有している第3のグループと、
前記基板にマウントされた第4のダイの第4のグループであって、前記第3の方向と反対の第4の方向に配向した各第4のダイの前記第1のボンディング端を有している第4のグループと
をさらに備え、
前記第3の方向および前記第4の方向が前記第1の方向および前記第2の方向に対して90度に各々配向される、
請求項1に記載の半導体デバイス。 - 前記第1のグループの前記第1のダイと前記第2のグループの前記第2のダイが交互にスタックされた、請求項1に記載の半導体デバイス。
- 各ダイが、前記第1のボンディング端に対して垂直な方向にある第2のボンディング端に沿って配列した第2の複数のボンディングパッドをさらに含む、請求項1に記載の半導体デバイス。
- 前記第1の方向が、前記第2の方向と反対であり、
前記第1のダイの各々の前記第2のボンディング端が、前記第1の方向および前記第2の方向とは異なる第3の方向に配向され、
前記第2のダイの各々の前記第2のボンディング端が、前記第3の方向と反対の第4の方向に配向される、
請求項4に記載の半導体デバイス。 - ダイの前記第1のグループがm個の第1のダイを含み、
ダイの前記第2のグループがn個の第2のダイを含み、
ダイの前記第1のグループの第1のダイが、前記基板に最も近いダイであり、
ダイの前記第1のグループの前記基板からi番目のダイの横方向オフセット距離Δiが、Δi=(i−1)dであり、
ダイの前記第2のグループの前記基板からj番目のダイの横方向オフセット距離Δjが、Δj=[m+(n−j)]dであり、
ここでは、dが所定の距離である、
請求項1に記載の半導体デバイス。 - dが前記第2の方向の各ダイの前記第1の複数のボンディングパッドの横方向幅である、請求項6に記載の半導体デバイス。
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US61/315,111 | 2010-03-18 | ||
PCT/CA2011/000253 WO2011113136A1 (en) | 2010-03-18 | 2011-03-08 | Multi-chip package with offset die stacking and method of making same |
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JP2013522887A JP2013522887A (ja) | 2013-06-13 |
JP2013522887A5 JP2013522887A5 (ja) | 2014-02-20 |
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EP (1) | EP2548226A4 (ja) |
JP (1) | JP5579879B2 (ja) |
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-
2011
- 2011-03-08 CN CN2011800143724A patent/CN103098206A/zh active Pending
- 2011-03-08 KR KR1020127026510A patent/KR20130007602A/ko not_active Application Discontinuation
- 2011-03-08 US US13/042,571 patent/US8502368B2/en active Active
- 2011-03-08 EP EP11755583.9A patent/EP2548226A4/en not_active Withdrawn
- 2011-03-08 WO PCT/CA2011/000253 patent/WO2011113136A1/en active Application Filing
- 2011-03-08 JP JP2012557360A patent/JP5579879B2/ja not_active Expired - Fee Related
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2013
- 2013-07-25 US US13/951,132 patent/US9177863B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
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WO2011113136A1 (en) | 2011-09-22 |
KR20130007602A (ko) | 2013-01-18 |
US20120056335A1 (en) | 2012-03-08 |
US9177863B2 (en) | 2015-11-03 |
CN103098206A (zh) | 2013-05-08 |
EP2548226A4 (en) | 2013-11-20 |
JP2013522887A (ja) | 2013-06-13 |
US20130309810A1 (en) | 2013-11-21 |
US8502368B2 (en) | 2013-08-06 |
EP2548226A1 (en) | 2013-01-23 |
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