TW202218099A - 包含半導體晶片的半導體封裝 - Google Patents

包含半導體晶片的半導體封裝 Download PDF

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TW202218099A
TW202218099A TW110118358A TW110118358A TW202218099A TW 202218099 A TW202218099 A TW 202218099A TW 110118358 A TW110118358 A TW 110118358A TW 110118358 A TW110118358 A TW 110118358A TW 202218099 A TW202218099 A TW 202218099A
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Taiwan
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semiconductor
memory
memory chip
tower
chip
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TW110118358A
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English (en)
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姜炫求
成載圭
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南韓商三星電子股份有限公司
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Publication of TW202218099A publication Critical patent/TW202218099A/zh

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Abstract

本發明提供一種半導體封裝，可包含在封裝基底上的半導體晶片。半導體封裝可包含將半導體晶片連接至封裝基底的多個導電連接件以及彼此隔開且各自包含多個記憶體晶片的多個塔，其中從俯視圖來看多個塔中的每一者的最下部記憶體晶片與半導體晶片重疊。半導體封裝更包含附接於多個塔中的每一者的最下部記憶體晶片與半導體晶片之間的多個黏著層。

Description

包含半導體晶片的半導體封裝
本發明概念是關於一種包含多個半導體晶片的半導體封裝及製造半導體封裝的方法。
正在研究裝備有多個半導體晶片的多種半導體封裝。每一半導體封裝的大小可基於工業標準而標準化。隨著裝備在具有有限大小的半導體封裝中的半導體晶片的數目增大，易於提高整合程度及操作速度。
本揭露的例示性實施例提供一種裝備有多個半導體晶片的半導體封裝及製造半導體封裝的方法。
根據本揭露的實施例的半導體封裝可包含在封裝基底上的半導體晶片。半導體封裝另外可包含：將半導體晶片連接至封裝基底的多個第一導電連接件；在封裝基底上的第一間隔件及第二間隔件，所述第一間隔件及所述第二間隔件中的每一者與半導體晶片水平間隔開；以及第一塔及第二塔。第一塔及第二塔中的每一者包含多個記憶體晶片，第一記憶體晶片安置於第一塔的最下端處且從俯視圖來看與半導體晶片及第一間隔件豎直地重疊，以及第二記憶體晶片安置於第二塔的最下端處且從俯視圖來看與半導體晶片及第二間隔件豎直地重疊。半導體封裝可更包含多個第一黏著層。多個第一黏著層包含：附接於第一記憶體晶片與半導體晶片之間的黏著層、附接於第一記憶體晶片與第一間隔件之間的黏著層、附接於第二記憶體晶片與半導體晶片之間的黏著層，以及附接於第二記憶體晶片與第二間隔件之間的黏著層。
根據本揭露的實施例的半導體封裝可包含在封裝基底上的半導體晶片。半導體封裝可包含將半導體晶片連接至封裝基底的多個導電連接件以及彼此隔開且各自包含多個記憶體晶片的多個塔，其中從俯視圖來看多個塔中的每一者的最下部記憶體晶片與半導體晶片重疊。半導體封裝更包含附接於多個塔中的每一者的最下部記憶體晶片與半導體晶片之間的多個黏著層。
根據本揭露的實施例的半導體封裝可包含在封裝基底上且彼此水平地間隔開的第一半導體晶片、第二半導體晶片以及第三半導體晶片。半導體封裝可包含將第一半導體晶片至第三半導體晶片連接至封裝基底的多個第一導電連接件，以及各自包含多個記憶體晶片的第一塔及第二塔。從俯視圖來看安置於第一塔的最下端處的第一記憶體晶片可與第一半導體晶片及第二半導體晶片重疊。從俯視圖來看，安置於第二塔的最下端處的第二記憶體晶片可與第一半導體晶片及第三半導體晶片重疊。多個第一黏著層可分別附接於第一記憶體晶片與第一半導體晶片之間、第一記憶體晶片與第二半導體晶片之間、第二記憶體晶片與第一半導體晶片之間，以及第二記憶體晶片與第三半導體晶片之間。
圖1為用於描述根據本揭露的實施例的半導體封裝的橫截面圖。根據本揭露的實施例的半導體封裝可包含都爾門狀（Dolmen-like）結構（例如，反向）。
參考圖1，根據本揭露的實施例的半導體封裝可包含封裝基底11、第一半導體晶片21、第一間隔件27、第二間隔件28、多個主記憶體晶片31至38以及51至58、多個基底黏著層71、多個第一黏著層72、多個第二黏著層73、多個第一導電連接件81、多個第二導電連接件83，以及密封體91。
半導體封裝可包含第一側表面S1及與第一側表面S1相對的第二側表面S2。可基於封裝基底11及/或密封體91而判定第一側表面S1及第二側表面S2。在實施例中，封裝基底11及密封體91可暴露於第一側表面S1及第二側表面S2處。封裝基底11及密封體91的側表面可實質上彼此共面。如本文中所使用的諸如「相同」、「相等」、「平面」或「共面」的術語涵蓋包含例如由於製造製程而可引起的變化的相同或接近的相同。除非上下文或其他陳述另外指示，否則本文中可使用術語「實質上」來強調此含義。
封裝基底11可包含多個基底佈線13及多個基底接墊15。第一半導體晶片21可包含多個第一接墊25。
為便於說明，多個主記憶體晶片31至38以及51至58可分別被稱作第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33、第四記憶體晶片34、第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37、第八記憶體晶片38、第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53、第二十四記憶體晶片54、第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57，以及第二十八記憶體晶片58。第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33、第四記憶體晶片34、第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37以及第八記憶體晶片38可組態第一塔T1。第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53、第二十四記憶體晶片54、第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57以及第二十八記憶體晶片58可組態第二塔T2。顯而易見，諸如「第一」、「第二」、「第三」等序數可簡單地用作某些元件、步驟等的標記以將此類元件、步驟等彼此區分開。在本說明書中未使用「第一」、「第二」等描述的術語在申請專利範圍中仍可稱作「第一」或「第二」。另外，用特定序數引用的術語（例如，在特定申請專利範圍中的「第一」）可在其他處用不同序數（例如，在本說明書或另一申請專利範圍中的「第二」）描述。詳言之，關於本文中所論述的記憶體晶片的堆疊，諸如「第二十一」、「第三十一」等的術語僅意欲作為標記。在堆疊晶片的上下文中，為指定晶片堆疊內的位置，將使用諸如「定位（-positioned）」的術語，例如，來自記憶體晶片的堆疊的底部的首先定位的記憶體晶片、來自記憶體晶片的堆疊的頂部的第三定位的記憶體晶片，來自記憶體晶片的堆疊的底部的最後定位的記憶體晶片等。
儘管在圖1中的每一堆疊中示出八個主記憶體晶片，但基於技術限制，多個主記憶體晶片31至38以及51至58可包含兩個或多於兩個或不同數目個記憶體晶片。多個主記憶體晶片31至38以及51至58中的每一者可包含多個第二接墊85。
圖2為用於描述根據本揭露的實施例的半導體封裝的佈局。
參考圖2，根據本揭露的實施例的半導體封裝可包含封裝基底11、第一半導體晶片21、多個主記憶體晶片31至38以及51至58、多個第一導電連接件81以及多個第二導電連接件83。
封裝基底11可包含多個基底接墊15（例如，封裝基底接墊）。第一半導體晶片21可包含多個第一接墊25（例如，晶片接墊）。第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33、第四記憶體晶片34、第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37以及第八記憶體晶片38可形成第一塔T1。第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53、第二十四記憶體晶片54、第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57以及第二十八記憶體晶片58可形成第二塔T2。第一塔T1及第二塔T2中的每一者可相對於封裝基底11的頂部表面具有成角定向。多個主記憶體晶片31至38以及51至58中的每一者可包含多個第二接墊85（例如，晶片接墊）。多個主記憶體晶片31至38以及51至58中的每一者可包含形成於由晶圓形成的半導體晶粒上的積體電路，所述積體電路包含記憶體胞元陣列。
再次參考圖1及圖2，封裝基底11可包含剛性印刷電路板（printed circuit board；PCB）、可撓性PCB或剛性-可撓性PCB。封裝基底11可為多層PCB。多個基底佈線13可形成於封裝基底11的內部部分及表面上。多個基底接墊15可形成於封裝基底11的頂部表面上。多個基底接墊15可包含指狀電極或指狀接墊。多個基底佈線13及多個基底接墊15可各自包含導電材料或由導電材料形成，所述導電材料諸如銅（Cu）、鋁（Al）、鎢（W）或其組合。多個基底接墊15可電連接至多個基底佈線13，且可形成於封裝基底11的外表面處以連接於多個基底佈線13與主記憶體晶片之間。
第一半導體晶片21、第一間隔件27以及第二間隔件28中的每一者可安置於封裝基底11上。多個基底黏著層71可附接於第一半導體晶片21與封裝基底11之間、第一間隔件27與封裝基底11之間，以及第二間隔件28與封裝基底11之間。多個基底黏著層71可包含底膠、黏著膜、直接黏著膜（direct adhesive film；DAF）、線上膜（film over wire；FOW）或其組合。在一些實施例中，第一半導體晶片21、第一間隔件27以及第二間隔件28全部都具有用於其各別基底黏著層71的相同材料。在其他實施例中，第一半導體晶片21、第一間隔件27以及第二間隔件28中的至少一者具有用於其各別基底黏著層71的與其他兩者不同的材料。第一間隔件27及第二間隔件28中的每一者可具有與第一半導體晶片21的豎直厚度實質上相同的豎直厚度。第一半導體晶片21、第一間隔件27以及第二間隔件28的頂部表面可實質上彼此共面。
第一半導體晶片21可包含形成於由晶圓形成的半導體晶粒上的積體電路，且可包含緩衝器晶片、插入件晶片、控制器晶片、邏輯晶片或其組合。在實施例中，第一半導體晶片21可包含操作速度相對快於多個主記憶體晶片31至38以及51至58中的每一者的操作速度的記憶體。舉例而言，第一半導體晶片21可包含操作速度相對快於多個主記憶體晶片31至38以及51至58中的每一者的操作速度的緩衝器記憶體裝置，如靜態隨機存取記憶體（static random access memory；SRAM）、動態隨機存取記憶體（dynamic random access memory；DRAM）或其組合。第一半導體晶片21可包含揮發性記憶體裝置、非揮發性記憶體裝置或其組合。多個第一接墊25可形成於第一半導體晶片21的一個表面上。多個第一接墊25可包含導電材料或由導電材料形成，所述導電材料諸如Cu、Al、W或其組合。
第一間隔件27及第二間隔件28中的每一者可包含諸如虛設晶片的虛設區塊，所述虛設區塊具有與第一半導體晶片21的豎直厚度實質上相同的豎直厚度。虛設區塊或虛設晶片可不執行電通信功能，但實際上可充當實體支撐結構。在實施例中，第一間隔件27及第二間隔件28中的每一者可包含PCB、金屬板、塑膠板或半導體基底。第一間隔件27及第二間隔件28中的每一者可描述為支撐區塊或支撐柱。如在此實體意義上使用的「區塊」指代具有實質上平坦的頂部及底部表面且具有剛性以支撐形成於其上的結構的三維結構。
第一半導體晶片21的中心可與封裝基底11的中心相鄰對準。在實施例中，第一半導體晶片21的中心可相對於封裝基底11的中心豎直對準（例如，從俯視圖來看）。第一間隔件27可安置於第一半導體晶片21與第一側表面S1之間。第二間隔件28可安置於第一半導體晶片21與第二側表面S2之間。
多個第一導電連接件81可安置於第一半導體晶片21與封裝基底11之間。多個第一導電連接件81可各自接觸多個第一接墊25及多個基底接墊15中的各別一者。第一半導體晶片21可經由多個第一接墊25、多個第一導電連接件81以及多個基底接墊15電連接至封裝基底11。多個第一導電連接件81可包含接線、樑形引線、導電帶、導電間隔件、基底穿孔（例如，矽穿孔）、焊球、焊料凸塊或其組合。舉例而言，在一些實施例中，所有第一導電連接件81為接線。在其他實施例中，第一導電連接件81中的每一者包含基底穿孔及連接至基底穿孔的焊料凸塊或焊球。在實施例中，多個第一導電連接件81可包含接線，諸如金（Au）線或Al線。
彼此隔開的第一塔T1及第二塔T2可安置於第一半導體晶片21上。第二塔T2可安置成與第一塔T1相對，例如相對於第一半導體晶片21的中心。從俯視圖來看，第一塔T1的至少一部分可與第一半導體晶片21重疊。從俯視圖來看，第一塔T1可與第一半導體晶片21及第一間隔件27重疊。從俯視圖來看，第二塔T2的至少一部分可與第一半導體晶片21重疊。從俯視圖來看，第二塔T2可與第一半導體晶片21及第二間隔件28重疊。在一些實施例中，在第一間隔件27、第一半導體晶片21以及第二間隔件28之間延伸的方向上，亦描述為晶片的第一堆疊的第一塔T1可具有與第一間隔件27的中心對準或在第一間隔件27的中心與第一半導體晶片21的中心之間的重心。類似地，在第一間隔件27、第一半導體晶片21以及第二間隔件28之間延伸的方向上，亦描述為晶片的第二堆疊的第二塔T2可具有與第二間隔件28的中心對準或在第二間隔件28的中心與第一半導體晶片21的中心之間的重心。
第一記憶體晶片31可安置於第一塔T1的最下端處。第一記憶體晶片31可被稱作第一塔T1的最下部主記憶體晶片。第一記憶體晶片31且因此第一塔T1可懸垂於第一半導體晶片21，使得第一記憶體晶片31的底部表面及第一塔T1的最底部表面延伸超出第一半導體晶片21的頂部表面的邊緣（例如，最外部邊緣）。第二十一記憶體晶片51可安置於第二塔T2的最下端處。第二十一記憶體晶片51可被稱作第二塔T2的最下部主記憶體晶片。第二十一記憶體晶片51且因此第二塔T2可懸垂於第一半導體晶片21，使得第二十一記憶體晶片31的底部表面及第二塔T2的最底部表面延伸超出第一半導體晶片21的頂部表面的邊緣（例如，最外部邊緣）。第八記憶體晶片38可安置於第一塔T1的最上端處。第八記憶體晶片38可被稱作第一塔T1的最上部主記憶體晶片。第二十八記憶體晶片58可安置於第二塔T2的最上端處。第二十八記憶體晶片58可被稱作第二塔T2的最上部主記憶體晶片。
從俯視圖來看，第一記憶體晶片31的側表面可與第一間隔件27的側表面豎直對準。第一記憶體晶片31的側表面與第一間隔件27的側表面可實質上彼此共面。從俯視圖來看，第二十八記憶體晶片58的側表面可與第二間隔件28的側表面豎直對準。第二十八記憶體晶片58的側表面與第二間隔件28的側表面可實質上彼此共面。
多個第一黏著層72可安置於第一記憶體晶片31與第一半導體晶片21之間以及第二十一記憶體晶片51及第一半導體晶片21之間。選自多個第一黏著層72當中的一個第一黏著層72可附接於第一記憶體晶片31與第一半導體晶片21之間，且可延伸至或亦可形成於第一記憶體晶片31與第一間隔件27之間的區域中。舉例而言，黏著層可形成於第一記憶體晶片31與第一半導體晶片21之間，且黏著層可形成於第一記憶體晶片31與第一間隔件27之間。此兩個黏著層可為同一連續黏著層的部分，或可彼此分離。選自多個第一黏著層72當中的一個其他第一黏著層72可附接於第二十一記憶體晶片51與第一半導體晶片21之間，且可延伸至或亦可形成於第二十一記憶體晶片51與第二間隔件28之間的區域中。舉例而言，黏著層可形成於第二十一記憶體晶片51與第一半導體晶片21之間，且黏著層可形成於第二十一記憶體晶片51與第二間隔件28之間。此兩個黏著層可為同一連續黏著層的部分，或可彼此分離。
多個第一黏著層72可包含DAF或FOW。多個第一導電連接件81中的一些可延伸至多個第一黏著層72的內部部分。多個第一導電連接件81中的一些可部分地穿過多個第一黏著層72。多個第一黏著層72中的每一者可具有相對大於多個第二黏著層73中的每一者的豎直厚度的豎直厚度。
多個主記憶體晶片31至38以及51至58中的每一者可包含非揮發性記憶體裝置、揮發性記憶體裝置或其組合。多個主記憶體晶片31至38以及51至58中的每一者可包含NAND快閃記憶體、磁電阻隨機存取記憶體（magnetoresistive random access memory；MRAM）、相變隨機存取記憶體（phase-change random access memory；PRAM）、鐵電隨機存取記憶體（ferroelectric random access memory；FeRAM）、電阻性隨機存取記憶體（resistive random access memory；RRAM）、X點隨機存取記憶體（X-point random access memory；X點RAM）或其組合。多個主記憶體晶片31至38以及51至58中的每一者可包含DRAM、SRAM或其組合。
多個第二接墊85可分別形成於多個主記憶體晶片31至38以及51至58的第一表面上。多個第二接墊85可包含導電材料或由導電材料形成，所述導電材料諸如Cu、Al、W或其組合。第一記憶體晶片31至第八記憶體晶片38可依序堆疊。在實施例中，第一記憶體晶片31至第八記憶體晶片38可在朝向第一側表面S1的方向上依序偏移式排列。舉例來說，第一記憶體晶片31至第八記憶體晶片38可按級聯結構或階梯結構堆疊，以在朝向第一側表面S1的方向上以向上階梯方式延伸。
第二十一記憶體晶片51至第二十八記憶體晶片58可依序堆疊。在實施例中，第二十一記憶體晶片51至第二十八記憶體晶片58可在朝向第二側表面S2的方向上依序偏移式排列。第二十一記憶體晶片51至第二十八記憶體晶片58可在與第一記憶體晶片31至第八記憶體晶片38相反的方向上，例如在鏡像結構定向中偏移式排列。舉例來說，第二十一記憶體晶片51至第二十八記憶體晶片58可按級聯結構或階梯結構堆疊，以在朝向第二側表面S2的方向上以向上階梯方式延伸。在實施例中，第一記憶體晶片31至第八記憶體晶片38與第二十一記憶體晶片51至第二十八記憶體晶片58之間的間隔可在遠離第一半導體晶片21的方向上增加。舉例來說，第二記憶體晶片32與第二十二記憶體晶片52之間的距離可大於第一記憶體晶片31與第二十一記憶體晶片51之間的距離，且堆疊之間的相同豎直水平面上的晶片之間的各別距離可在遠離第一半導體晶片21的方向上增加。
多個第二黏著層73可分別附接於第一記憶體晶片31至第八記憶體晶片38中的每一記憶體晶片之間以及第二十一記憶體晶片51至第二十八記憶體晶片58中的每一晶片之間。多個第二黏著層73可包含底膠、DAF、FOW或其組合。多個第二黏著層73中的每一者可具有相對小於多個第一黏著層71中的每一者的豎直厚度的豎直厚度。
多個第二導電連接件83可安置於第一記憶體晶片31至第八記憶體晶片38的鄰近晶片之間以及第一記憶體晶片31與第一半導體晶片21之間，且可安置於第二十一記憶體晶片51至第二十八記憶體晶片58的鄰近晶片之間以及第二十一記憶體晶片51與第一半導體晶片21之間。第一組多個第二導電連接件83可接觸一組多個第二接墊85，且第二組多個第二導電連接件83可接觸一組第一接墊25。多個主記憶體晶片31至38以及51至58可經由多個第二接墊85、多個第二導電連接件83以及多個第一接墊25電連接至第一半導體晶片21。多個第二導電連接件83可包含接線、樑形引線、導電帶、導電間隔件、矽穿孔、焊球、焊料凸塊或其組合。在實施例中，多個第二導電連接件83可為接線，諸如金（Au）線或Al線。
多個第二導電連接件83中的一些可連接於第一記憶體晶片31至第八記憶體晶片38中的一者與封裝基底11之間。多個第二導電連接件83中的一些可接觸多個第二接墊85及多個第一接墊25。第一記憶體晶片31至第八記憶體晶片38可經由多個第二接墊85、多個第二導電連接件83以及多個第一接墊25電連接至封裝基底11。
多個第二導電連接件83中的一些可連接於第二十一記憶體晶片51至第二十八記憶體晶片58中的一者與封裝基底11之間。多個第二導電連接件83中的一些可接觸多個第二接墊85及多個第一接墊25。第二十一記憶體晶片51至第二十八記憶體晶片58可經由多個第二接墊85、多個第二導電連接件83以及多個第一接墊25電連接至封裝基底11。應理解，當元件被稱為「連接」或「耦接」至另一元件時或「在」另一元件「上」時，所述元件可直接連接或耦接至另一元件或在另一元件上，或可存在介入元件。相比之下，當元件被稱為「直接連接」或「直接耦接」至另一元件，或被稱作「接觸」另一元件或「與」另一元件「接觸」時，接觸點處不存在介入元件。
密封體91可覆蓋封裝基底11。第一塔T1、第二塔T2、第一半導體晶片21、第一間隔件27以及第二間隔件28可安置於密封體91中。
根據本揭露的實施例的半導體封裝的水平寬度（例如，在諸如X方向的第一方向上）可為第一寬度W1。第一寬度W1可定義為第一側表面S1與第二側表面S2之間的間隔或距離。可基於封裝基底11及/或密封體91而判定第一寬度W1。可基於行業標準而判定第一寬度W1。第一半導體晶片21與第一記憶體晶片31之間的重疊區（從俯視圖來看）的水平寬度（例如，在X方向上）可為第二寬度W2。第二十一半導體晶片51與第一記憶體晶片31之間的重疊區（從俯視圖來看）的水平寬度（例如，在X方向上）可與第二寬度W2實質上相同。
第一側表面S1與第八記憶體晶片38之間的間隔或距離（例如，在X方向上）（從俯視圖來看）可為第三寬度W3。在實施例中，可基於封裝基底11而判定第一側表面S1及第二側表面S2。第三寬度W3可對應於第八記憶體晶片38與穿過第一側表面S1且垂直於封裝基底11的頂部表面（例如，在Z方向上）的延長線之間的最小距離（例如，在X方向上且從俯視圖來看）。第二側表面S2與第二十八記憶體晶片58之間的間隔或距離（例如，在X方向上）（從俯視圖來看）可與第三寬度W3實質上相同。在實施例中，第三寬度W3對應於從俯視圖來看在X方向上的第一記憶體晶片31至第八記憶體晶片38中的每一者與穿過第一側表面S1且垂直於封裝基底11的頂部表面的延長線之間的最小間隔。
第一記憶體晶片31與穿過第一半導體晶片21的中心且垂直於封裝基底11的頂部表面的延長線之間的間隔可為第四寬度W4。第二十一記憶體晶片51與穿過第一半導體晶片21的中心且垂直於封裝基底11的頂部表面的延長線之間的間隔可為第五寬度W5。在實施例中，第五寬度W5可與第四寬度W4實質上相同。第一記憶體晶片31與第二十一記憶體晶片51之間的間隔可為第六寬度W6。在實施例中，第六寬度W6可為第四寬度W4及第五寬度W5的總和。第一塔T1的水平寬度可為第七寬度W7。第二塔T2的水平寬度可與第七寬度W7實質上相同。
第二寬度W2可大於0毫米且小於第一寬度W1的一半。在實施例中，第一記憶體晶片31及第二十一記憶體晶片51中的每一者可與多個第一接墊25中的一些對應第一接墊25的上部部分重疊（例如，在使用基底穿孔將第一半導體晶片21連接至封裝基底11的情形中）。在一些實施例中，第二寬度W2可大於約0.2毫米且小於第一寬度W1的一半。可基於對技術可靠性的限制而判定第三寬度W3。第三寬度W3可大於0毫米且等於或小於第二寬度W2。在實施例中，第三寬度W3可大於約0.1毫米且小於或等於第二寬度W2。在實施例中，第二寬度W2可大於或等於第三寬度W3且小於第一寬度W1的一半。術語諸如「約」或「大致」可反映僅以較小的相對方式及/或以並不會顯著地更改某些元件的操作、功能或結構的方式變化的量、大小、定向或佈局。舉例而言，自「約0.1至約1」的範圍可涵蓋諸如0.1左右的0%至5%的偏差及1左右的0%至5%的偏差的範圍，尤其在此偏差維持與所列範圍相同的效果的情況下。
第一記憶體晶片31至第八記憶體晶片38以及第二十一記憶體晶片51至第二十八記憶體晶片58在Y方向上的寬度可彼此實質上相同且可大於第一半導體晶片21的寬度。第一間隔件27及第二間隔件28在Y方向上的寬度與第一記憶體晶片31至第八記憶體晶片38以及第二十一記憶體晶片51至第二十八記憶體晶片58在Y方向上的寬度實質上相同，或可小於第一記憶體晶片31至第八記憶體晶片38以及第二十一記憶體晶片51至第二十八記憶體晶片58在Y方向上的寬度且大於第一半導體晶片21在Y方向上的寬度。
第一半導體晶片、第一間隔件27以及第二間隔件28的與第一塔T1及第二塔T2的最底部記憶體晶片31及最底部記憶體晶片51重疊的部分可描述為支撐件、支撐部分或支撐結構。第一塔T1的一側可由由第一間隔件27的部分或全部形成的支撐件支撐，且第一塔T1的另一側可由由第一半導體晶片21的部分形成的支撐件支撐。第二塔T2的一側可由由第二間隔件28的部分或全部形成的支撐件支撐，且第二塔T2的另一側可由由第一半導體晶片21的部分形成的支撐件支撐。
根據本揭露的實施例，第七寬度W7的大小可藉由控制第二寬度W2的大小而最大化。裝備於第一塔T1及第二塔T2中的記憶體晶片的數目可基於增大第七寬度W7的大小而增加。多個主記憶體晶片31至38以及51至58可經由多個第二導電連接件83電連接至第一半導體晶片21。可縮短根據本揭露的實施例的半導體封裝的信號傳送路徑。
圖3為用於描述根據本揭露的實施例的半導體封裝的橫截面圖，且圖4為用於描述根據本揭露的實施例的半導體封裝的佈局。
參考圖3及圖4，第一記憶體晶片31與第二十一記憶體晶片51之間的間隔可為第六寬度W6。可基於技術可靠性的限制而判定第六寬度W6的最小值。在實施例中，第六寬度W6的最小值可大於多個第一接墊25中的每一者的水平寬度。第六寬度W6的最小值可大於約0.1毫米。
圖5至圖8為用於描述根據本揭露的實施例的製造半導體封裝的方法的橫截面圖。
參考圖5，根據本揭露的實施例的製造半導體封裝的方法可包含藉由使用基底黏著層71將第一半導體晶片21安裝於封裝基底11上的製程，所述封裝基底11包含第一側表面S1及第二側表面S2。多個第一導電連接件81可形成於第一半導體晶片21的多個第一接墊25與封裝基底11的多個基底接墊15之間。儘管第一導電連接件81經描繪為接線，但在一些實施例中，其可為基底穿孔。
參考圖6，第一間隔件27及第二間隔件28可藉由使用基底黏著層71而附接於封裝基底11上。
參考圖7，彼此隔開的第一塔T1及第二塔T2可安置於第一半導體晶片21、第一間隔件27以及第二間隔件28上。多個第一黏著層72可附接於第一記憶體晶片31與第一半導體晶片21之間、第一記憶體晶片31與第一間隔件27之間、第二十一記憶體晶片51與第一半導體晶片21之間，以及第二十一記憶體晶片51與第二間隔件28之間。在一些實施例中（例如，若使用線接合），多個第一導電連接件81可部分地穿過多個第一黏著層72。舉例而言，第一黏著層72可為DAF或FOW。
多個第二黏著層73可附接於第一記憶體晶片31至第八記憶體晶片38中的每一晶片之間以及第一記憶體晶片31與第一半導體晶片21之間，以及第二十一記憶體晶片51至第二十八記憶體晶片58中的每一晶片之間以及第二十一記憶體晶片51與第一半導體晶片21之間。多個第二導電連接件83可形成於第一記憶體晶片31至第八記憶體晶片38與第一半導體晶片21之間以及第二十一記憶體晶片51至第二十八記憶體晶片58與第一半導體晶片21之間。多個第二導電連接件83中的每一者可接觸多個第二接墊85中的一對第二接墊85，或可接觸多個第二接墊85中的第二接墊85及多個第一接墊25中的第一接墊25。
參考圖8，形成覆蓋封裝基底11的密封體91。舉例而言，密封體91可包含環氧模製化合物。多個外部端子17接著可形成於封裝基底11的一個表面（例如，底部表面）上。多個外部端子17可連接至多個基底佈線13。多個外部端子17可包含例如焊球、焊料凸塊、接腳柵格陣列、導線柵格陣列、導電分接頭或其組合。在實施例中，可省略多個外部端子17。
圖9至圖15為用於描述根據本揭露的實施例的半導體封裝的橫截面圖。
參考圖9，根據本揭露的實施例的半導體封裝可包含封裝基底11、第一半導體晶片21、第一間隔件27、第二間隔件28、多個主記憶體晶片31至38以及51至58、多個基底黏著層71、多個第一黏著層72、多個第二黏著層73、多個第一導電連接件81、多個第二導電連接件83、密封體91以及多個虛設晶片94。
在實施例中，多個虛設晶片94可安置於第八記憶體晶片38及第二十八記憶體晶片58上。多個虛設晶片94中的每一者可包含與多個主記憶體晶片31至38以及51至58中的每一者的大小及組態類似的大小及組態。多個虛設晶片94可分散多個主記憶體晶片31至38以及51至58的應力。多個虛設晶片94中的每一者可充當散熱盤。多個虛設晶片94可安置於密封體91中。在實施例中，多個虛設晶片94可暴露於密封體91的側表面及/或頂部表面處。在一個實施例中，多個虛設晶片不以通信方式連接至每一塔中的任何其他晶片。
參考圖10，第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33以及第四記憶體晶片34可藉由使用選自多個第二導電連接件83中的至少一個第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個對應第一接墊25。第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37以及第八記憶體晶片38可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。
第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53以及第二十四記憶體晶片54可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57以及第二十八記憶體晶片58可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。
參考圖11，根據本揭露的實施例的半導體封裝可包含封裝基底11、第一半導體晶片21、第二半導體晶片22、第三半導體晶片23、多個主記憶體晶片31至46以及51至66、多個基底黏著層71、多個第一黏著層72、多個第二黏著層73、多個第一導電連接件81、多個第二導電連接件83，以及密封體91。第二半導體晶片22及第三半導體晶片23中的每一者可包含與第一半導體晶片21的組態類似的組態。
多個基底黏著層71可附接於第一半導體晶片21與封裝基底11之間、第二半導體晶片22與封裝基底11之間，以及第三半導體晶片23與封裝基底11之間。第一半導體晶片21、第二半導體晶片22以及第三半導體晶片23的頂部表面可實質上彼此共面。第二半導體晶片22可安置於半導體封裝的第一半導體晶片21與第一側表面S1之間。第三半導體晶片23可安置於半導體封裝的第一半導體晶片21與第二側表面S2與之間。
多個第一導電連接件81可分別連接於封裝基底11與第一半導體晶片21、第二半導體晶片22以及第三半導體晶片23之間。多個第一導電連接件81可接觸多個第一接墊25及多個基底接墊15。第一半導體晶片21、第二半導體晶片22以及第三半導體晶片23中的每一者可經由多個第一接墊25、多個第一導電連接件81以及多個基底接墊15電連接至封裝基底11。
從俯視圖來看，第一塔T1可與第一半導體晶片21及第二半導體晶片22重疊。第一塔T1可包含第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33、第四記憶體晶片34、第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37、第八記憶體晶片38、第九記憶體晶片39、第十記憶體晶片40、第十一記憶體晶片41、第十二記憶體晶片42、第十三記憶體晶片43、第十四記憶體晶片44、第十五記憶體晶片45以及第十六記憶體晶片46。第一記憶體晶片31至第十六記憶體晶片46可依序堆疊。第一記憶體晶片31至第八記憶體晶片38可在朝向第一側表面S1的方向上依序偏移式排列，使得其在朝向第一側表面S1的方向上以向上階梯方式依序堆疊。第九記憶體晶片39至第十六記憶體晶片46可在朝向第二側表面S2的方向依序偏移式排列，使得其在朝向第二側表面S2的方向上以向上階梯方式依序堆疊。
從俯視圖來看，第二塔T2可與第一半導體晶片21及第三半導體晶片23重疊。第二塔T2可包含第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53、第二十四記憶體晶片54、第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57、第二十八記憶體晶片58、第二十九記憶體晶片59、第三十記憶體晶片60、第三十一記憶體晶片61、第三十二記憶體晶片62、第三十三記憶體晶片63、第三十四記憶體晶片64、第三十五記憶體晶片65以及第三十六記憶體晶片66。第二十一記憶體晶片51至第三十六記憶體晶片66可依序堆疊。第二十一記憶體晶片51至第二十八記憶體晶片58可在朝向第二側表面S2的方向依序偏移式排列，使得其在朝向第二側表面S2的方向上以向上階梯方式依序堆疊。第二十九記憶體晶片59至第三十六記憶體晶片66可在朝向第一側表面S1的方向上依序偏移式排列，使得其在朝向第一側表面S1的方向上以向上階梯方式依序堆疊。
從俯視圖來看，第一記憶體晶片31可與第一半導體晶片21及第二半導體晶片22重疊。從俯視圖來看，第二十一記憶體晶片51可與第一半導體晶片21及第三半導體晶片23重疊。除分別以電氣方式及以通信方式連接至兩個塔T1及T2之外，第二半導體晶片22及第三半導體晶片23可充當實體支撐結構，且可各自描述為支撐件或支撐結構，或描述為包含支撐部分。多個第一黏著層72可附接於第一記憶體晶片31與第一半導體晶片21之間、第一記憶體晶片31與第二半導體晶片22之間、第二十一記憶體晶片51與第一半導體晶片21之間，以及第二十一記憶體晶片51與第三半導體晶片23之間。多個第二黏著層73可附接於第一記憶體晶片31至第十六記憶體晶片46與第二十一記憶體晶片51至第三十六記憶體晶片66之間。
多個第二導電連接件83可安置於第一記憶體晶片31至第八記憶體晶片38與第一半導體晶片21之間、第九記憶體晶片39至第十六記憶體晶片46與第二半導體晶片22之間、第二十一記憶體晶片51至第二十八記憶體晶片58與第一半導體晶片21之間，以及第二十一記憶體晶片51至第三十六記憶體晶片66與第三半導體晶片23之間。
參考圖12，第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33以及第四記憶體晶片34可藉由使用選自多個第二導電連接件83中的至少一個第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個對應第一接墊25。第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37以及第八記憶體晶片38可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。
第九記憶體晶片39、第十記憶體晶片40、第十一記憶體晶片41以及第十二記憶體晶片42可藉由使用選自多個第二導電連接件83中的至少一個第二導電連接件83連接至第二半導體晶片22的多個第一接墊25中的至少一個對應第一接墊25。第十三記憶體晶片43、第十四記憶體晶片44、第十五記憶體晶片45以及第十六記憶體晶片46可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第二半導體晶片22的多個第一接墊25中的至少一個其他對應第一接墊25。
第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53以及第二十四記憶體晶片54可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57以及第二十八記憶體晶片58可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。
第二十九記憶體晶片59、第三十記憶體晶片60、第三十一記憶體晶片61以及第三十二記憶體晶片62可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第三半導體晶片23的多個第一接墊25中的至少一個對應第一接墊25。第三十三記憶體晶片63、第三十四記憶體晶片64、第三十五記憶體晶片65以及第三十六記憶體晶片66可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第三半導體晶片23的多個第一接墊25中的至少一個其他對應第一接墊25。
參考圖13，第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33以及第四記憶體晶片34可在朝向根據本揭露的實施例的半導體封裝的第一側表面S1的方向上依序偏移式排列。第一記憶體晶片31、第二記憶體晶片32、第三記憶體晶片33以及第四記憶體晶片34可藉由使用選自多個第二導電連接件83中的至少一個第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個對應第一接墊25。
第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37以及第八記憶體晶片38可在朝向根據本揭露的實施例的半導體封裝的第二側表面S2的方向上依序偏移式排列。第五記憶體晶片35、第六記憶體晶片36、第七記憶體晶片37以及第八記憶體晶片38可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第二半導體晶片22的多個第一接墊25中的至少一個對應第一接墊25。
第九記憶體晶片39、第十記憶體晶片40、第十一記憶體晶片41以及第十二記憶體晶片42可在朝向根據本揭露的實施例的半導體封裝的第一側表面S1的方向上依序偏移式排列。第九記憶體晶片39、第十記憶體晶片40、第十一記憶體晶片41以及第十二記憶體晶片42可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。
第十三記憶體晶片43、第十四記憶體晶片44、第十五記憶體晶片45以及第十六記憶體晶片46可在朝向根據本揭露的實施例的半導體封裝的第二側表面S2的方向上依序偏移式排列。第十三記憶體晶片43、第十四記憶體晶片44、第十五記憶體晶片45以及第十六記憶體晶片46可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第二半導體晶片22的多個第一接墊25中的至少一個其他對應第一接墊25。
第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53以及第二十四記憶體晶片54可在朝向根據本揭露的實施例的半導體封裝的第二側表面S2的方向上依序偏移式排列。第二十一記憶體晶片51、第二十二記憶體晶片52、第二十三記憶體晶片53以及第二十四記憶體晶片54可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。
第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57以及第二十八記憶體晶片58可在朝向根據本揭露的實施例的半導體封裝的第一側表面S1的方向上依序偏移式排列。第二十五記憶體晶片55、第二十六記憶體晶片56、第二十七記憶體晶片57以及第二十八記憶體晶片58可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第三半導體晶片23的多個第一接墊25中的至少一個對應第一接墊25。
第二十九記憶體晶片59、第三十記憶體晶片60、第三十一記憶體晶片61以及第三十二記憶體晶片62可在朝向根據本揭露的實施例的半導體封裝的第二側表面S2的方向上依序偏移式排列。第二十九記憶體晶片59、第三十記憶體晶片60、第三十一記憶體晶片61以及第三十二記憶體晶片62可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。
第三十三記憶體晶片63、第三十四記憶體晶片64、第三十五記憶體晶片65以及第三十六記憶體晶片66可在朝向根據本揭露的實施例的半導體封裝的第一側表面S1的方向上依序偏移式排列。第三十三記憶體晶片63、第三十四記憶體晶片64、第三十五記憶體晶片65以及第三十六記憶體晶片66可藉由使用選自多個第二導電連接件83中的至少一個其他第二導電連接件83連接至第三半導體晶片23的多個第一接墊25中的至少一個其他對應第一接墊25。
參考圖14，第一記憶體晶片31至第八記憶體晶片38可Z形堆疊在第一記憶體晶片21及第二記憶體晶片22上。第二十一記憶體晶片51至第二十八記憶體晶片58可Z形堆疊在第一記憶體晶片21及第三記憶體晶片23上。舉例而言，第二記憶體晶片32可在朝向根據本揭露的實施例的半導體封裝的第一側表面S1的方向上在第一記憶體晶片31上偏移式排列。第三記憶體晶片33可在朝向根據本揭露的實施例的半導體封裝的第二側表面S2的方向上在第二記憶體晶片32上偏移式排列。第二十二記憶體晶片52可在朝向根據本揭露的實施例的半導體封裝的第二側表面S2的方向上在第二十一記憶體晶片51上偏移式排列。第二十三記憶體晶片53可在朝向根據本揭露的實施例的半導體封裝的第一側表面S1的方向上在第二十二記憶體晶片52上偏移式排列。
第一記憶體晶片31、第三記憶體晶片33、第五記憶體晶片35以及第七記憶體晶片37可藉由使用多個第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個對應第一接墊25。第二記憶體晶片32、第四記憶體晶片34、第六記憶體晶片36以及第八記憶體晶片38可藉由使用多個第二導電連接件83連接至第二半導體晶片22的多個第一接墊25中的至少一個對應第一接墊25。
第二十一記憶體晶片51、第二十三記憶體晶片53、第二十五記憶體晶片55以及第二十七記憶體晶片57可藉由使用多個第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個對應第一接墊25。第二十二記憶體晶片52、第二十四記憶體晶片54、第二十六記憶體晶片56以及第二十八記憶體晶片58可藉由使用多個第二導電連接件83連接至第三半導體晶片23的多個第一接墊25中的至少一個對應第一接墊25。
參考圖15，第一記憶體晶片31至第八記憶體晶片38可堆疊於第一記憶體晶片21及第二記憶體晶片22上，且可懸垂於第一記憶體晶片21及第二記憶體晶片22中的每一者。第二十一記憶體晶片51至第二十八記憶體晶片58可堆疊於第一記憶體晶片21及第三記憶體晶片23上，且可懸垂於第一記憶體晶片21及第三記憶體晶片23中的每一者。舉例而言，第一記憶體晶片31至第八記憶體晶片38可豎直對準以具有共面側表面。第二十一記憶體晶片51至第二十八記憶體晶片58可豎直對準以具有共面側表面。
多個第二黏著層73可附接於第一記憶體晶片31至第八記憶體晶片38之間以及第二十一記憶體晶片51至第二十八記憶體晶片58之間。多個第二黏著層73中的每一者可包含與多個第一黏著層72中的每一者實質上相同的厚度及實質上相同的材料。多個第一黏著層72及多個第二黏著層73可包含DAF或FOW。
第一記憶體晶片31至第八記憶體晶片38中的每一者可藉由使用多個第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個對應第一接墊25。第一記憶體晶片31至第八記憶體晶片38中的每一者可藉由使用多個第二導電連接件83連接至第二半導體晶片22的多個第一接墊25中的至少一個對應第一接墊25。
第二十一記憶體晶片51至第二十八記憶體晶片58中的每一者可藉由使用多個第二導電連接件83連接至第一半導體晶片21的多個第一接墊25中的至少一個其他對應第一接墊25。第二十一記憶體晶片51至第二十八記憶體晶片58中的每一者可藉由使用多個第二導電連接件83連接至第三半導體晶片23的多個第一接墊25中的至少一個對應第一接墊25。多個第二導電連接件83可延伸至多個第二黏著層73的內部部分。多個第二導電連接件83可部分地穿過多個第二黏著層73。
根據本揭露的實施例，可提供包含多個主記憶體晶片且彼此隔開的多個塔。多個塔中的每一者的最下部主記憶體晶片可與半導體晶片重疊。可實施易於提高整合程度及操作速度的半導體封裝。
在上文，本揭露的實施例已參考隨附圖式進行描述，但可理解，所屬領域中具通常知識者可在不改變本發明概念或必需特徵的情況下以另一詳細形成實施實施例。應理解，上文所描述的實施例僅為所有態樣中的實例且不受限制。
11:封裝基底 13:基底佈線 15:基底接墊 17:外部端子 21:第一半導體晶片 22:第二半導體晶片 23:第三半導體晶片 25:第一接墊 27:第一間隔件 28:第二間隔件 31、32、33、34、35、36、37、38、39、40、41、42、43、44、45、46、51、52、53、54、55、56、57、58、59、60、61、62、63、64、65、66:主記憶體晶片 71:基底黏著層 72:第一黏著層 73:第二黏著層 81:第一導電連接件 83:第二導電連接件 85:第二接墊 91:密封體 94:虛設晶片 S1:第一側表面 S2:第二側表面 T1:第一塔 T2:第二塔 W1:第一寬度 W2:第二寬度 W3:第三寬度 W4:第四寬度 W5:第五寬度 W6:第六寬度 W7:第七寬度 X、Y、Z:方向
圖1為用於描述根據本揭露的實施例的半導體封裝的橫截面圖。 圖2為用於描述根據本揭露的實施例的半導體封裝的佈局。 圖3為用於描述根據本揭露的實施例的半導體封裝的橫截面圖。 圖4為用於描述根據本揭露的實施例的半導體封裝的佈局。 圖5至圖8為用於描述根據本揭露的實施例的製造半導體封裝的方法的橫截面圖。 圖9至圖15為用於描述根據本揭露的實施例的半導體封裝的橫截面圖。
11:封裝基底
13:基底佈線
15:基底接墊
21:第一半導體晶片
25:第一接墊
27:第一間隔件
28:第二間隔件
31、32、33、34、35、36、37、38、51、52、53、54、55、56、57、58:主記憶體晶片
71:基底黏著層
72:第一黏著層
73:第二黏著層
81:第一導電連接件
83:第二導電連接件
85:第二接墊
91:密封體
S1:第一側表面
S2:第二側表面
T1:第一塔
T2:第二塔
W1:第一寬度
W2:第二寬度
W3:第三寬度
W4:第四寬度
W5:第五寬度
W6:第六寬度
W7:第七寬度
X、Y、Z:方向

Claims (21)

  1. 一種半導體封裝，包括： 封裝基底； 半導體晶片，位於所述封裝基底上； 多個第一導電連接件，將所述半導體晶片連接至所述封裝基底； 第一間隔件及第二間隔件，位於所述封裝基底上，所述第一間隔件及所述第二間隔件中的每一者與所述半導體晶片水平間隔開； 第一塔及第二塔，各自包含多個記憶體晶片，所述第一塔的所述多個記憶體晶片中的第一記憶體晶片安置於所述第一塔的最下端處且從俯視圖來看與所述半導體晶片及所述第一間隔件豎直地重疊，以及所述第二塔的所述多個記憶體晶片中的第二記憶體晶片安置於所述第二塔的最下端處且從俯視圖來看與所述半導體晶片及所述第二間隔件豎直地重疊；以及 多個第一黏著層，包含附接於所述第一記憶體晶片與所述半導體晶片之間的黏著層、附接於所述第一記憶體晶片與所述第一間隔件之間的黏著層、附接於所述第二記憶體晶片與所述半導體晶片之間的黏著層，以及附接於所述第二記憶體晶片與所述第二間隔件之間的黏著層。
  2. 如請求項1所述的半導體封裝，其中 所述封裝基底的水平寬度為第一寬度， 所述第一記憶體晶片與所述半導體晶片之間的重疊區的水平寬度為第二寬度，以及 所述第二寬度小於所述第一寬度的一半。
  3. 如請求項2所述的半導體封裝，其中所述第二寬度為約0.2毫米或超過0.2毫米。
  4. 如請求項2所述的半導體封裝，其中 所述封裝基底包括第一側表面及與所述第一側表面相對的第二側表面， 所述多個記憶體晶片中的任一者與穿過所述第一側表面且垂直於所述封裝基底的頂部表面的延長線之間的最小水平距離為第三寬度，以及 所述第三寬度大於0毫米且小於或等於所述第二寬度。
  5. 如請求項4所述的半導體封裝，其中所述第二寬度大於或等於所述第三寬度。
  6. 如請求項1所述的半導體封裝，其中 所述半導體晶片包括多個接墊，以及 從俯視圖來看，所述第一記憶體晶片及所述第二記憶體晶片中的每一者與所述多個接墊中的至少一者的上部部分重疊。
  7. 如請求項1所述的半導體封裝，其中所述多個第一導電連接件中的至少一些延伸至由所述多個第一黏著層形成的內部邊界內。
  8. 如請求項1所述的半導體封裝，其中所述多個第一黏著層包括直接黏著膜（DAF）或線上膜（FOW）。
  9. 如請求項1所述的半導體封裝，其中 所述封裝基底包括第一側表面及與所述第一側表面相對的第二側表面， 所述第一塔的所述多個記憶體晶片依序地且在朝向所述第一側表面的方向上以向上階梯方式堆疊，以及 所述第二塔的所述多個記憶體晶片依序地且在朝向所述第二側表面的方向上以向上階梯方式堆疊。
  10. 如請求項1所述的半導體封裝，其中 所述第一記憶體晶片的側表面與所述第一間隔件的側表面彼此共面，以及 所述第二記憶體晶片的側表面與所述第二間隔件的側表面彼此共面。
  11. 如請求項1所述的半導體封裝，其中所述半導體晶片的頂部表面與所述第一間隔件及所述第二間隔件的頂部表面彼此共面。
  12. 如請求項1所述的半導體封裝，其中所述半導體晶片包括緩衝器晶片、插入件晶片、控制器晶片、邏輯晶片或其組合。
  13. 如請求項1所述的半導體封裝，更包括將所述多個記憶體晶片連接至所述半導體晶片的多個第二導電連接件。
  14. 如請求項1所述的半導體封裝，更包括安置於成對的所述多個記憶體晶片之間的多個第二黏著層， 其中所述多個第一黏著層中的每一者的厚度厚於所述多個第二黏著層中的每一者的厚度。
  15. 一種半導體封裝，包括： 封裝基底； 半導體晶片，位於所述封裝基底上； 多個導電連接件，將所述半導體晶片連接至所述封裝基底； 彼此隔開的多個塔，各自包含多個記憶體晶片，所述多個塔中的每一者的所述多個記憶體晶片中的最下部記憶體晶片從俯視圖來看與所述半導體晶片重疊；以及 多個黏著層，附接於所述多個塔中的每一者的所述最下部記憶體晶片與所述半導體晶片之間。
  16. 如請求項15所述的半導體封裝，其中所述多個導電連接件延伸至由所述多個黏著層形成的內部邊界內。
  17. 如請求項15所述的半導體封裝，其中： 所述多個塔包含至少第一塔，其中所述第一塔的最底部表面與所述半導體晶片重疊且延伸超出所述半導體晶片的頂部表面的最外部邊緣。
  18. 如請求項15所述的半導體封裝，其中： 所述封裝基底包括第一側表面及與所述第一側表面相對的第二側表面， 所述多個塔中的第一塔的所述多個記憶體晶片依序地且在朝向所述第一側表面的方向上以向上階梯方式堆疊，以及 所述多個塔中的第二塔的所述多個記憶體晶片依序地且在朝向所述第二側表面的方向上以向上階梯方式堆疊。
  19. 一種半導體封裝，包括： 封裝基底； 在所述封裝基底上彼此水平間隔開的第一半導體晶片、第二半導體晶片以及第三半導體晶片； 多個第一導電連接件，將所述第一半導體晶片、所述第二半導體晶片與所述第三半導體晶片連接至所述封裝基底； 第一塔及第二塔，各自包含多個記憶體晶片，所述第一塔的所述多個記憶體晶片中的第一記憶體晶片安置於所述第一塔的最下端處且從俯視圖來看與所述第一半導體晶片及所述第二半導體晶片重疊，以及所述第二塔的所述多個記憶體晶片中的第二記憶體晶片安置於所述第二塔的最下端處且從俯視圖來看與所述第一半導體晶片及所述第三半導體晶片重疊；以及 多個第一黏著層，分別附接於所述第一記憶體晶片與所述第一半導體晶片之間、所述第一記憶體晶片與所述第二半導體晶片之間、所述第二記憶體晶片與所述第一半導體晶片之間，以及所述第二記憶體晶片與所述第三半導體晶片之間。
  20. 如請求項19所述的半導體封裝，其中 所述封裝基底包括第一側表面及與所述第一側表面相對的第二側表面， 所述第一塔的所述多個記憶體晶片依序堆疊，所述第一塔的所述多個記憶體晶片中的一些在朝向所述第一側表面的方向以向上階梯方式依序堆疊，且所述第一塔的所述多個記憶體晶片中的一些其他記憶體晶片在朝向所述第二側表面的方向上以向上階梯方式依序堆疊，以及 所述第二塔的所述多個記憶體晶片依序堆疊，所述第二塔的所述多個記憶體晶片中的一些在朝向所述第二側表面的方向以向上階梯方式依序堆疊，且所述第二塔的所述多個記憶體晶片中的一些其他記憶體晶片在朝向所述第一側表面的方向上以向上階梯方式依序堆疊。
  21. 如請求項19所述的半導體封裝，更包括將所述多個記憶體晶片連接至所述第一半導體晶片、所述第二半導體晶片與所述第三半導體晶片的多個第二導電連接件。
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