CN114497023A - 包括半导体芯片的半导体封装件 - Google Patents

包括半导体芯片的半导体封装件 Download PDF

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CN114497023A
CN114497023A CN202110830956.4A CN202110830956A CN114497023A CN 114497023 A CN114497023 A CN 114497023A CN 202110830956 A CN202110830956 A CN 202110830956A CN 114497023 A CN114497023 A CN 114497023A
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chip
semiconductor
memory
memory chip
semiconductor chip
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姜炫求
成载圭
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Samsung Electronics Co Ltd
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Samsung Electronics Co Ltd
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Abstract

一种半导体封装件可以包括封装衬底上的半导体芯片。半导体封装件可以包括：多个导电连接件，其将半导体芯片连接到封装衬底；多个塔，它们彼此间隔开，并且各自包括多个存储器芯片，其中，从俯视图来看，多个塔中的每一个中的最下面的存储器芯片与半导体芯片叠置。半导体封装件还包括附着在多个塔中的每一个中的最下面的存储器芯片与半导体芯片之间的多个粘合层。

Description

包括半导体芯片的半导体封装件
相关申请的交叉引用
本申请要求于2020年10月26日在韩国知识产权局提交的韩国专利申请No.10-2020-0139250的优先权，该申请的公开内容以引用方式全部并入本文中。
技术领域
本发明构思涉及一种包括多个半导体芯片的半导体封装件和制造半导体封装件的方法。
背景技术
正在研究配备有多个半导体芯片的各种半导体封装件。可以基于工业标准来使每个半导体封装件的尺寸标准化。随着配备在具有有限尺寸的半导体封装件中的半导体芯片的数量增加，容易提高集成度和操作速度。
发明内容
本公开的示例性实施例提供了一种配备有多个半导体芯片的半导体封装件和制造半导体封装件的方法。
根据本公开的实施例的半导体封装件可以包括封装衬底上的半导体芯片。半导体封装件可以另外包括：多个第一导电连接件，其将半导体芯片连接到封装衬底；封装衬底上的第一间隔件和第二间隔件，第一间隔件和第二间隔件中的每一个与半导体芯片水平间隔开；以及第一塔和第二塔。第一塔和第二塔中的每一个包括多个存储器芯片，第一存储器芯片设置在第一塔的最下端，并且从俯视图来看与半导体芯片和第一间隔件竖直地叠置，并且第二存储器芯片设置在第二塔的最下端，并且从俯视图来看与半导体芯片和第二间隔件竖直地叠置。半导体封装件还可以包括多个第一粘合层。多个第一粘合层包括附着在第一存储器芯片与半导体芯片之间的粘合层、附着在第一存储器芯片第一间隔件之间的粘合层、附着在第二存储器芯片与半导体芯片之间的粘合层、以及附着在第二存储器芯片与第二间隔件之间的粘合层。
根据本公开的实施例的半导体封装件可以包括封装衬底上的半导体芯片。半导体封装件可以包括：多个导电连接件，其将半导体芯片连接到封装衬底；多个塔，它们彼此间隔开并且各自包括多个存储器芯片，其中，从俯视图来看，多个塔中的每一个中的最下面的存储器芯片与半导体芯片叠置。半导体封装件还包括多个粘合层，其附着在多个塔中的每一个中的最下面的存储器芯片与半导体芯片之间。
根据本公开的实施例的半导体封装件可以包括封装衬底上的彼此水平间隔开的第一半导体芯片、第二半导体芯片和第三半导体芯片。半导体封装件可以包括：多个第一导电连接件，其将第一半导体芯片至第三半导体芯片连接到封装衬底；以及各自包括多个存储器芯片的第一塔和第二塔。从俯视图来看，设置在第一塔的最下端的第一存储器芯片可以与第一半导体芯片和第二半导体芯片叠置。从俯视图来看，设置在第二塔的最下端的第二存储器芯片可以与第一半导体芯片和第三半导体芯片叠置。多个第一粘合层可以分别附着在第一存储器芯片与第一半导体芯片之间、第一存储器芯片与第二半导体芯片之间、第二存储器芯片与第一半导体芯片之间、以及第二存储器芯片与第三半导体芯片之间。
附图说明
图1是用于描述根据本公开的实施例的半导体封装件的截面图。
图2是用于描述根据本公开的实施例的半导体封装件的布局。
图3是用于描述根据本公开的实施例的半导体封装件的截面图。
图4是用于描述根据本公开的实施例的半导体封装件的布局。
图5至图8是用于描述根据本公开的实施例的制造半导体封装件的方法的截面图。
图9至图15是用于描述根据本公开的实施例的半导体封装件的截面图。
具体实施方式
图1是用于描述根据本公开的实施例的半导体封装件的截面图。根据本公开的实施例的半导体封装件可以包括石棚状(Dolmen-like)结构(例如，反向结构)。
参照图1，根据本公开的实施例的半导体封装件可以包括封装衬底11、第一半导体芯片21、第一间隔件27、第二间隔件28、多个主存储器芯片31至38和51至58、多个衬底粘合层71、多个第一粘合层72、多个第二粘合层73、多个第一导电连接件81、多个第二导电连接件83和密封剂91。
半导体封装件可以包括第一侧表面S1和与第一侧表面S1相对的第二侧表面S2。可以基于封装衬底11和/或密封剂91来确定第一侧表面S1和第二侧表面S2。在实施例中，封装衬底11和密封剂91可以在第一侧表面S1和第二侧表面S2被暴露出来。封装衬底11和密封剂91的侧表面可以彼此基本共面。如本文中使用的术语“相同”、“相等”、“平面”或“共面”涵盖包括例如由于制造工艺而可能发生的变化的相同性或接近相同性。除非上下文或其他陈述另有指示，否则在本文中可以使用术语“基本上”来强调该含义。
封装衬底11可以包括多条衬底布线13和多个衬底焊盘15。第一半导体芯片21可以包括多个第一焊盘25。
为了便于描述，多个主存储器芯片31至38和51至58可以分别被称作第一存储器芯片31、第二存储器芯片32、第三存储器芯片33、第四存储器芯片34、第五存储器芯片35、第六存储器芯片36、第七存储器芯片37、第八存储器芯片38、第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53、第二十四存储器芯片54、第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57和第二十八存储器芯片58。第一存储器芯片31、第二存储器芯片32、第三存储器芯片33、第四存储器芯片34、第五存储器芯片35、第六存储器芯片36、第七存储器芯片37和第八存储器芯片38可以构造出第一塔T1。第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53、第二十四存储器芯片54、第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57和第二十八存储器芯片58可以构造出第二塔T2。显而易见，诸如“第一”、“第二”、“第三”等的序号可以简单地用作某些元件、步骤等的标签，以将这样的元件、步骤等彼此区分开。在说明书中未使用“第一”、“第二”等进行描述的术语在权利要求中仍可以被称为“第一”或“第二”。另外，用特定序号(例如，特定权利要求中的“第一”)引用的术语可以在其他地方用不同序号(例如，说明书或另一权利要求中的“第二”)来描述。特别地，关于本文中讨论的存储器芯片的堆叠，诸如“第二十一”、“第三十一”等的术语仅意味着作为标签。在堆叠芯片的上下文中，为了指定芯片堆叠中的位置，将使用诸如“定位”的术语，例如，从存储器芯片的堆叠件的底部开始的第一定位的存储器芯片、从存储器芯片的堆叠件的顶部开始的第三定位的存储器芯片、从存储器芯片的堆叠件的底部开始最后定位的存储器芯片等。
尽管图1中的每个堆叠件中示出了八个主存储器芯片，但是多个主存储器芯片31至38和51至58可以基于技术限制包括两个或更多个或者各种数量的存储器芯片。多个主存储器芯片31至38和51至58中的每一个可以包括多个第二焊盘85。
图2是用于描述根据本公开的实施例的半导体封装件的布局。
参照图2，根据本公开的实施例的半导体封装件可以包括封装衬底11、第一半导体芯片21、多个主存储器芯片31至38和51至58、多个第一导电连接件81以及多个第二导电连接件83。
封装衬底11可以包括多个衬底焊盘15(例如，封装衬底焊盘)。第一半导体芯片21可以包括多个第一焊盘25(例如，芯片焊盘)。第一存储器芯片31、第二存储器芯片32、第三存储器芯片33、第四存储器芯片34、第五存储器芯片35、第六存储器芯片36、第七存储器芯片37和第八存储器芯片38可以形成第一塔T1。第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53、第二十四存储器芯片54、第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57和第二十八存储器芯片58可以形成第二塔T2。第一塔T1和第二塔T2中的每一个可以相对于封装衬底11的顶表面具有成角度的取向。多个主存储器芯片31至38和51至58中的每一个可以包括多个第二焊盘85(例如，芯片焊盘)。多个主存储器芯片31至38和51至58中的每一个可以包括集成电路，其包括形成在由晶圆形成的半导体晶片上的存储器单元阵列。
再次参照图1和图2，封装衬底11可以包括刚性印刷电路板(PCB)、柔性PCB或刚性柔性PCB。封装衬底11可以是多层PCB。多条衬底布线13可以形成在封装衬底11的内部和表面上。多个衬底焊盘15可以形成在封装衬底11的顶表面上。多个衬底焊盘15可以包括手指电极或手指焊盘。多条衬底布线13和多个衬底焊盘15可以各自包括导电材料(诸如铜(Cu)、铝(Al)、钨(W)或它们的组合)或者由导电材料(诸如铜(Cu)、铝(Al)、钨(W)或它们的组合)形成。多个衬底焊盘15可以电连接到多条衬底布线13，并且可以形成在封装衬底11的外表面以连接在多条衬底布线13与主存储器芯片之间。
第一半导体芯片21、第一间隔件27和第二间隔件28中的每一个可以设置在封装衬底11上。多个衬底粘合层71可以附着在第一半导体芯片21与封装衬底11之间、第一间隔件27与封装衬底11之间、以及第二间隔件28与封装衬底11之间。多个衬底粘合层71可以包括底部填充物、粘合膜、直接粘合膜(DAF)、线上膜(FOW)或它们的组合。在一些实施例中，第一半导体芯片21、第一间隔件27和第二间隔件28对于其各自的衬底粘合层71都具有相同的材料。在其它实施例中，第一半导体芯片21、第一间隔件27和第二间隔件28中的至少一个对于其各自的衬底粘合层71与其它两个具有不同的材料。第一间隔件27和第二间隔件28中的每一个的竖直厚度可以与第一半导体芯片21的竖直厚度基本相同。第一半导体芯片21、第一间隔件27和第二间隔件28的顶表面可以基本彼此共面。
第一半导体芯片21可以包括形成在由晶圆形成的半导体晶片上的集成电路，并且可以包括缓冲芯片、插入器芯片、控制器芯片、逻辑芯片或它们的组合。在实施例中，第一半导体芯片21可以包括操作速度比多个主存储器芯片31至38和51至58中的每一个的操作速度相对更快的存储器。例如，第一半导体芯片21可以包括操作速度比多个主存储器芯片31至38和51至58中的每一个的操作速度相对更快的缓冲存储器装置，如静态随机存取存储器(SRAM)、动态随机存取存储器(DRAM)或它们的组合。第一半导体芯片21可以包括易失性存储器装置、非易失性存储器装置或它们的组合。多个第一焊盘25可以形成在第一半导体芯片21的一个表面上。多个第一焊盘25可以包括导电材料(诸如Cu、Al、W或它们的组合)或者由导电材料(诸如Cu、Al、W或它们的组合)形成。
第一间隔件27和第二间隔件28中的每一个可以包括竖直厚度与第一半导体芯片21的竖直厚度基本相同的虚设块(诸如虚设芯片)。虚设块或虚设芯片可以不执行电通信功能，而是可以用作物理支撑结构。在实施例中，第一间隔件27和第二间隔件28中的每一个可以包括PCB、金属板、塑料板或半导体衬底。第一间隔件27和第二间隔件28中的每一个可以被描述为支撑块或支撑柱。如该物理含义中使用的“块”指具有基本平坦的顶表面和底表面并且具有支撑形成在其上的结构的刚性的三维结构。
第一半导体芯片21的中心可以与封装衬底11的中心对准。在实施例中，第一半导体芯片21的中心可以相对于封装衬底11的中心(例如，从俯视图)竖直地对准。第一间隔件27可以设置在第一半导体芯片21与第一侧表面S1之间。第二间隔件28可以设置在第一半导体芯片21与第二侧表面S2之间。
多个第一导电连接件81可以设置在第一半导体芯片21与封装衬底11之间。多个第一导电连接件81可以各自接触多个第一焊盘25和多个衬底焊盘15中对应的一个。第一半导体芯片21可以经由多个第一焊盘25、多个第一导电连接件81和多个衬底焊盘15电连接到封装衬底11。多个第一导电连接件81可以包括键合接线、梁式引线、导电带、导电间隔件、衬底通孔件(例如，硅通孔件)、焊球、焊料凸块或它们的组合。例如，在一些实施例中，所有的第一导电连接件81是键合接线。在另一实施例中，第一导电连接件81中的每一个包括衬底通孔件和连接到衬底通孔件的焊料凸块或焊球。在实施例中，多个第一导电连接件81可以包括键合接线(诸如金(Au)接线或Al接线)。
彼此间隔开的第一塔T1和第二塔T2可以设置在第一半导体芯片21上。第二塔T2可以被设置为例如相对于第一半导体芯片21的中心与第一塔T1相对。从俯视图来看，第一塔T1的至少一部分可以与第一半导体芯片21叠置。从俯视图来看，第一塔T1可以与第一半导体芯片21和第一间隔件27叠置。从俯视图来看，第二塔T2的至少一部分可以与第一半导体芯片21叠置。从俯视图来看，第二塔T2可以与第一半导体芯片21和第二间隔件28叠置。在一些实施例中，在第一间隔件27、第一半导体芯片21和第二间隔件28之间的延伸的方向上，第一塔T1(也被描述为芯片的第一堆叠件)的重心可以与第一间隔件27的中心对准或者位于第一间隔件27的中心与第一半导体芯片21的中心之间。相似地，在第一间隔件27、第一半导体芯片21和第二间隔件28之间延伸的方向上，第二塔T2(也被描述为芯片的第二堆叠件)的重心可以与第二间隔件28的中心对准或者位于第二间隔件28的中心与第一半导体芯片21的中心之间。
第一存储器芯片31可以设置在第一塔T1的最下端。第一存储器芯片31可以被称作第一塔T1的最下面的主存储器芯片。第一存储器芯片31(因此，第一塔T1)可以悬在第一半导体芯片21上，使得第一存储器芯片31的底表面和第一塔T1的最底部表面延伸超过第一半导体芯片21的顶表面的边缘(例如，最外边缘)。第二十一存储器芯片51可以设置在第二塔T2的最下端。第二十一存储器芯片51可以被称作第二塔T2的最下面的主存储器芯片。第二十一存储器芯片51(因此，第二塔T2)可以悬在第一半导体芯片21上，使得第二十一存储器芯片31的底表面和第二塔T2的最底部表面延伸超过第一半导体芯片21的顶表面的边缘(例如，最外边缘)。第八存储器芯片38可以设置在第一塔T1的最上端部。第八存储器芯片38可以被称作第一塔T1的最上主存储器芯片。第二十八存储器芯片58可以设置在第二塔T2的最上端部。第二十八存储器芯片58可以被称作第二塔T2的最上主存储器芯片。
从俯视图来看，第一存储器芯片31的侧表面可以与第一间隔件27的侧表面竖直对齐。第一存储器芯片31的侧表面和第一间隔件27的侧表面可以基本彼此共面。从俯视图来看，第二十八存储器芯片58的侧表面可以与第二间隔件28的侧表面竖直对齐。第二十八存储器芯片58的侧表面和第二间隔件28的侧表面可以基本彼此共面。
多个第一粘合层72可以设置在第一存储器芯片31与第一半导体芯片21之间以及第二十一存储器芯片51与第一半导体芯片21还之间。从多个第一粘合层72选择的一个第一粘合层72可以附着在第一存储器芯片31与第一半导体芯片21之间，并且可以延伸到第一存储器芯片31与第一间隔件27之间的区域或者还可以形成在第一存储器芯片31与第一间隔件27之间的区域中。例如，粘合层可以形成在第一存储器芯片31与第一半导体芯片21之间，并且粘合层可以形成在第一存储器芯片31与第一间隔件27之间。这两个粘合层可以是相同的连续的粘合层的一部分，或者可以彼此分离。从多个第一粘合层72选择的另一个第一粘合层72可以附着在第二十一存储器芯片51与第一半导体芯片21之间，并且可以延伸到第二十一存储器芯片51与第二间隔件28之间的区域，或者也可以形成在第二十一存储器芯片51与第二间隔件28之间的区域中。例如，粘合层可以形成在第二十一存储器芯片51与第一半导体芯片21之间，并且粘合层可以形成在第二十一存储器芯片51与第二间隔件28之间。这两个粘合层可以是相同的连续的粘合层的一部分，或者可以彼此分离。
多个第一粘合层72可以包括DAF或FOW。多个第一导电连接件81中的一些可以延伸到多个第一粘合层72的内部。多个第一导电连接件81中的一些可以部分穿过多个第一粘合层72。多个第一粘合层72中的每一个可以具有相对大于多个第二粘合层73中的每一个的竖直厚度的竖直厚度。
多个主存储器芯片31至38和51至58中的每一个可以包括非易失性存储器装置、易失性存储器装置或它们的组合。多个主存储器芯片31至38和51至58中的每一个可以包括NAND闪存、磁阻随机存取存储器(MRAM)、相变随机存取存储器(PRAM)、铁电随机存取存储器(FeRAM)、电阻式随机存取存储器(RRAM)、X点随机存取存储器(X点RAM)或它们的组合。多个主存储器芯片31至38和51至58中的每一个可以包括DRAM、SRAM或它们的组合。
多个第二焊盘85可以分别形成在多个主存储器芯片31至38和51至58的第一表面上。多个第二焊盘85可以包括导电材料(诸如Cu、Al、W或它们的组合)或者由导电材料(诸如Cu、Al、W或它们的组合)形成。第一存储器芯片31至第八存储器芯片38可以顺序地堆叠。在实施例中，第一存储器芯片31至第八存储器芯片38可以在朝向第一侧表面S1的方向上顺序地偏移对准。例如，第一存储器芯片31至第八存储器芯片38可以以级联结构或阶梯结构堆叠，以在朝向第一侧表面S1的方向上以向上阶梯方式延伸。
第二十一存储器芯片51至第二十八存储器芯片58可以顺序地堆叠。在实施例中，第二十一存储器芯片51至第二十八存储器芯片58可以在朝向第二侧表面S2的方向上顺序地偏移对准。第二十一存储器芯片51至第二十八存储器芯片58可以在与第一存储器芯片31至第八存储器芯片38相对的方向上例如以镜像结构取向偏移对准。例如，第二十一存储器芯片51至第二十八存储器芯片58可以以级联结构或阶梯结构堆叠，以在朝向第二侧表面S2的方向上以向上阶梯方式延伸。在实施例中，第一存储器芯片31至第八存储器芯片38与第二十一存储器芯片51至第二十八存储器芯片58之间的间隔可以在远离第一半导体芯片21的方向上增大。例如，第二存储器芯片32与第二十二存储器芯片52之间的距离可以大于第一存储器芯片31与第二十一存储器芯片51之间的距离，堆叠件之间的同一竖直高度(level)上的芯片之间的相应距离可以在远离第一半导体芯片21的方向上增大。
多个第二粘合层73可以各自附着在第一存储器芯片31至第八存储器芯片38的每个存储器芯片之间以及第二十一存储器芯片51至第二十八存储器芯片58的每个存储器芯片之间。多个第二粘合层73可以包括底部填充物、DAF、FOW或它们的组合。多个第二粘合层73中的每一个可以具有比多个第一粘合层72中的每一个的竖直厚度相比更小的竖直厚度。
多个第二导电连接件83可以设置在第一存储器芯片31至第八存储器芯片38的相邻的芯片之间以及第一存储器芯片31与第一半导体芯片21之间，并且可以设置在第二十一存储器芯片51至第二十八存储器芯片58的相邻的芯片之间以及第二十一存储器芯片51与第一半导体芯片21之间。多个第二导电连接件83的第一组可以接触多个第二焊盘85的一组，多个第二导电连接件83的第二组可以接触第一焊盘25的一组。多个主存储器芯片31至38和51至58可以经由多个第二焊盘85、多个第二导电连接件83和多个第一焊盘25电连接到第一半导体芯片21。多个第二导电连接件83可以包括键合接线、梁式引线、导电带、导电间隔件、硅通孔件、焊球、焊料凸块或它们的组合。在实施例中，多个第二导电连接件83可以是键合接线(诸如金(Au)接线或Al接线)。
多个第二导电连接件83中的一些可以连接在第一存储器芯片31至第八存储器芯片38之一与封装衬底11之间。多个第二导电连接件83中的一些可以接触多个第二焊盘85和多个第一焊盘25。第一存储器芯片31至第八存储器芯片38可以经由多个第二焊盘85、多个第二导电连接件83和多个第一焊盘25电连接到封装衬底11。
多个第二导电连接件83中的一些可以连接在第二十一存储器芯片51至第二十八存储器芯片58之一与封装衬底11之间。多个第二导电连接件83中的一些可以接触多个第二焊盘85和多个第一焊盘25。第二十一存储器芯片51至第二十八存储器芯片58可以经由多个第二焊盘85、多个第二导电连接件83和多个第一焊盘25电连接到封装衬底11。将理解，当元件被称作“连接”或“耦合”到另一元件或者“在”另一元件“上”时，该元件可以直接连接或直接耦合到所述另一元件或者直接在所述另一元件上，或者可以存在其它元件或中间元件。相反，当元件被称作“直接连接”或“直接耦合”到另一元件或者被称作“接触”另一元件或者“与”另一元件“接触”时，在接触点不存在中间元件。
密封剂91可以覆盖封装衬底11。第一塔T1、第二塔T2、第一半导体芯片21、第一间隔件27和第二间隔件28可以设置在密封剂91中。
根据本公开的实施例的半导体封装件的水平宽度(例如，在诸如X方向的第一方向上)可以是第一宽度W1。第一宽度W1可以被限定为第一侧表面S1与第二侧表面S2之间的间隔或距离。可以基于封装衬底11和/或密封剂91来确定第一宽度W1。可以基于工业标准来确定第一宽度W1。第一半导体芯片21与第一存储器芯片31之间的叠置区域(从俯视图)的水平宽度(例如，在X方向上)可以是第二宽度W2。第二十一半导体芯片51与第一存储器芯片31之间的叠置区域(从俯视图)的水平宽度(例如，在X方向上)可以基本与第二宽度W2相同。
第一侧表面S1与第八存储器芯片38(从俯视图)之间的间隔或距离(例如，在X方向上)可以是第三宽度W3。在实施例中，可以基于封装衬底11来确定第一侧表面S1和第二侧表面S2。第三宽度W3可以对应于第八存储器芯片38与穿过第一侧表面S1并且垂直于封装衬底11的顶表面(例如，在Z方向上)的延伸线之间的最小距离(例如，在X方向上并且从俯视图)。第二侧表面S2与第二十八存储器芯片58(从俯视图)之间的间隔或距离(例如，在X方向上)可以基本与第三宽度W3相同。在实施例中，第三宽度W3可以对应于第一存储器芯片31至第八存储器芯片38中的每一个与穿过第一侧表面S1并且垂直于封装衬底11的顶表面的延伸线之间的从俯视图来看在X方向上的最小间隔。
第一存储器芯片31与穿过第一半导体芯片21的中心并且垂直于封装衬底11的顶表面的延伸线之间的间隔可以是第四宽度W4。第二十一存储器芯片51与穿过第一半导体芯片21的中心并且垂直于封装衬底11的顶表面的延伸线之间的间隔可以是第五宽度W5。在实施例中，第五宽度W5可以基本与第四宽度W4相同。第一存储器芯片31与第二十一存储器芯片51之间的间隔可以是第六宽度W6。在实施例中，第六宽度W6可以是第四宽度W4合第五宽度W5之和。第一塔T1的水平宽度可以是第七宽度W7。第二塔T2的水平宽度可以基本与第七宽度W7相同。
第二宽度W2可以大于0mm且小于第一宽度W1的一半。在实施例中，第一存储器芯片31和第二十一存储器芯片51中的每一个可以与多个第一焊盘25中的一些对应的第一焊盘25的上部叠置(例如，在其中衬底通孔件用于将第一半导体芯片21连接到封装衬底11的情况下)。在一些实施例中，第二宽度W2可以大于大约0.2mm且小于第一宽度W1的一半。可以基于技术可靠性的限制来确定第三宽度W3。第三宽度W3可以大于0mm且等于或小于第二宽度W2。在实施例中，第三宽度W3可以大于大约0.1mm且小于或等于第二宽度W2。在实施例中，第二宽度W2可以大于或等于第三宽度W3且小于第一宽度W1的一半。诸如“大约”或“近似”的术语可以反映仅以较小的相对方式和/或以不会显著更改特定元件的操作、功能或结构的方式变化的数量、尺寸、方向或布局。例如，从“大约0.1至大约1”的范围可以包含诸如0.1左右的0％-5％偏差和1左右的0％至5％偏差的范围，特别是如果这样的偏差维持与所列范围相同的效果。
第一存储器芯片31至第八存储器芯片38以及第二十一存储器芯片51至第二十八存储器芯片58在Y方向上的宽度可以基本彼此相同，并且可以大于第一半导体芯片21的宽度。第一间隔件27和第二间隔件28在Y方向上的宽度可以基本与第一存储器芯片31至第八存储器芯片38以及第二十一存储器芯片51至第二十八存储器芯片58在Y方向上的宽度相同，或者可以小于第一存储器芯片31至第八存储器芯片38以及第二十一存储器芯片51至第二十八存储器芯片58在Y方向上的宽度，并且大于第一半导体芯片21在Y方向上的宽度。
第一半导体芯片21、第一间隔件27和第二间隔件28的与第一塔T1和第二塔T2的最底部存储器芯片31和51叠置的一些部分可以被描述为支撑件、支撑部分或支撑结构。第一塔T1的一侧可以被由第一间隔件27的一部分或全部形成的支撑件支撑，第一塔T1的另一侧可以被由第一半导体芯片21的一部分形成的支撑件支撑。第二塔T2的一侧可以被由第二间隔件28的一部分或全部形成的支撑件支撑，第二塔T2的另一侧可以被由第一半导体芯片21的一部分形成的支撑件支撑。
根据本公开的实施例，可以通过控制第二宽度W2的尺寸来最小化第七宽度W7的尺寸。第一塔T1和第二塔T2中配备的存储器芯片的数量可以基于增大第七宽度W7的尺寸而增大。多个主存储器芯片31至38和51至58可以经由多个第二导电连接件83电连接到第一半导体芯片21。可以缩短根据本公开的实施例的半导体封装件的信号传输路径。
图3是用于描述根据本公开的实施例的半导体封装件的截面图，图4是用于描述根据本公开的实施例的半导体封装件的布局。
参照图3和图4，第一存储器芯片31与第二十一存储器芯片51之间的间隔可以是第六宽度W6。可以基于技术可靠性的限制来确定第六宽度W6的最小值。在实施例中，第六宽度W6的最小值可以大于多个第一焊盘25中的每一个的水平宽度。第六宽度W6的最小值可以大于大约0.1mm。
图5至图8是用于描述根据本公开的实施例的制造半导体封装件的方法的截面图。
参照图5，根据本公开的实施例的制造半导体封装件的方法可以包括通过使用衬底粘合层71在包括第一侧表面S1和第二侧表面S2的封装衬底11上安装第一半导体芯片21的工艺。可以在第一半导体芯片21的多个第一焊盘25与封装衬底11的多个衬底焊盘15之间形成多个第一导电连接件81。尽管第一导电连接件81被描绘为键合接线，但是在一些实施例中，它们可以是衬底通孔件。
参照图6，第一间隔件27和第二间隔件28可以通过使用衬底粘合层71附着在封装衬底11上。
参照图7，可以在第一半导体芯片21、第一间隔件27和第二间隔件28上设置彼此间隔开的第一塔T1和第二塔T2。多个第一粘合层72可以附着在第一存储器芯片31与第一半导体芯片21之间、第一存储器芯片31与第一间隔件27之间、第二十一存储器芯片51与第一半导体芯片21之间、以及第二十一存储器芯片51与第二间隔件28之间。在一些实施例(例如，如果使用接线键合)中，多个第一导电连接件81可以部分地穿过多个第一粘合层72。例如，第一粘合层72可以是DAF或FOW。
多个第二粘合层73可以附着在第一存储器芯片31至第八存储器芯片38中的每个芯片之间、第一存储器芯片31与第一半导体芯片21之间、第二十一存储器芯片51至第二十八存储器芯片58中的每个芯片之间以及第二十一存储器芯片51与第一半导体芯片21之间。可以在第一存储器芯片31至第八存储器芯片38与第一半导体芯片21之间以及第二十一存储器芯片51至第二十八存储器芯片58与第一半导体芯片21之间形成多个第二导电连接件83。多个第二导电连接件83中的每一个可以接触多个第二焊盘85中的一对第二焊盘85，或者可以接触多个第二焊盘85中的第二焊盘85和多个第一焊盘25中的第一焊盘25。
参照图8，形成覆盖封装衬底11的密封剂91。密封剂91可以包括例如环氧模制化合物。随后可以在封装衬底11的一个表面(例如，底表面)上形成多个外部端子17。多个外部端子17可以连接到多条衬底布线13。多个外部端子17可以包括例如焊球、焊料凸块、引脚栅格阵列、引线栅格阵列、导电带或它们的组合。在实施例中，可以省略多个外部端子17。
图9至图15是用于描述根据本公开的实施例的半导体封装件的截面图。
参照图9，根据本公开的实施例的半导体封装件可以包括封装衬底11、第一半导体芯片21、第一间隔件27、第二间隔件28、多个主存储器芯片31至38和51至58、多个衬底粘合层71、多个第一粘合层72、多个第二粘合层73、多个第一导电连接件81、多个第二导电连接件83、密封剂91和多个虚设芯片94。
在实施例中，多个虚设芯片94可以设置在第八存储器芯片38和第二十八存储器芯片58上。多个虚设芯片94中的每一个可以包括与多个主存储器芯片31至38和51至58中的每一个的尺寸和配置相似的尺寸和配置。多个虚设芯片94可以分散多个主存储器芯片31至38和51至58的应力。多个虚设芯片94中的每一个可以用作散热板。多个虚设芯片94可以设置在密封剂91中。在实施例中，多个虚设芯片94可以在密封剂91的侧表面和/或顶表面被暴露出来。在一个实施例中，多个虚设芯片不与每个塔中的芯片当中的任何其它芯片通信连接。
参照图10，第一存储器芯片31、第二存储器芯片32、第三存储器芯片33和第四存储器芯片34可以通过使用从多个第二导电连接件83选择的至少一个第二导电连接件83连接到第一半导体芯片21的多个第一焊盘25中的至少一个对应的第一焊盘25。第五存储器芯片35、第六存储器芯片36、第七存储器芯片37和第八存储器芯片38可以通过使用从多个第二导电连接件83选择的至少一个其他第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53和第二十四存储器芯片54可以通过使用从多个第二导电连接件83选择的至少一个其它第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57和第二十八存储器芯片58可以通过使用从多个第二导电连接件83选择的至少一个其它第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
参照图11，根据本公开的实施例的半导体封装件可以包括封装衬底11、第一半导体芯片21、第二半导体芯片22、第三半导体芯片23、多个主存储器芯片31至46和51至66、多个衬底粘合层71、多个第一粘合层72、多个第二粘合层73、多个第一导电连接件81、多个第二导电连接件83和密封剂91。第二半导体芯片22和第三半导体芯片23中的每一个可以包括与第一半导体芯片21的配置相似的配置。
多个衬底粘合层71可以附着在第一半导体芯片21与封装衬底11之间、第二半导体芯片22与封装衬底11之间、以及第三半导体芯片23与封装衬底11之间。第一半导体芯片21、第二半导体芯片22和第三半导体芯片23的顶表面可以基本彼此共面。第二半导体芯片22可以设置在半导体封装件的第一半导体芯片21与第一侧表面S1之间。第三半导体芯片23可以设置在半导体封装件的第一半导体芯片21与第二侧表面S2之间。
多个第一导电连接件81可以分别连接在封装衬底11与第一半导体芯片21、第二半导体芯片22和第三半导体芯片23之间。多个第一导电连接件81可以接触多个第一焊盘25和多个衬底焊盘15。第一半导体芯片21、第二半导体芯片22和第三半导体芯片23中的每一个可以经由多个第一焊盘25、多个第一导电连接件81和多个衬底焊盘15电连接到封装衬底11。
从俯视图来看，第一塔T1可以与第一半导体芯片21和第二半导体芯片22叠置。第一塔T1可以包括第一存储器芯片31、第二存储器芯片32、第三存储器芯片33、第四存储器芯片34、第五存储器芯片35、第六存储器芯片36、第七存储器芯片37、第八存储器芯片38、第九存储器芯片39、第十存储器芯片40、第十一存储器芯片41、第十二存储器芯片42、第十三存储器芯片43、第十四存储器芯片44、第十五存储器芯片45和第十六存储器芯片46。第一存储器芯片31至第十六存储器芯片46可以顺序地堆叠。第一存储器芯片31至第八存储器芯片38可以在朝向第一侧表面S1的方向上顺序地偏移对准，使得它们在朝向第一侧表面S1的方向上以向上阶梯方式顺序地堆叠。第九存储器芯片39至第十六存储器芯片46可以在朝向第二侧表面S2的方向上顺序地偏移对准，使得它们在朝向第二侧表面S2的方向上以向上阶梯方式顺序地堆叠。
从俯视图来看，第二塔T2可以与第一半导体芯片21和第三半导体芯片23叠置。第二塔T2可以包括第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53、第二十四存储器芯片54、第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57、第二十八存储器芯片58、第二十九存储器芯片59、第三十存储器芯片60、第三十一存储器芯片61、第三十二存储器芯片62、第三十三存储器芯片63、第三十四存储器芯片64、第三十五存储器芯片65和第三十六存储器芯片66。第二十一存储器芯片51至第三十六存储器芯片66可以顺序地堆叠。第二十一存储器芯片51至第二十八存储器芯片58可以在朝向第二侧表面S2的方向上顺序地偏移对准，使得它们在朝向第二侧表面S2的方向上以向上阶梯方式顺序地堆叠。第二十九存储器芯片59至第三十六存储器芯片66可以在朝向第一侧表面S1的方向上顺序地偏移对准，使得它们在朝向第一侧表面S1的方向上以向上阶梯方式顺序地堆叠。
从俯视图来看，第一存储器芯片31可以与第一半导体芯片21和第二半导体芯片22叠置。从俯视图来看，第二十一存储器芯片51可以与第一半导体芯片21和第三半导体芯片23叠置。除了分别电连接到并且通信连接到两个塔T1和T2之外，第二半导体芯片22和第三半导体芯片23可以用作物理支撑结构，并且可以每个被描述为支撑件或支撑结构，或者被描述为包括支撑部分。多个第一粘合层72可以附着在第一存储器芯片31与第一半导体芯片21之间、第一存储器芯片31与第二半导体芯片22之间、第二十一存储器芯片51与第一半导体芯片21之间、以及第二十一存储器芯片51与第三半导体芯片23之间。多个第二粘合层73可以附着在第一存储器芯片31至第十六存储器芯片46与第二十一存储器芯片51至第三十六存储器芯片66之间。
多个第二导电连接件83可以设置在第一存储器芯片31至第八存储器芯片38与第一半导体芯片21之间、第九存储器芯片31至第十六存储器芯片46与第二半导体芯片22之间、第二十一存储器芯片51至第二十八存储器芯片58与第一半导体芯片21之间、以及第二十一存储器芯片51至第三十六存储器芯片66与第三半导体芯片23之间。
参照图12，第一存储器芯片31、第二存储器芯片32、第三存储器芯片33和第四存储器芯片34可以通过使用从多个第二导电连接件83选择的至少一个第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个对应的第一焊盘25。第五存储器芯片35、第六存储器芯片36、第七存储器芯片37和第八存储器芯片38可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第九存储器芯片39、第十存储器芯片40、第十一存储器芯片41和第十二存储器芯片42可以通过使用从多个第二导电连接件83选择的至少一个第二导电连接件83来连接到第二半导体芯片22的多个第一焊盘25中的至少一个对应的第一焊盘25。第十三存储器芯片43、第十四存储器芯片44、第十五存储器芯片45和第十六存储器芯片46可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第二半导体芯片22的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53和第二十四存储器芯片54可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57和第二十八存储器芯片58可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第二十九存储器芯片59、第三十存储器芯片60、第三十一存储器芯片61和第三十二存储器芯片62可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第三半导体芯片23的多个第一焊盘25中的至少一个对应的第一焊盘25。第三十三存储器芯片63、第三十四存储器芯片64、第三十五存储器芯片65和第三十六存储器芯片66可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第三半导体芯片23的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
参照图13，第一存储器芯片31、第二存储器芯片32、第三存储器芯片33和第四存储器芯片34可以在朝向根据本公开的实施例的半导体封装件的第一侧表面S1的方向上顺序地偏移对准。第一存储器芯片31、第二存储器芯片32、第三存储器芯片33和第四存储器芯片34可以通过使用从多个第二导电连接件83选择的至少一个第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个对应的第一焊盘25。
第五存储器芯片35、第六存储器芯片36、第七存储器芯片37和第八存储器芯片38可以在朝向根据本公开的实施例的半导体封装件的第二侧表面S2的方向上顺序地偏移对准。第五存储器芯片35、第六存储器芯片36、第七存储器芯片37和第八存储器芯片38可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第二半导体芯片22的多个第一焊盘25中的至少一个对应的第一焊盘25。
第九存储器芯片39、第十存储器芯片40、第十一存储器芯片41和第十二存储器芯片42可以在朝向根据本公开的实施例的半导体封装件的第一侧表面S1的方向上顺序地偏移对准。第九存储器芯片39、第十存储器芯片40、第十一存储器芯片41和第十二存储器芯片42可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第十三存储器芯片43、第十四存储器芯片44、第十五存储器芯片45和第十六存储器芯片46可以在朝向根据本公开的实施例的半导体封装件的第二侧表面S2的方向上顺序地偏移对准。第十三存储器芯片43、第十四存储器芯片44、第十五存储器芯片45和第十六存储器芯片46可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第二半导体芯片22的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53和第二十四存储器芯片54可以在朝向根据本公开的实施例的半导体封装件的第二侧表面S2的方向上顺序地偏移对准。第二十一存储器芯片51、第二十二存储器芯片52、第二十三存储器芯片53和第二十四存储器芯片54可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57和第二十八存储器芯片58可以在朝向根据本公开的实施例的半导体封装件的第一侧表面S1的方向上顺序地偏移对准。第二十五存储器芯片55、第二十六存储器芯片56、第二十七存储器芯片57和第二十八存储器芯片58可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第三半导体芯片23的多个第一焊盘25中的至少一个对应的第一焊盘25。
第二十九存储器芯片59、第三十存储器芯片60、第三十一存储器芯片61和第三十二存储器芯片62可以在朝向根据本公开的实施例的半导体封装件的第二侧表面S2的方向上顺序地偏移对准。第二十九存储器芯片59、第三十存储器芯片60、第三十一存储器芯片61和第三十二存储器芯片62可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
第三十三存储器芯片63、第三十四存储器芯片64、第三十五存储器芯片65和第三十六存储器芯片66可以在朝向根据本公开的实施例的半导体封装件的第一侧表面S1的方向上顺序地偏移对准。第三十三存储器芯片63、第三十四存储器芯片64、第三十五存储器芯片65和第三十六存储器芯片66可以通过使用从多个第二导电连接件83选择的至少一个其它的第二导电连接件83来连接到第三半导体芯片23的多个第一焊盘25中的至少一个其它对应的第一焊盘25。
参照图14，第一存储器芯片31至第八存储器芯片38可以按之字形堆叠在第一半导体芯片21和第二半导体芯片22上。第二十一存储器芯片51至第二十八存储器芯片58可以按之字形堆叠在第一半导体芯片21和第三半导体芯片23上。例如，第二存储器芯片32可以在朝向根据本公开的实施例的半导体封装件的第一侧表面S1的方向上在第一存储器芯片31上偏移对准。第三存储器芯片33可以在朝向根据本公开的实施例的半导体封装件的第二侧表面S2的方向上在第二存储器芯片32上偏移对准。第二十二存储器芯片52可以在朝向根据本公开的实施例的半导体封装件的第二侧表面S2的方向上在第二十一存储器芯片51上偏移对准。第二十三存储器芯片53可以在朝向根据本公开的实施例的半导体封装件的第一侧表面S1的方向上在第二十二存储器芯片52上偏移对准。
第一存储器芯片31、第三存储器芯片33、第五存储器芯片35和第七存储器芯片37可以通过使用多个第二导电连接件83连接到第一半导体芯片21的多个第一焊盘25中的至少一个对应的第一焊盘25。第二存储器芯片32、第四存储器芯片34、第六存储器芯片36和第八存储器芯片38可以通过使用多个第二导电连接件83来连接到第二半导体芯片22的多个第一焊盘25中的至少一个对应的第一焊盘25。
第二十一存储器芯片51、第二十三存储器芯片53、第二十五存储器芯片55和第二十七存储器芯片57可以通过使用多个第二导电连接件83来连接到第一半导体芯片21的多个第一焊盘25中的至少一个对应的第一焊盘25。第二十二存储器芯片52、第二十四存储器芯片54、第二十六存储器芯片56和第二十八存储器芯片58可以通过使用多个第二导电连接件83连接到第三半导体芯片23的多个第一焊盘25中的至少一个对应的第一焊盘25。
参照图15，第一存储器芯片31至第八存储器芯片38可以堆叠在第一半导体芯片21和第二半导体芯片22上，并且可以悬在第一半导体芯片21和第二半导体芯片22中的每一个上。第二十一存储器芯片51至第二十八存储器芯片58可以堆叠在第一半导体芯片21和第三半导体芯片23上，并且可以悬在第一半导体芯片21和第三半导体芯片23中的每一个上。例如，第一存储器芯片31至第八存储器芯片38可以竖直地对准以具有共面侧表面。第二十一存储器芯片51至第二十八存储器芯片58可以竖直地对准以具有共面侧表面。
多个第二粘合层73可以附着在第一存储器芯片31至第八存储器芯片38之间以及第二十一存储器芯片51至第二十八存储器芯片58之间。多个第二粘合层73中的每一个可以包括与多个第一粘合层72中的每一个的厚度基本相同的厚度和与多个第一粘合层72中的每一个的材料基本相同的材料。多个第一粘合层72和多个第二粘合层73可以包括DAF或FOW。
第一存储器芯片31至第八存储器芯片38中的每一个可以通过使用多个第二导电连接件83连接到第一半导体芯片21的多个第一焊盘25中的至少一个对应的第一焊盘25。第一存储器芯片31至第八存储器芯片38中的每一个可以通过使用多个第二导电连接件83连接到第二半导体芯片22的多个第一焊盘25中的至少一个对应的第一焊盘25。
第二十一存储器芯片51至第二十八存储器芯片58中的每一个可以通过使用多个第二导电连接件83连接到第一半导体芯片21的多个第一焊盘25中的至少一个其它对应的第一焊盘25。第二十一存储器芯片51至第二十八存储器芯片58中的每一个可以通过使用多个第二导电连接件83连接到第三半导体芯片23的多个第一焊盘25中的至少一个对应的第一焊盘25。多个第二导电连接件83可以延伸到多个第二粘合层73的内部。多个第二导电连接件83可以部分地穿过多个第二粘合层73。
根据本公开的实施例，可以提供包括多个主存储器芯片并且彼此间隔开的多个塔。多个塔中的每一个中的最下面的主存储器芯片可以与半导体芯片叠置。可以实现容易提高集成度和操作速度的半导体封装件。
在上文中，已经参照附图描述了本公开的实施例，但是可以理解，本领域技术人员可以在不改变本发明构思或基本特征的情况下以另一详细的形式来实现实施例。应理解，上述实施例在所有方面仅是示例而不是限制。

Claims (21)

1.一种半导体封装件，包括：
封装衬底；
半导体芯片，其位于所述封装衬底上；
多个第一导电连接件，其将所述半导体芯片连接到所述封装衬底；
所述封装衬底上的第一间隔件和第二间隔件，所述第一间隔件和所述第二间隔件中的每一个与所述半导体芯片水平间隔开；
各自包括多个存储器芯片的第一塔和第二塔，第一存储器芯片设置在所述第一塔的最下端并且从俯视图来看与所述半导体芯片和所述第一间隔件竖直地叠置，并且第二存储器芯片设置在所述第二塔的最下端并且从俯视图来看与所述半导体芯片和所述第二间隔件竖直地叠置；以及
多个第一粘合层，其包括附着在所述第一存储器芯片与所述半导体芯片之间的粘合层、附着在所述第一存储器芯片与所述第一间隔件之间的粘合层、附着在所述第二存储器芯片与所述半导体芯片之间的粘合层和附着在所述第二存储器芯片与所述第二间隔件之间的粘合层。
2.根据权利要求1所述的半导体封装件，其中，
所述封装衬底的水平宽度为第一宽度，
所述第一存储器芯片与所述半导体芯片之间的叠置区域的水平宽度为第二宽度，并且
所述第二宽度小于所述第一宽度的一半。
3.根据权利要求2所述的半导体封装件，其中，所述第二宽度为0.2mm或更大。
4.根据权利要求2所述的半导体封装件，其中，
所述封装衬底包括第一侧表面和与所述第一侧表面相对的第二侧表面，
所述多个存储器芯片中的任意一个与穿过所述第一侧表面并且垂直于所述封装衬底的顶表面的延伸线之间的最小水平距离为第三宽度，并且
所述第三宽度大于0mm且小于或等于所述第二宽度。
5.根据权利要求4所述的半导体封装件，其中，所述第二宽度大于或等于所述第三宽度。
6.根据权利要求1所述的半导体封装件，其中，
所述半导体芯片包括多个焊盘，并且
从俯视图来看，所述第一存储器芯片和所述第二存储器芯片中的每一个与所述多个焊盘中的至少一个的上部叠置。
7.根据权利要求1所述的半导体封装件，其中，所述多个第一导电连接件中的至少一些延伸到由所述多个第一粘合层形成的内部边界内。
8.根据权利要求1所述的半导体封装件，其中，所述多个第一粘合层包括直接粘合膜或线上膜。
9.根据权利要求1所述的半导体封装件，其中，
所述封装衬底包括第一侧表面和与所述第一侧表面相对的第二侧表面，
所述第一塔的多个存储器芯片在朝向所述第一侧表面的方向上顺序地且以向上阶梯方式堆叠，并且
所述第二塔的多个存储器芯片在朝向所述第二侧表面的方向上顺序地且以向上阶梯方式堆叠。
10.根据权利要求1所述的半导体封装件，其中，
所述第一存储器芯片的侧表面和所述第一间隔件的侧表面彼此共面，并且
所述第二存储器芯片的侧表面和所述第二间隔件的侧表面彼此共面。
11.根据权利要求1所述的半导体封装件，其中，所述半导体芯片以及所述第一间隔件和所述第二间隔件的顶表面彼此共面。
12.根据权利要求1所述的半导体封装件，其中，所述半导体芯片包括缓冲芯片、插入器芯片、控制器芯片、逻辑芯片或它们的组合。
13.根据权利要求1所述的半导体封装件，还包括：多个第二导电连接件，其将所述第一塔和所述第二塔的多个存储器芯片连接到所述半导体芯片。
14.根据权利要求1所述的半导体封装件，还包括：多个第二粘合层，其设置在所述第一塔的多个存储器芯片的对之间和所述第二塔的多个存储器芯片的对之间，
其中，所述多个第一粘合层中的每一个的厚度比所述多个第二粘合层中的每一个的厚度更厚。
15.一种半导体封装件，包括：
封装衬底；
半导体芯片，其位于所述封装衬底上；
多个导电连接件，其将所述半导体芯片连接到所述封装衬底；
彼此间隔开的多个塔，所述多个塔各自包括多个存储器芯片，从俯视图来看，所述多个塔中的每一个中的最下面的存储器芯片与所述半导体芯片叠置；以及
多个粘合层，其附着在所述多个塔中的每一个中的最下面的存储器芯片与所述半导体芯片之间。
16.根据权利要求15所述的半导体封装件，其中，所述多个导电连接件延伸到由所述多个粘合层形成的内部边界内。
17.根据权利要求15所述的半导体封装件，其中：
所述多个塔至少包括第一塔，其中，所述第一塔的最底部表面与所述半导体芯片叠置，并且延伸超出所述半导体芯片的顶表面的最外边缘。
18.根据权利要求15所述的半导体封装件，其中：
所述封装衬底包括第一侧表面和与所述第一侧表面相对的第二侧表面，
所述多个塔中的第一塔的多个存储器芯片在朝向所述第一侧表面的方向上顺序地且以向上阶梯方式堆叠，并且
所述多个塔中的第二塔的多个存储器芯片在朝向所述第二侧表面的方向上顺序地且以向上阶梯方式堆叠。
19.一种半导体封装件，包括：
封装衬底；
所述封装衬底上的彼此水平间隔开的第一半导体芯片、第二半导体芯片和第三半导体芯片；
多个第一导电连接件，其将所述第一半导体芯片至所述第三半导体芯片连接到所述封装衬底；
各自包括多个存储器芯片的第一塔和第二塔，第一存储器芯片设置在所述第一塔的最下端并且从俯视图来看与所述第一半导体芯片和所述第二半导体芯片叠置，并且第二存储器芯片设置在所述第二塔的最下端并且从俯视图来看与所述第一半导体芯片和所述第三半导体芯片叠置；以及
多个第一粘合层，其分别附着在所述第一存储器芯片与所述第一半导体芯片之间、所述第一存储器芯片与所述第二半导体芯片之间、所述第二存储器芯片与所述第一半导体芯片之间、以及所述第二存储器芯片与所述第三半导体芯片之间。
20.根据权利要求19所述的半导体封装件，其中，
所述封装衬底包括第一侧表面和与所述第一侧表面相对的第二侧表面，
所述第一塔的多个存储器芯片顺序地堆叠，所述第一塔的多个存储器芯片中的一些在朝向所述第一侧表面的方向上顺序地且以向上阶梯方式堆叠，并且所述第一塔的多个存储器芯片中的一些其它存储器芯片在朝向所述第二侧表面的方向上顺序地且以向上阶梯方式堆叠，并且
所述第二塔的多个存储器芯片顺序地堆叠，所述第二塔的多个存储器芯片中的一些在朝向所述第二侧表面的方向上顺序地且以向上阶梯方式堆叠，并且所述第二塔的多个存储器芯片中的一些其它存储器芯片在朝向所述第一侧表面的方向上顺序地且以向上阶梯方式堆叠。
21.根据权利要求19所述的半导体封装件，还包括：多个第二导电连接件，其将所述第一塔和第二塔的多个存储器芯片连接到所述第一半导体芯片至所述第三半导体芯片。
CN202110830956.4A 2020-10-26 2021-07-22 包括半导体芯片的半导体封装件 Pending CN114497023A (zh)

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