TW202201703A - 半導體封裝 - Google Patents
半導體封裝 Download PDFInfo
- Publication number
- TW202201703A TW202201703A TW110108466A TW110108466A TW202201703A TW 202201703 A TW202201703 A TW 202201703A TW 110108466 A TW110108466 A TW 110108466A TW 110108466 A TW110108466 A TW 110108466A TW 202201703 A TW202201703 A TW 202201703A
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- semiconductor
- die
- pads
- wafer
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 537
- 239000000758 substrate Substances 0.000 claims abstract description 244
- 235000012431 wafers Nutrition 0.000 claims description 461
- 238000000926 separation method Methods 0.000 description 6
- 239000000853 adhesive Substances 0.000 description 5
- 230000001070 adhesive effect Effects 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 3
- 238000007665 sagging Methods 0.000 description 3
- 239000010949 copper Substances 0.000 description 2
- 238000006073 displacement reaction Methods 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 150000001875 compounds Chemical class 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
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Abstract
本發明提供一種半導體封裝,包含:封裝基板,包含第一基板通道墊及第二基板通道墊;晶片堆疊,包含堆疊於封裝基板上以在第一方向上偏移的多個半導體晶片,其中多個半導體晶片中的位於奇數層上的第一半導體晶片及多個半導體晶片中的位於偶數層上的第二半導體晶片在垂直於第一方向的第二方向上偏移,第一半導體晶片中的每一者包含第一晶片通道墊,且第二半導體晶片中的每一者包含第二晶片通道墊;第一晶片間連接線,經組態以使第一半導體晶片的第一晶片通道墊彼此電連接;第二晶片間連接線,經組態以使第二半導體晶片的第二晶片通道墊彼此電連接。
Description
本發明概念是關於一種半導體封裝,且更特定言之,是關於一種具有其中多個半導體晶片豎直地堆疊在彼此上的結構的半導體封裝。
在半導體產品體積逐漸減小的同時需要高容量的資料處理。具有其中堆疊有多個半導體晶片的結構的半導體封裝可在具有較小佔用面積的同時快速處理高容量資料。然而,隨著堆疊的半導體晶片的數目增加且形成於半導體晶片上的電極墊的數目增加,半導體晶片之間的電連接變得困難且複雜。
本發明概念提供一種能夠改良多個半導體晶片之間的電連接的可靠性及多個半導體晶片與基板之間的電連接的可靠性的半導體封裝。
根據本發明概念的一態樣,提供一種半導體封裝,包含:封裝基板,包含第一基板通道墊及第二基板通道墊;晶片堆疊,包含堆疊於封裝基板上以在第一方向上偏移的多個半導體晶片,其中多個半導體晶片中的位於奇數層上的第一半導體晶片及多個半導體晶片中的位於偶數層上的第二半導體晶片在垂直於第一方向的第二方向上偏移,第一半導體晶片中的每一者包括第一晶片通道墊,且第二半導體晶片中的每一者包括第二晶片通道墊;第一晶片間連接線,經組態以使第一半導體晶片的第一晶片通道墊彼此電連接;第二晶片間連接線,經組態以使第二半導體晶片的第二晶片通道墊彼此電連接;第一基板晶片連接線,經組態以將第一半導體晶片中的位於最低層上的第一半導體晶片的第一晶片通道墊連接至第一基板通道墊;以及第二基板晶片連接線,經組態以將第二半導體晶片中的位於最低層上的第二半導體晶片的第二晶片通道墊連接至第二基板通道墊。
根據本發明概念的另一態樣,提供一種半導體封裝,包含:封裝基板,包含共用基板墊、第一基板通道墊以及第二基板通道墊;多個半導體晶片,堆疊於封裝基板上以在第一方向上偏移,多個半導體晶片中的每一者包含共用墊及通道墊;第一晶片間連接線,經組態以使多個半導體晶片中的位於奇數層上的半導體晶片的通道墊彼此電連接;第二晶片間連接線,經組態以使多個半導體晶片中的位於偶數層上的半導體晶片的通道墊彼此電連接;第三晶片間連接線,經組態以使多個半導體晶片的共用墊彼此電連接;第一基板晶片連接線,經組態以將位於奇數層上的半導體晶片中的位於最低層上的半導體晶片的通道墊電連接至第一基板通道墊;第二基板晶片連接線,經組態以將位於偶數層上的半導體晶片中的位於最低層上的半導體晶片的通道墊電連接至第二基板通道墊;第三基板晶片連接線,經組態以將位於奇數層上的半導體晶片中的位於最低層上的半導體晶片的共用墊電連接至共用基板墊;以及控制器,安裝於封裝基板上且包含彼此分離的第一通道及第二通道。控制器的第一通道經由第一基板晶片連接線及第一晶片間連接線電連接至位於奇數層上的半導體晶片,且控制器的第二通道經由第二基板晶片連接線及第二晶片間連接線電連接至位於偶數層上的半導體晶片。
根據本發明概念的另一態樣,提供一種半導體封裝,包含:封裝基板,包含共用基板墊、第一基板通道墊以及第二基板通道墊;多個半導體晶片,在豎直方向上堆疊於封裝基板上,多個半導體晶片中的每一者包含共用墊及通道墊;第一晶片間連接線,經組態以使多個半導體晶片中的位於奇數層上的半導體晶片的通道墊彼此電連接;第二晶片間連接線,經組態以使多個半導體晶片中的位於偶數層上的半導體晶片的通道墊彼此電連接;第三晶片間連接線,經組態以使多個半導體晶片的共用墊彼此電連接;第一基板晶片連接線,經組態以將位於奇數層上的半導體晶片中的位於最低層上的半導體晶片的通道墊連接至第一基板通道墊;第二基板晶片連接線,經組態以將位於偶數層上的半導體晶片中的位於最低層上的半導體晶片的通道墊連接至第二基板通道墊;第三基板晶片連接線,經組態以將位於奇數層上的半導體晶片中的位於最低層上的半導體晶片的共用墊電連接至共用基板墊;以及控制器,安裝於封裝基板上,經由第一基板晶片連接線及第一晶片間連接線電連接至位於奇數層上的半導體晶片,且經由第二基板晶片連接線及第二晶片間連接線電連接至位於偶數層上的半導體晶片。第一晶片間連接線的數目等於藉由自位於奇數層上的半導體晶片的總數目減去1而獲得的數目,第二晶片間連接線的數目等於藉由自位於偶數層上的半導體晶片的總數目減去1而獲得的數目,且第三晶片間連接線的數目等於藉由自多個半導體晶片的總數目減去1而獲得的數目。
在下文中,將參考隨附圖式更全面地描述本發明概念的實施例。在隨附圖式中,相同附圖標號可指代相同元件,且將省略對相同元件的重複描述。
圖1是根據本發明概念的實例實施例的半導體封裝100的透視圖。圖2是圖1的半導體封裝100的平面圖。圖3及圖4是示出半導體封裝100的不同橫截面的橫截面圖。
參考圖1至圖4,半導體封裝100可包含封裝基板130及晶片堆疊101。
封裝基板130可包含例如印刷電路板(printed circuit board;PCB)、可撓性基板或條帶基板。封裝基板130可包含配置於封裝基板130的上部表面上的上部基板墊。舉例而言,一或多個基板共用墊135、一或多個第一基板通道墊131以及一或多個第二基板通道墊133可設置在封裝基板130的上部表面上。封裝基板130可包含配置於封裝基板130的下部表面上的下部基板墊139。經組態以將外部設備電連接至半導體封裝100的外部連接端子190可配置於下部基板墊139上。外部連接端子190可為例如焊球。
晶片堆疊101可包含在豎直方向(Z方向)上堆疊於封裝基板130上的多個半導體晶片。儘管晶片堆疊101包含在圖1至圖4中在豎直方向上堆疊的八個半導體晶片,但實施例不限於此。舉例而言,晶片堆疊101可包含三個至七個半導體晶片或九個或大於九個半導體晶片。
根據本發明概念的例示性實施例,晶片堆疊101可包含多個半導體晶片中的位於奇數層上的第一半導體晶片110,及多個半導體晶片中的位於偶數層上的第二半導體晶片120。奇數層及偶數層是基於其上安裝有晶片堆疊101的封裝基板130的上部表面而限定。第一半導體晶片110中的位於最低層上的第一半導體晶片110是指在垂直於第一半導體晶片110中的封裝基板130的上部表面的方向上最接近封裝基板130的上部表面的半導體晶片,且第二半導體晶片120中的位於最低層上的第二半導體晶片120是指在垂直於第二半導體晶片120中的封裝基板130的上部表面的方向(例如,Z方向)上最接近封裝基板130的上部表面的半導體晶片。
如圖1至圖4所示,第一半導體晶片110及第二半導體晶片120可在封裝基板130的上部表面上在豎直方向上彼此交替。舉例而言,當晶片堆疊101包含八個半導體晶片時,晶片堆疊101可包含四個第一半導體晶片110及四個第二半導體晶片120。
根據例示性實施例,包含於晶片堆疊101中的多個半導體晶片可為相同種類的半導體晶片。舉例而言,多個半導體晶片可為記憶體半導體晶片。記憶體半導體晶片中的每一者可例如為諸如動態隨機存取記憶體(Dynamic Random Access Memory;DRAM)或靜態隨機存取記憶體(Static Random Access Memory;SRAM)的揮發性記憶體半導體晶片,或諸如相變隨機存取記憶體(Phase-change Random Access Memory;PRAM)、磁阻式隨機存取記憶體(Magnetoresistive Random Access Memory;MRAM)、鐵電隨機存取記憶體(Ferroelectric Random Access Memory;FeRAM)或電阻式隨機存取記憶體(Resistive Random Access Memory;RRAM)的非揮發性記憶體半導體晶片。根據一些例示性實施例,多個半導體晶片可為快閃記憶體,例如反及閘快閃記憶體。
根據其他例示性實施例,包含於晶片堆疊101中的多個半導體晶片可包含不同種類的半導體晶片。舉例而言,多個半導體晶片中的一些可為邏輯晶片,且另一些可為記憶體晶片。舉例而言,邏輯晶片中的每一者可為中央處理單元(central processing unit;CPU)晶片、圖形處理單元(graphics processing unit;GPU)晶片或應用程式處理器(application processor;AP)晶片。
每一半導體晶片可包含鄰近於半導體晶片的第一邊緣且沿著其第一邊緣配置的晶片墊。舉例而言,每一半導體晶片的晶片墊可配置在第二方向(Y方向)上,鄰近於與第二方向(Y方向)平行的邊緣。包含於每一半導體晶片中的晶片墊可電連接至設置於半導體晶片內的積體電路。舉例而言,積體電路可包含記憶體電路或邏輯電路。
根據例示性實施例,多個半導體晶片可具有相同尺寸。舉例而言,多個半導體晶片可具有相同水平寬度、相同豎直寬度以及相同厚度。
多個半導體晶片可具有具有相同形狀的接墊配置。舉例而言,在多個半導體晶片中,包含於每一半導體晶片中的晶片墊的數目、晶片墊的配置順序、每一晶片墊的大小以及晶片墊之間的間隔可以相同。
黏合部件180可設置在每一第一半導體晶片110的下部表面及每一第二半導體晶片120的下部表面上。第一半導體晶片110可經由黏合部件180堆疊於配置於其下方的第二半導體晶片120上,且第二半導體晶片120可經由另一黏合部件180堆疊於配置於其下方的第一半導體晶片110上。第一半導體晶片110中的配置於最低層上的第一半導體晶片110可經由另一黏合部件180附接至封裝基板130的上部表面。舉例而言,黏合部件180可為晶粒附接膜(die attach film;DAF)。
包含於晶片堆疊101中的多個半導體晶片可堆疊為在第一方向(X方向)上彼此依序偏移,以使得每一半導體晶片延伸超過下伏半導體晶片的側表面。舉例而言,第二半導體晶片120可堆疊於配置於其下方的第一半導體晶片110上,以使得第二半導體晶片120的一部分在第一方向(X方向)上自第一半導體晶片110突出。第一半導體晶片110可堆疊於配置於其下方的第二半導體晶片120上,以使得第一半導體晶片110的一部分在第一方向(X方向)上自第二半導體晶片120突出。舉例而言,多個半導體晶片可以逐步方式堆疊於彼此上。
多個半導體晶片可堆疊為在第一方向(X方向)上偏移第一偏移距離171,以使得包含於每一半導體晶片中的晶片墊暴露。舉例而言,第二半導體晶片120可堆疊為在第一方向(X方向)上偏移第一偏移距離171,以使得配置於第二半導體晶片120下方的第一半導體晶片110的晶片墊不經覆蓋。第一半導體晶片110可堆疊為在第一方向(X方向)上偏移第一偏移距離171,以使得配置於第一半導體晶片110下方的第二半導體晶片120的晶片墊不經覆蓋。
根據例示性實施例,第一偏移距離171可在約230微米(µm)與約400微米之間。當第一偏移距離171小於230微米時,每一半導體晶片的晶片墊可由其他半導體晶片覆蓋。當第一偏移距離171大於400微米時,多個半導體晶片的堆疊結構可崩塌。
根據例示性實施例,第二半導體晶片120可在垂直於第一方向(X方向)的第二方向(Y方向)上自第一半導體晶片110偏移。舉例而言,第二半導體晶片120可堆疊於配置於其下方的第一半導體晶片110上,以使得第二半導體晶片120的一部分在第二方向(Y方向)上自第一半導體晶片110突出。第一半導體晶片110可堆疊於配置於其下方的第二半導體晶片120上,以使得第一半導體晶片110的一部分在第二方向(Y方向)上自第二半導體晶片120突出。由於包含於晶片堆疊101中的多個半導體晶片在第一方向(X方向)上依序偏移,且第二半導體晶片120亦在第二方向(Y方向)上自第一半導體晶片110偏移,因此多個半導體晶片在圖2中所繪示的平面圖中可以Z字形方式配置。舉例而言,第一半導體晶片110的側表面可沿著第一方向(X方向)對準,且第二半導體晶片120的側表面可沿著第一方向(X方向)對準。
根據例示性實施例,當將第二半導體晶片120在第二方向(Y方向)上自第一半導體晶片110偏移的距離限定為第二偏移距離172時,第二偏移距離172可為約60微米至約80微米。舉例而言,第一半導體晶片110的側表面可在第二方向(Y方向)上自第二半導體晶片120的鄰近側表面偏移第二偏移距離172。
第一半導體晶片110中的每一者可包含沿著第一半導體晶片110中的每一者的第一邊緣配置的晶片墊。第一半導體晶片110中的每一者的晶片墊可包含一或多個第一晶片通道墊111及一或多個第一晶片共用墊115。
第一半導體晶片110中的每一者可具有相同的接墊配置。舉例而言,在第一半導體晶片110中的每一者中,包含第一晶片通道墊111及第一晶片共用墊115的晶片墊的配置順序、第一晶片通道墊111的數目、第一晶片共用墊115的數目以及晶片墊之間的間隔可以相同。當以平面圖進行查看時,位於不同層上的第一半導體晶片110的第一晶片通道墊111可在第一方向(X方向)上並排配置。舉例而言,位於不同層上的第一半導體晶片110的第一晶片通道墊111可在第一方向(X方向)上對準。當以平面圖進行查看時,位於不同層上的第一半導體晶片110的第一晶片共用墊115可在第一方向(X方向)上並排配置。舉例而言,位於不同層上的第一半導體晶片110的第一晶片共用墊115可在第一方向(X方向)上對準。根據例示性實施例,第一晶片通道墊111中的每一者在第二方向(Y方向)上的寬度175可為約50微米至約80微米。根據例示性實施例,在第二方向(Y方向)上的兩個鄰近第一晶片通道墊111之間的間隔176可為約80微米至約180微米。
位於不同層上的第一半導體晶片110的第一晶片通道墊111可藉由第一晶片間連接線141彼此電連接。第一晶片間連接線141中的每一者可連接在豎直方向上彼此間隔開的兩個第一半導體晶片110的第一晶片通道墊111與兩個第一半導體晶片110之間的單個第二半導體晶片120。舉例而言,藉由不同的第一晶片間連接線141,位於第一層及第三層上的第一半導體晶片110的第一晶片通道墊111可彼此電連接,位於第三層及第五層上的第一半導體晶片110的第一晶片通道墊111可彼此電連接,且位於第五層及第七層上的第一半導體晶片110的第一晶片通道墊111可彼此電連接。在此情況下,第一晶片間連接線141的數目可等於藉由自包含於晶片堆疊101中的第一半導體晶片110的總數目減去1而獲得的數目。舉例而言,三個第一晶片間連接線141可用於電連接在四個第一半導體晶片110的第一方向(X方向)上對準的第一晶片通道墊111。舉例而言,在第一方向(X方向)上對準的每一組第一晶片通道墊111可藉由比在第一方向(X方向)上對準的第一晶片通道墊111的總數目少一條的多個第一晶片間連接線141彼此電連接。
根據例示性實施例,第一半導體晶片110可為反及閘快閃記憶體,且可連接至同一通道。通道可指用於反及閘快閃記憶體的訊號的集合。舉例而言,由於位於不同層上的第一半導體晶片110的第一晶片通道墊111藉由第一晶片間連接線141彼此電連接,因此第一半導體晶片110可連接至同一通道。
第一半導體晶片110中的位於最低層上的第一半導體晶片110的第一晶片通道墊111可藉由第一基板晶片連接線151電連接至封裝基板130的第一基板通道墊131。第一基板晶片連接線151可經組態以將各種訊號傳輸至連接至同一通道的第一半導體晶片110的第一晶片通道墊111。
根據例示性實施例,第一晶片通道墊111中的每一者可對應於以下各者中的一者:資料I/O訊號經由其傳輸的輸入/輸出(input/output;I/O)墊,DQS經由其傳輸的資料選通訊號(data strobe signal;DQS)墊,CE訊號經由其傳輸的晶片啟用(chip enable;CE)墊,RE訊號經由其傳輸的讀取啟用(read enable;RE)墊,WE訊號經由其傳輸的寫入啟用(write enable;WE)墊,CLE訊號經由其傳輸的命令鎖存啟用(command latch enable;CLE)墊,ALE訊號經由其傳輸的位址鎖存啟用(ALE)墊以及R/B訊號經由其傳輸的就緒/忙碌(R/B)墊。
根據例示性實施例,第一晶片共用墊115中的每一者可對應於將電源電壓(例如,2.0伏至5.0伏的電壓)供應至第一半導體晶片110的Vcc墊或將接地電壓供應至第一半導體晶片110的Vss墊。
第二半導體晶片120中的每一者可包含沿著第二半導體晶片120中的每一者的第一邊緣配置的晶片墊。第二半導體晶片120中的每一者的晶片墊可包含一或多個第二晶片通道墊121及一或多個第二晶片共用墊125。
第二半導體晶片120中的每一者可具有相同的接墊配置。舉例而言,在第二半導體晶片120中的每一者中,包含第二晶片通道墊121及第二晶片共用墊125的晶片墊的配置順序、第二晶片通道墊121的數目、第二晶片共用墊125的數目以及晶片墊之間的間隔可以相同。當以平面圖進行查看時,位於不同層上的第二半導體晶片120的第二晶片通道墊121可在第一方向(X方向)上並排配置。舉例而言,位於不同層上的第二半導體晶片120的第二晶片通道墊121可沿著第一方向(X方向)對準。當以平面圖進行查看時,位於不同層上的第二半導體晶片120的第二晶片共用墊125可在第一方向(X方向)上並排配置。舉例而言,位於不同層上的第二半導體晶片120的第二晶片共用墊125可沿著第一方向(X方向)對準。根據例示性實施例,第二晶片通道墊121中的每一者在第二方向(Y方向)上的寬度173可為約50微米至約80微米。根據例示性實施例,在第二方向(Y方向)上的兩個鄰近第二晶片通道墊121之間的間隔174可為約80微米至約180微米。根據例示性實施例,第二半導體晶片120的晶片墊的接墊配置可與第一半導體晶片110的晶片墊的接墊配置相同。
位於不同層上的第二半導體晶片120的第二晶片通道墊121可藉由第二晶片間連接線143彼此電連接。第二晶片間連接線143中的每一者可連接在豎直方向上彼此間隔開的兩個第二半導體晶片120的第二晶片通道墊121與兩個第二半導體晶片120之間的單個第一半導體晶片110。舉例而言,藉由不同的第二晶片間連接線143,位於第二層及第四層上的第二半導體晶片120的第二晶片通道墊121可彼此電連接,位於第四層及第六層上的第二半導體晶片120的第二晶片通道墊121可彼此電連接,且位於第六層及第八層上的第二半導體晶片120的第二晶片通道墊121可彼此電連接。在此情況下,第二晶片間連接線143的數目可等於藉由自包含於晶片堆疊101中的第二半導體晶片120的總數目減去1而獲得的數目。舉例而言,三個第二晶片間連接線143可用於電連接在四個第二半導體晶片120的第一方向(X方向)上對準的第二晶片通道墊121。舉例而言,在第一方向(X方向)上對準的每一組第二晶片通道墊121可藉由比在第一方向(X方向)上對準的第二晶片通道墊121的總數目少一條的數個第二晶片間連接線143彼此電連接。
根據例示性實施例,第二半導體晶片120可為反及閘快閃記憶體,且可連接至同一通道。舉例而言,由於位於不同層上的第二半導體晶片120的第二晶片通道墊121藉由第二晶片間連接線143彼此電連接,因此第二半導體晶片120可連接至同一通道。在此情況下,第二半導體晶片120可連接至與第一半導體晶片110連接至的通道不同的通道。
第二半導體晶片120中的位於最低層上的第二半導體晶片120的第二晶片通道墊121可藉由第二基板晶片連接線153電連接至封裝基板130的第二基板通道墊133。第二基板晶片連接線153可經組態以將各種訊號傳輸至連接至同一通道的第二半導體晶片120的第二晶片通道墊121。
根據例示性實施例,第二晶片通道墊121中的每一者可對應於以下中各者的一者:I/O墊、DQS墊、CE墊、RE墊、WE墊、CLE墊、ALE墊以及R/B墊。
根據例示性實施例,第二晶片共用墊125中的每一者可對應於將電源電壓供應至第二半導體晶片120的Vcc墊或將接地電壓供應至第二半導體晶片120的Vss墊。
位於不同層上的第一半導體晶片110的第一晶片共用墊115可藉由第三晶片間連接線145電連接至位於不同層上的第二半導體晶片120的第二晶片共用墊125。第三晶片間連接線145中的每一者可在第一半導體晶片110與第二半導體晶片120之間延伸以在豎直方向上彼此接觸。舉例而言,每一第一半導體晶片110可經由第三晶片間連接線145連接至位於鄰近層處的一或多個第二半導體晶片120。在此情況下,第三晶片間連接線145的數目可等於藉由自第一半導體晶片110的數目與第二半導體晶片120的數目的總和減去1而獲得的數目。舉例而言,當晶片堆疊101包含八個半導體晶片時,七個第三晶片間連接線145可用於將第一半導體晶片110的第一晶片共用墊115電連接至第二半導體晶片120的第二晶片共用墊125。
第一半導體晶片110中的位於最低層上的第一半導體晶片110的第一晶片共用墊115可藉由第三基板晶片連接線155電連接至封裝基板130的基板共用墊135。
通常供應至第一半導體晶片110及第二半導體晶片120的訊號可經由第三晶片間連接線145及第三基板晶片連接線155傳輸。舉例而言,經由第三晶片間連接線145及第三基板晶片連接線155,驅動半導體晶片中的每一者所需的電源電壓及接地電壓可供應至半導體晶片中的每一者。
第一晶片間連接線141、第二晶片間連接線143、第三晶片間連接線145、第一基板晶片連接線151、第二基板晶片連接線153以及第三基板晶片連接線155可經由線接合製程形成,且可為包含諸如金(Au)或銅(Cu)的導電材料的導電線。
由第一晶片間連接線141連接的第一半導體晶片110的第一晶片通道墊111可在第二方向(Y方向)上與由第二晶片間連接線143連接的第二半導體晶片120的第二晶片通道墊121間隔開。在此情況下,使第一半導體晶片110的第一晶片通道墊111彼此連接的第一晶片間連接線141可在第二方向(Y方向)上與使第二半導體晶片120的第二晶片通道墊121彼此連接的第二晶片間連接線143間隔開。
根據例示性實施例,鄰近第一晶片通道墊111之間的間隔176與鄰近第二晶片通道墊121之間的間隔174中的每一者可不同於第二偏移距離172,所述第二偏移距離為第二半導體晶片120在第二方向(Y方向)上自第一半導體晶片110偏移的距離。當鄰近第一晶片通道墊111之間的間隔176及鄰近第二晶片通道墊121之間的間隔174不同於第二偏移距離172時,第一半導體晶片110的第一晶片通道墊111與第二半導體晶片120的第二晶片通道墊121可在第二方向(Y方向)上偏移,且因此,第一晶片間連接線141及第二晶片間連接線143可在第二方向(Y方向)上彼此間隔開。
舉例而言,鄰近第一晶片通道墊111之間的間隔176及鄰近第二晶片通道墊121之間的間隔174中的每一者大於第二偏移距離172。根據例示性實施例,第二偏移距離172可為鄰近第一晶片通道墊111之間的間隔176的約70%至約90%,或為鄰近第二晶片通道墊121之間的間隔174的約70%至約90%。
儘管圖1至圖4中未繪示,但半導體封裝100可包含覆蓋設置在封裝基板130上的晶片堆疊101的模製層。舉例而言,模製層可形成為覆蓋封裝基板130的上部表面且覆蓋包含於晶片堆疊101中的半導體晶片的各別側向表面。舉例而言,模製層可包含絕緣樹脂或環氧樹脂模製化合物(epoxy mold compound;EMC)。
一般而言,包含在豎直方向上堆疊的多個半導體晶片的半導體封裝使用延伸超出兩個或大於兩個半導體晶片的長導線,以便實現半導體晶片之間的電連接或半導體晶片與封裝基板之間的電連接。與其他相對較短的導線相比,長導線具有較大迴路高度,且在諸如模製製程的製造製程期間易於移位或下垂。歸因於長導線的移位或下垂,長導線接觸其他導線且因此頻繁地發生電短路。
然而,根據本發明概念的實施例,半導體封裝100可藉由使用具有相對較小長度的導電線來實施半導體晶片之間的電連接或半導體晶片與封裝基板130之間的電連接。因此,可解決由於導電線的移位或下垂而引起的電短路。此外,由於連接至不同通道的第一半導體晶片110及第二半導體晶片120可交替地堆疊,因此可在不使用長導線的情況下實施第一半導體晶片110與封裝基板130之間的電連接或第二半導體晶片120與封裝基板130之間的電連接。因此,可防止構成不同通道的導電線之間的電短路。因此,在半導體封裝100中,多個半導體晶片之間的電連接及多個半導體晶片與基板之間的電連接可具有改良的可靠性。
圖5是根據本發明概念的實例實施例的半導體封裝100a的平面圖。除每一半導體晶片的接墊配置之外,圖5的半導體封裝100a可與上文參考圖1至圖4所描述的半導體封裝100實質上相同。為方便解釋起見,將省略或簡要地給出與上文給出的描述相同的描述。
參考圖5,每一第一半導體晶片110可包含兩個或大於兩個第一晶片共用墊115及兩個或大於兩個第一晶片通道墊111。在每一第一半導體晶片110中,一個第一晶片通道墊111可安置於在第二方向(Y方向)上鄰近的兩個第一晶片共用墊115之間,且兩個鄰近的第一晶片通道墊111可在第二方向(Y方向)上藉由其間的一個第一晶片共用墊115彼此間隔開。在此情況下,經組態以使得輸入或輸出的資料或其類似物的第一晶片通道墊111藉由其間的第一晶片共用墊115彼此間隔開,第一晶片共用墊115具備電源電壓或接地電壓,且因此,可防止由於雜訊而在第一晶片通道墊111之間發生訊號干擾。
每一第二半導體晶片120可包含兩個或大於兩個第二晶片共用墊125及兩個或大於兩個第二晶片通道墊121。在每一第二半導體晶片120中,一個第二晶片通道墊121可安置於在第二方向(Y方向)上鄰近的兩個第二晶片共用墊125之間,且兩個鄰近的第二晶片通道墊121可在第二方向(Y方向)上藉由其間的一個第二晶片共用墊125彼此間隔開。在此情況下,經組態以使得輸入或輸出的資料或其類似物的第二晶片通道墊121藉由其間的第二晶片共用墊125彼此間隔開,第二晶片共用墊125具備電源電壓或接地電壓,且因此,可防止由於雜訊而在第二晶片通道墊121之間發生訊號干擾。
圖6是根據本發明概念的實例實施例的半導體封裝100b的橫截面圖。圖7是示出圖6的半導體封裝100b的主要組件的方塊圖。為方便解釋起見,將省略或簡要地給出與上文給出的描述相同的描述。
參考圖6及圖7,半導體封裝100b可包含經組態以控制包含於晶片堆疊101中的半導體晶片的操作的控制器160。
控制器160可安裝於封裝基板130上。舉例而言,控制器160可以覆晶方式安裝於封裝基板130上。連接凸塊可位於控制器160的接墊與封裝基板130的接墊之間,以便將控制器160的接墊電連接至封裝基板130的接墊。控制器160可經由設置於封裝基板130內的互連路徑電連接至晶片堆疊101的半導體晶片。根據一些例示性實施例,與圖6相比,控制器160可設置於半導體封裝100b外部。
根據例示性實施例,控制器160可包含彼此分離的兩個通道,且可經由所述兩個通道連接至晶片堆疊101的半導體晶片。舉例而言,控制器160的第一通道CH1可連接至位於晶片堆疊101中的奇數層上的第一半導體晶片110,且控制器160的第二通道CH2可連接至位於晶片堆疊101中的偶數層上的第二半導體晶片120。控制器160可經由兩個獨立通道(例如,第一通道CH1及第二通道CH2)分別將第一通道訊號及第二通道訊號提供至第一半導體晶片110及第二半導體晶片120。舉例而言,第一通道訊號及第二通道訊號中的每一者可包含I/O訊號、DQS訊號、CE訊號、RE訊號、WE訊號、CLE訊號、ALE訊號、R/B訊號或其類似者。
根據例示性實施例,控制器160可經由獨立導電路徑電連接至第一半導體晶片110及第二半導體晶片120。舉例而言,控制器160的第一接墊161可經由封裝基板130的第一互連路徑137電連接至封裝基板130的第一基板通道墊131,且控制器160的第二接墊163可經由封裝基板130的第二互連路徑138電連接至封裝基板130的第二基板通道墊133。在此情況下,可經由封裝基板130的第一互連路徑137、第一基板晶片連接線151以及第一晶片間連接線141將提供至控制器160的第一接墊161的第一通道訊號提供至第一半導體晶片110。可經由封裝基板130的第二互連路徑138、第二基板晶片連接線153以及第二晶片間連接線143將提供至控制器160的第二接墊163的第二通道訊號提供至第二半導體晶片120。
在圖6及圖7中,控制器160具有兩個通道。然而,控制器160可具有三個或大於三個通道。在此情況下,控制器160的通道中的每一者可經組態以連接至連接的兩個或大於兩個半導體晶片。
圖8是根據本發明概念的實例實施例的半導體封裝100c的橫截面圖。除每一半導體晶片的接墊配置之外,圖8的半導體封裝100c可與上文參考圖6及圖7所描述的半導體封裝100b實質上相同。為方便解釋起見,將省略或簡要地給出與上文給出的描述相同的描述。
參考圖8,控制器160可安裝於封裝基板130上以在垂直於封裝基板130的上部表面的豎直方向上由晶片堆疊101至少部分地重疊。舉例而言,如自上方查看,控制器160的一部分可由一些半導體晶片重疊及覆蓋。作為另一實例,如自上方查看,控制器160可由一些半導體晶片完全重疊及覆蓋。當控制器160由晶片堆疊101重疊時,半導體封裝100c可具有減小的平面大小。
圖9是根據本發明概念的實例實施例的半導體封裝100d的橫截面圖。圖10是示出圖9的半導體封裝100d的主要組件的方塊圖。為方便解釋起見,將省略或簡要地給出與上文給出的描述相同的描述。
參考圖9及圖10,半導體封裝100d可包含封裝基板130、第一晶片堆疊101a、第二晶片堆疊101b以及控制器160。
第一晶片堆疊101a可包含藉由使用黏合部件180在豎直方向上堆疊於封裝基板130的上部表面上的多個半導體晶片。第一晶片堆疊101a可包含多個半導體晶片中的位於奇數層上的第一半導體晶片110及多個半導體晶片中的位於偶數層上的第二半導體晶片120。第一半導體晶片110的第一晶片通道墊111可經由第一晶片間連接線141彼此電連接,且第一半導體晶片110中的位於最低層上的第一半導體晶片110的第一晶片通道墊111可經由第一基板晶片連接線151電連接至封裝基板130的第一基板通道墊131。第二半導體晶片120的第二晶片通道墊121可經由第二晶片間連接線143彼此電連接,且第二半導體晶片120中的位於最低層上的第二半導體晶片120的第二晶片通道墊121可經由第二基板晶片連接線153電連接至封裝基板130的第二基板通道墊133。第一半導體晶片110的第一晶片共用墊115(參見圖1)及第二半導體晶片120的第二晶片共用墊125(參見圖1)可經由第三晶片間連接線145(參見圖1)彼此電連接,且第一半導體晶片110中的位於最低層上的第一半導體晶片110的第一晶片共用墊115可經由第三基板晶片連接線155(參見圖1)電連接至封裝基板130的基板共用墊135(參見圖1)。包含於第一晶片堆疊101a中的第一半導體晶片110及第二半導體晶片120、第一晶片間連接線141、第二晶片間連接線143、第三晶片間連接線145、第一基板晶片連接線151、第二基板晶片連接線153以及第三基板晶片連接線155可與上文參考圖1至圖4所描述的彼等組件實質上相同。
第二晶片堆疊101b可包含藉由使用黏合部件280在豎直方向上堆疊於封裝基板130的下部表面上的多個半導體晶片。
第二晶片堆疊101b可包含多個半導體晶片中的位於奇數層上的第三半導體晶片210及多個半導體晶片中的位於偶數層上的第四半導體晶片220。第二晶片堆疊101b可與上文參考圖1至圖4所描述的晶片堆疊101實質上相同或相似。
第三半導體晶片210可包含第三晶片通道墊211及第三晶片共用墊。第三半導體晶片210的第三晶片通道墊211可經由第四晶片間連接線241彼此電連接,且第三半導體晶片210中的位於最低層上的第三半導體晶片210的第三晶片通道墊211可經由第四基板晶片連接線251電連接至封裝基板130的第三基板通道墊231。第三半導體晶片210可連接至同一通道。第三半導體晶片210、第四晶片間連接線241以及第四基板晶片連接線251可分別與上文參考圖1至圖4所描述的第一半導體晶片110、第一晶片間連接線141以及第一基板晶片連接線151實質上相同或相似。
第四半導體晶片220可包含第四晶片通道墊221及第四晶片共用墊。第四半導體晶片220的第四晶片通道墊221可經由第五晶片間連接線243彼此電連接,且第四半導體晶片220中的位於最低層上的第四半導體晶片220的第四晶片通道墊221可經由第五基板晶片連接線253電連接至封裝基板130的第四基板通道墊233。第四半導體晶片220可連接至同一通道。第四半導體晶片220、第五晶片間連接線243以及第五基板晶片連接線253可分別與上文參考圖1至圖4所描述的第二半導體晶片120、第二晶片間連接線143以及第二基板晶片連接線153實質上相同或相似。
第三半導體晶片210的第三晶片共用墊及第四半導體晶片220的第四晶片共用墊可經由第六晶片間連接線彼此電連接,且第三半導體晶片210中的位於最低層上的第三半導體晶片210的第三晶片共用墊可經由第六基板晶片連接線電連接至設置在封裝基板130的下部表面上的基板共用墊。第六晶片間連接線及第六基板晶片連接線可分別與上文參考圖1至圖4所描述的第三晶片間連接線145及第三基板晶片連接線155實質上相同或相似。第三半導體晶片210及第四半導體晶片220可經組態以經由第六基板晶片連接線及第六晶片間連接線接收電源電壓或接地電壓。
控制器160可具有彼此分離的四個通道。舉例而言,控制器160的兩個通道可連接至第一晶片堆疊101a,且控制器160的剩餘兩個通道可連接至第二晶片堆疊101b。
舉例而言,控制器160的第一通道CH1可連接至包含於第一晶片堆疊101a中的第一半導體晶片110,控制器160的第二通道CH2可連接至包含於第一晶片堆疊101a中的第二半導體晶片120,控制器160的第三通道CH3可連接至包含於第二晶片堆疊101b中的第三半導體晶片210,以及控制器160的第四通道CH4可連接至包含於第二晶片堆疊101b中的第四半導體晶片220。控制器160可經由四個獨立通道分別將第一通道訊號、第二通道訊號、第三通道訊號以及第四通道訊號提供至第一半導體晶片110、第二半導體晶片120、第三半導體晶片210以及第四半導體晶片220。舉例而言,第一至第四通道訊號中的每一者可包含I/O訊號、DQS訊號、CE訊號、RE訊號、WE訊號、CLE訊號、ALE訊號、R/B訊號或其類似者。
根據例示性實施例,控制器160可經由獨立導電路徑電連接至第一半導體晶片110、第二半導體晶片120、第三半導體晶片210以及第四半導體晶片220。舉例而言,控制器160的第一接墊161可經由封裝基板130內的第一互連路徑電連接至封裝基板130的第一基板通道墊131,控制器160的第二接墊163可經由封裝基板130內的第二互連路徑電連接至封裝基板130的第二基板通道墊133,控制器160的第三接墊165可經由封裝基板130內的第三互連路徑電連接至封裝基板130的第三基板通道墊231,且控制器160的第四接墊167可經由封裝基板130內的第四互連路徑電連接至封裝基板130的第四基板通道墊233。
舉例而言,可經由封裝基板130內的第一互連路徑、第一基板晶片連接線151以及第一晶片間連接線141將提供至控制器160的第一接墊161的第一通道訊號提供至第一半導體晶片110。可經由封裝基板130內的第二互連路徑、第二基板晶片連接線153以及第二晶片間連接線143將提供至控制器160的第二接墊163的第二通道訊號提供至第二半導體晶片120。可經由封裝基板130內的第三互連路徑、第四基板晶片連接線251以及第四晶片間連接線241將提供至控制器160的第三接墊165的第三通道訊號提供至第三半導體晶片210。可經由封裝基板130內的第四互連路徑、第五基板晶片連接線253以及第五晶片間連接線243將提供至控制器160的第四接墊167的第四通道訊號提供至第四半導體晶片220。
圖11是根據本發明概念的實例實施例的半導體封裝100e的橫截面圖。為方便解釋起見,將省略或簡要地給出與上文給出的描述相同的描述。
參考圖11,半導體封裝100e可為其中上部半導體封裝100U堆疊於下部半導體封裝100L上的疊層封裝型半導體封裝。
下部半導體封裝100L可包含封裝基板130、包含第一半導體晶片110及第二半導體晶片120的第一晶片堆疊101a、控制器160、第一晶片間連接線141、第二晶片間連接線143、第三晶片間連接線、第一基板晶片連接線151、第二基板晶片連接線153以及第三基板晶片連接線155。下部半導體封裝100L可具有與上文參考圖8所描述的半導體封裝100c實質上相似的結構。
然而,下部半導體封裝100L可更包含多個半導體晶片中的存在於最高層上的半導體晶片上的重佈圖案191。重佈圖案191可經由電連接部件電連接至控制器160、包含於第一晶片堆疊101a中的半導體晶片中的至少一者或封裝基板130。
上部半導體封裝100U可包含上部封裝基板230、包含第三半導體晶片210及第四半導體晶片220的第二晶片堆疊101b、第四晶片間連接線241、第五晶片間連接線243、第六晶片間連接線、第四基板晶片連接線251、第五基板晶片連接線253以及第六基板晶片連接線。上部封裝基板230可經由封裝間連接凸塊290電連接至下部半導體封裝100L的重佈圖案191。
第二晶片堆疊101b以及包含於第二晶片堆疊101b中的第三半導體晶片210及第四半導體晶片220可與上文參考圖9及圖10所描述的半導體封裝100d的彼等組件實質上相同或相似。
第三半導體晶片210的第三晶片通道墊211可經由第四晶片間連接線241彼此電連接,且第三半導體晶片210中的位於最低層上的第三半導體晶片210的第三晶片通道墊211可經由第四基板晶片連接線251電連接至上部封裝基板230的第三基板通道墊231。第三半導體晶片210可連接至同一通道。
根據例示性實施例,由控制器160提供的訊號可經由重佈圖案191、封裝間連接凸塊290、上部封裝基板230、第四基板晶片連接線251以及第四晶片間連接線241傳輸至第三半導體晶片210。
第四半導體晶片220的第四晶片通道墊221可經由第五晶片間連接線243彼此電連接,且第四半導體晶片220中的位於最低層上的第四半導體晶片220的第四晶片通道墊221可經由第五基板晶片連接線253電連接至封裝基板130的第四基板通道墊233。第四半導體晶片220可連接至同一通道。
根據例示性實施例,由控制器160提供的訊號可經由重佈圖案191、封裝間連接凸塊290、上部封裝基板230、第五基板晶片連接線253以及第五晶片間連接線243傳輸至第四半導體晶片220。
第三半導體晶片210的第三晶片共用墊及第四半導體晶片220的第四晶片共用墊可經由第六晶片間連接線彼此電連接,且第三半導體晶片210中的位於最低層上的第三半導體晶片210的第三晶片共用墊可經由第六基板晶片連接線電連接至上部封裝基板230的基板共用墊。外部接收的電源電壓或接地電壓可經由重佈圖案191、封裝間連接凸塊290、上部封裝基板230、第六基板晶片連接線以及第六晶片間連接線傳輸至第三半導體晶片210及第四半導體晶片220。
控制器160可類似於上文參考圖9及圖10所描述具有彼此分離的四個通道,且可經組態以經由四個通道將不同通道訊號傳輸至第一半導體晶片110、第二半導體晶片120、第三半導體晶片210以及第四半導體晶片220。
儘管本發明概念已參考其實施例進行具體繪示及描述,但應理解,可在不脫離隨附申請專利範圍的精神及範疇的情況下對形式及細節作出各種改變。
100、100a、100b、100c、100d、100e:半導體封裝
100L:下部半導體封裝
100U:上部半導體封裝
101:晶片堆疊
101a:第一晶片堆疊
101b:第二晶片堆疊
110:第一半導體晶片
111:第一晶片通道墊
115:第一晶片共用墊
120:第二半導體晶片
121:第二晶片通道墊
125:第二晶片共用墊
130:封裝基板
131:第一基板通道墊
133:第二基板通道墊
135:基板共用墊
137:第一互連路徑
138:第二互連路徑
139:下部基板墊
141:第一晶片間連接線
143:第二晶片間連接線
145:第三晶片間連接線
151:第一基板晶片連接線
153:第二基板晶片連接線
155:第三基板晶片連接線
160:控制器
161:第一接墊
163:第二接墊
165:第三接墊
167:第四接墊
171:第一偏移距離
172:第二偏移距離
173、175:寬度
174、176:間隔
180、280:黏合部件
190:外部連接端子
191:重佈圖案
210:第三半導體晶片
211:第三晶片通道墊
220:第四半導體晶片
221:第四晶片通道墊
230:上部封裝基板
231:第三基板通道墊
233:第四基板通道墊
241:第四晶片間連接線
243:第五晶片間連接線
251:第四基板晶片連接線
253:第五基板晶片連接線
290:封裝間連接凸塊
CH1:第一通道
CH2:第二通道
CH3:第三通道
CH4:第四通道
X、Y、Z:方向
自結合隨附圖式進行的以下詳細描述將更清楚地理解本發明概念的例示性實施例,在隨附圖式中:
圖1是根據本發明概念的實例實施例的半導體封裝的透視圖。
圖2是圖1的半導體封裝的平面圖。
圖3及圖4是示出圖1的半導體封裝的不同橫截面的橫截面圖。
圖5是根據本發明概念的實例實施例的半導體封裝的平面圖。
圖6是根據本發明概念的實例實施例的半導體封裝的橫截面圖。
圖7是示出圖6的半導體封裝的主要組件的方塊圖。
圖8是根據本發明概念的實例實施例的半導體封裝的橫截面圖。
圖9是根據本發明概念的實例實施例的半導體封裝的橫截面圖。
圖10是示出圖9的半導體封裝的主要組件的方塊圖。
圖11是根據本發明概念的實例實施例的半導體封裝的橫截面圖。
100:半導體封裝
101:晶片堆疊
110:第一半導體晶片
111:第一晶片通道墊
115:第一晶片共用墊
120:第二半導體晶片
121:第二晶片通道墊
125:第二晶片共用墊
130:封裝基板
131:第一基板通道墊
133:第二基板通道墊
135:基板共用墊
141:第一晶片間連接線
143:第二晶片間連接線
145:第三晶片間連接線
151:第一基板晶片連接線
153:第二基板晶片連接線
155:第三基板晶片連接線
180:黏合部件
190:外部連接端子
X、Y、Z:方向
Claims (20)
- 一種半導體封裝,包括: 封裝基板,包括第一基板通道墊及第二基板通道墊; 晶片堆疊,包括堆疊於所述封裝基板上以在第一方向上偏移的多個半導體晶片,其中所述多個半導體晶片中的位於奇數層上的第一半導體晶片及所述多個半導體晶片中的位於偶數層上的第二半導體晶片在垂直於所述第一方向的第二方向上偏移,所述第一半導體晶片中的每一者包括第一晶片通道墊,且所述第二半導體晶片中的每一者包括第二晶片通道墊; 第一晶片間連接線,經組態以使所述第一半導體晶片的所述第一晶片通道墊彼此電連接; 第二晶片間連接線,經組態以使所述第二半導體晶片的所述第二晶片通道墊彼此電連接; 第一基板晶片連接線,經組態以將所述第一半導體晶片中的位於最低層上的第一半導體晶片的所述第一晶片通道墊連接至所述第一基板通道墊;以及 第二基板晶片連接線,經組態以將所述第二半導體晶片中的位於最低層上的第二半導體晶片的所述第二晶片通道墊連接至所述第二基板通道墊。
- 如請求項1所述的半導體封裝,其中,從平面圖上看,所述第一半導體晶片的所述第一晶片通道墊在所述第一方向上並排配置,且所述第二半導體晶片的所述第二晶片通道墊在所述第一方向上並排配置。
- 如請求項2所述的半導體封裝,其中,從平面圖上看,所述第一半導體晶片的所述第一晶片通道墊在所述第二方向上與所述第二半導體晶片的所述第二晶片通道墊間隔開。
- 如請求項1所述的半導體封裝,更包括: 控制器,包括彼此分離的第一通道及第二通道, 其中所述控制器的所述第一通道經由所述第一基板晶片連接線及所述第一晶片間連接線電連接至所述第一半導體晶片的所述第一晶片通道墊,且 其中所述控制器的所述第二通道經由所述第二基板晶片連接線及所述第二晶片間連接線電連接至所述第二半導體晶片的所述第二晶片通道墊。
- 如請求項4所述的半導體封裝, 其中所述第一半導體晶片的所述第一晶片通道墊包括以下各者中的至少一者:輸入/輸出(I/O)墊、資料選通訊號(DQS)墊、晶片啟用(CE)墊、讀取啟用(RE)墊、寫入啟用(WE)墊、命令鎖存啟用(CLE)墊、位址鎖存啟用(ALE)墊以及就緒/忙碌(R/B)墊,且 其中所述第二半導體晶片的所述第二晶片通道墊包括以下各者中的至少一者:I/O墊、DQS墊、CE墊、RE墊、WE墊、CLE墊、ALE墊以及R/B墊。
- 如請求項1所述的半導體封裝, 其中所述封裝基板包括共用基板墊, 其中所述第一半導體晶片中的每一者包括第一共用墊, 其中所述第二半導體晶片中的每一者包括第二共用墊,且 其中所述半導體封裝更包括: 第三晶片間連接線,經組態以將所述第一半導體晶片的所述第一共用墊電連接至所述第二半導體晶片的所述第二共用墊;以及 第三基板晶片連接線,經組態以將所述第一半導體晶片中的位於所述最低層上的所述第一半導體晶片的所述第一共用墊電連接至所述共用基板墊。
- 如請求項6所述的半導體封裝, 其中所述第一半導體晶片的所述第一共用墊包括Vcc墊及Vss墊中的至少一者,且 其中所述第二半導體晶片的所述第二共用墊包括Vcc墊及Vss墊中的至少一者。
- 如請求項7所述的半導體封裝, 其中,從平面圖上看,所述第一半導體晶片的所述第一共用墊在所述第一方向上並排配置,且所述第二半導體晶片的所述第二共用墊在所述第一方向上並排配置,且 其中,從平面圖上看,所述第一半導體晶片的所述第一共用墊在所述第二方向上與所述第二半導體晶片的所述第二共用墊間隔開。
- 如請求項6所述的半導體封裝, 其中所述第一半導體晶片中的每一者具有其中所述第一晶片通道墊中的兩個第一晶片通道墊藉由所述兩個第一晶片通道墊之間的所述第一共用墊中的一個第一共用墊彼此間隔開的接墊配置,且 其中所述第二半導體晶片中的每一者具有其中所述第二晶片通道墊中的兩個第二晶片通道墊藉由所述兩個第二晶片通道墊之間的所述第二共用墊中的一個第二共用墊彼此間隔開的接墊配置。
- 如請求項1所述的半導體封裝,其中所述多個半導體晶片在所述第一方向上偏移的距離為約230微米至約400微米。
- 如請求項1所述的半導體封裝, 其中所述第一半導體晶片中的每一者包括沿著所述第一半導體晶片的一個邊緣配置的多個第一晶片通道墊,其中所述第二半導體晶片中的每一者包括沿著所述第二半導體晶片的一個邊緣配置的多個第二晶片通道墊,且其中所述多個第一晶片通道墊之間的間隔等於所述多個第二晶片通道墊之間的間隔。
- 如請求項11所述的半導體封裝,其中所述多個第一晶片通道墊之間的所述間隔及所述多個第二晶片通道墊之間的所述間隔大於所述第一半導體晶片及所述第二半導體晶片在所述第二方向上偏移的距離。
- 如請求項1所述的半導體封裝,其中所述多個半導體晶片中的每一者包含反及閘快閃記憶體。
- 如請求項1所述的半導體封裝,其中所述第一晶片間連接線中的每一者經組態以連接所述第一半導體晶片的彼此間隔開的兩個第一半導體晶片與所述第二半導體晶片中的位於所述兩個第一半導體晶片之間的一個第二半導體晶片。
- 一種半導體封裝,包括: 封裝基板,包括共用基板墊、第一基板通道墊以及第二基板通道墊; 多個半導體晶片,堆疊於所述封裝基板上以在第一方向上偏移,所述多個半導體晶片中的每一者包括共用墊及通道墊; 第一晶片間連接線,經組態以使所述多個半導體晶片中的位於奇數層上的半導體晶片的所述通道墊彼此電連接; 第二晶片間連接線,經組態以使所述多個半導體晶片中的位於偶數層上的半導體晶片的所述通道墊彼此電連接; 第三晶片間連接線,經組態以使所述多個半導體晶片的所述共用墊彼此電連接; 第一基板晶片連接線,經組態以將位於所述奇數層上的所述半導體晶片中的位於最低層上的半導體晶片的所述通道墊電連接至所述第一基板通道墊; 第二基板晶片連接線,經組態以將位於所述偶數層上的所述半導體晶片中的位於最低層上的半導體晶片的所述通道墊電連接至所述第二基板通道墊; 第三基板晶片連接線,經組態以將位於所述奇數層上的所述半導體晶片中的位於所述最低層上的所述半導體晶片的所述共用墊電連接至所述共用基板墊;以及 控制器,安裝於所述封裝基板上且包括彼此分離的第一通道及第二通道, 其中所述控制器的所述第一通道經由所述第一基板晶片連接線及所述第一晶片間連接線電連接至位於所述奇數層上的所述半導體晶片,且 其中所述控制器的所述第二通道經由所述第二基板晶片連接線及所述第二晶片間連接線電連接至位於所述偶數層上的所述半導體晶片。
- 如請求項15所述的半導體封裝, 其中第一晶片間連接線的數目等於藉由自位於所述奇數層上的所述半導體晶片的總數目減去1而獲得的數目, 其中第二晶片間連接線的數目等於藉由自位於所述偶數層上的所述半導體晶片的總數目減去1而獲得的數目,且 其中第三晶片間連接線的數目等於藉由自所述多個半導體晶片的總數目減去1而獲得的數目。
- 如請求項15所述的半導體封裝,其中所述第一晶片間連接線中的每一者在所述第一方向上延伸,且所述第二晶片間連接線中的每一者在所述第一方向上延伸。
- 如請求項15所述的半導體封裝,其中位於所述奇數層上的所述半導體晶片的所述通道墊在所述第一方向上及垂直於所述第一方向的第二方向上與位於所述偶數層上的所述半導體晶片的所述通道墊間隔開。
- 如請求項15所述的半導體封裝, 其中所述多個半導體晶片的所述通道墊對應於以下各者:輸入/輸出(I/O)墊、資料選通訊號(DQS)墊、晶片啟用(CE)墊、讀取啟用(RE)墊、寫入啟用(WE)墊、命令鎖存啟用(CLE)墊、位址鎖存啟用(ALE)墊或就緒/忙碌(R/B)墊,且 其中所述多個半導體晶片的所述共用墊對應於Vcc墊或Vss墊。
- 一種半導體封裝,包括: 封裝基板,包括共用基板墊、第一基板通道墊以及第二基板通道墊; 多個半導體晶片,在豎直方向上堆疊於所述封裝基板上,所述多個半導體晶片中的每一者包括共用墊及通道墊; 第一晶片間連接線,經組態以使所述多個半導體晶片中的位於奇數層上的半導體晶片的所述通道墊彼此電連接; 第二晶片間連接線,經組態以使所述多個半導體晶片中的位於偶數層上的半導體晶片的所述通道墊彼此電連接; 第三晶片間連接線,經組態以使所述多個半導體晶片的所述共用墊彼此電連接; 第一基板晶片連接線,經組態以將位於所述奇數層上的所述半導體晶片中的位於最低層上的半導體晶片的所述通道墊連接至所述第一基板通道墊; 第二基板晶片連接線,經組態以將位於所述偶數層上的所述半導體晶片中的位於最低層上的半導體晶片的所述通道墊連接至所述第二基板通道墊; 第三基板晶片連接線,經組態以將位於所述奇數層上的所述半導體晶片中的位於所述最低層上的所述半導體晶片的所述共用墊電連接至所述共用基板墊;以及 控制器,安裝於所述封裝基板上,經由所述第一基板晶片連接線及所述第一晶片間連接線電連接至位於所述奇數層上的所述半導體晶片,且經由所述第二基板晶片連接線及所述第二晶片間連接線電連接至位於所述偶數層上的所述半導體晶片, 其中第一晶片間連接線的數目等於藉由自位於所述奇數層上的所述半導體晶片的總數目減去1而獲得的數目, 其中第二晶片間連接線的數目等於藉由自位於所述偶數層上的所述半導體晶片的總數目減去1而獲得的數目,且 其中第三晶片間連接線的數目等於藉由自所述多個半導體晶片的總數目減去1而獲得的數目。
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