CN202394961U - 具有散热柱的半导体晶圆及封装构造 - Google Patents

具有散热柱的半导体晶圆及封装构造 Download PDF

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CN202394961U
CN202394961U CN2011205134165U CN201120513416U CN202394961U CN 202394961 U CN202394961 U CN 202394961U CN 2011205134165 U CN2011205134165 U CN 2011205134165U CN 201120513416 U CN201120513416 U CN 201120513416U CN 202394961 U CN202394961 U CN 202394961U
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方仁广
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Advanced Semiconductor Engineering Shanghai Inc
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Abstract

本实用新型公开一种具有散热柱的半导体晶圆及封装构造，所述半导体封装构造包含：一芯片、一绝缘区、一金属层及至少一散热柱。在晶圆作业期间，在所述芯片的上表面形成所述金属层，并于所述金属层上形成所述至少一散热柱。本实用新型通过所述散热柱可大幅提高所述半导体封装构造的散热效率，并且所述散热柱与所述芯片的结合稳固性良好。

Description

具有散热柱的半导体晶圆及封装构造
技术领域
本实用新型涉及一种半导体晶圆及封装构造，特别是有关于一种具有散热柱的半导体晶圆及封装构造。
背景技术
现今，半导体封装产业为了满足各种高密度封装的需求，逐渐发展出各种不同型式的封装构造，其中各种不同的系统封装(system in package，SIP)设计概念常用于架构高密度封装构造。一般而言，系统封装可分为多芯片模块(multi chip module，MCM)、封装体上堆栈封装体(package on package，POP)及封装体内堆栈封装体(package in package，PIP)等。然而，随着芯片的堆栈与累加，原本存在半导体封装构造中的芯片散热问题就更为严重。有几种现有应用于半导体封装构造的散热方式，举例如下。
请参照图1所示，其揭示一种现有具堆栈芯片的封装构造，其包含一封装基板11、一第一芯片12、一第二芯片13、数条第一导线14及数条第二导线15。所述封装基板11依序承载所述第一芯片12及第二芯片13，其中所述第一芯片12例如为中央处理单元(CPU)的芯片，所述第二芯片13例如为适当规格的内存芯片(如DRAM或FLASH)。所述第一芯片12的有源表面朝上，及其背面朝下且贴附于所述封装基板11上；所述第二芯片13的有源表面朝上，及其背面朝下且贴附于所述第一芯片12的有源表面上。所述第一芯片12及所述第二芯片13分别通过所述第一导线14及第二导线15电性连接所述封装基板11。为了增加散热效果，在封装构造的上表面贴付一散热片(或称热沉，heat sink)16以增加封装构造的散热效果。
另外，请参照图2所示，其揭示另一种现有多芯片的封装构造，其包含一封装基板21、一第一芯片22、一第二芯片23、数条导线24及数个凸块25。所述封装基板21依序承载所述第一芯片22及第二芯片23，其中所述第一芯片22例如为中央处理单元(CPU)的芯片，所述第二芯片23例如为适当规格的内存芯片(如DRAM或FLASH)。所述第一芯片22的有源表面朝上，及其背面朝下且贴附于所述封装基板21上，所述第一芯片22通过所述导线24电性连接所述封装基板21；所述第二芯片23设于所述第一芯片22的上方，所述第二芯片23的有源表面朝下，所述第二芯片23通过所述数个凸块25电性连接所述第一芯片22。为了增加散热效果，在封装构造的上表面设有一金属散热层26，以增加封装构造的散热效果。
虽然，图1或2的封装构造但仍具有一些缺点，例如：若封装构造采用散热片的方式，那么散热片黏贴的稳固性并不可靠；若封装构造采用平面状的金属散热层，则多半增加的散热效果有限。
故，有必要提供一种具有散热柱的半导体晶圆及封装构造，以解决现有技术所存在的问题。
实用新型内容
有鉴于此，本实用新型提供一种具有散热柱的半导体晶圆及封装构造，以解决现有多芯片封装技术所存在的散热构造不稳固或散热性不佳的技术问题。
本实用新型的主要目的在于提供一种半导体晶圆及封装构造，所述半导体封装构造包含：一芯片、一绝缘区、一金属层及至少一散热柱。在晶圆作业期间，在所述芯片的上表面形成所述金属层，并于所述金属层上形成所述至少一散热柱。本实用新型通过所述散热柱可大幅提高所述半导体封装构造的散热效率，并且所述散热柱与所述芯片的结合稳固性良好。
为达成本实用新型的前述目的，本实用新型提供一种半导体晶圆，其中所述半导体晶圆包含：
数个芯片；
一绝缘连接区，连接及支撑所述数个芯片，其中所述数个芯片是呈数组状的等距排列在所述绝缘连接区中；
一重布线层，形成在所述数个芯片及绝缘连接区的一第一表面上；
一金属层，形成在所述数个芯片及绝缘连接区的一第二表面上；以及
数个散热柱，对应每一芯片的位置形成在所述金属层上。
在本实用新型的一实施例中，所述第一表面电路层选自中央处理单元、逻辑集成电路、微机电系统、整合式无源组件装置、动态随机存取内存或闪存内存的表面电路。
在本实用新型的一实施例中，所述芯片各为一硅芯片区，所述绝缘连接区为一环氧树脂层。
在本实用新型的一实施例中，所述金属层包含一钛粘着层及一铜种子层。
在本实用新型的一实施例中，所述散热柱选自柱状凸块，如铜柱凸块或镍柱凸块。
再者，本实用新型提供另一种半导体封装构造，其中所述半导体封装构造包含：
一芯片；
一绝缘区，形成在所述芯片的周边；
一重布线层，形成在所述芯片及绝缘区的一第一表面上；
一金属层，形成在所述芯片及绝缘区的一第二表面上；以及
至少一散热柱，形成在所述金属层上。
在本实用新型的一实施例中，所述金属层包含一钛粘着层及一铜种子层。
在本实用新型的一实施例中，所述散热柱选自柱状凸块，如铜柱凸块或镍柱凸块。
在本实用新型的一实施例中，所述散热柱为多个，排列成一直行状，一数组状或一圆圈状。
在本实用新型的一实施例中，所述绝缘区为一环氧树脂层。
附图说明
图1是一现有具散热片的多芯片封装构造的示意图。
图2是另一现有具金属散热层的多芯片封装构造的示意图。
图3A、3B、3C及3D是本实用新型第一实施例半导体晶圆及芯片的制造方法各步骤的示意图。
图4是本实用新型第一实施例半导体封装构造的示意图。
图5是本实用新型第二实施例半导体封装构造的示意图。
具体实施方式
为让本实用新型上述目的、特征及优点更明显易懂，下文特举本实用新型较佳实施例，并配合附图，作详细说明如下。再者，本实用新型所提到的方向用语，例如「上」、「下」、「前」、「后」、「左」、「右」、「内」、「外」、「侧面」等，仅是参考附加图式的方向。因此，使用的方向用语是用以说明及理解本实用新型，而非用以限制本实用新型。
请参照图3A、3B、3C及3D所示，其概要揭示本实用新型第一实施例半导体晶圆及芯片的制造方法各步骤的示意图，本实用新型将于下文利用图3A至3D逐一详细说明第一实施例之上述各步骤的制造过程及其加工原理。
请参照图3A所示，本实用新型第一实施例的半导体晶圆及芯片的制造方法首先是：提供一半导体晶圆30，其中所述半导体晶圆30是以晶圆制造工艺先在其第一表面加工形成表面电路层(未绘示)，可以预定义出数个芯片31，此时的芯片31仍相互邻接，尚未进行分割单离。再者，所述半导体晶圆30例如选自一硅晶圆，同时所述数个芯片31即为数个硅芯片区，但并不限于此。
请参照图3B所示，本实用新型第一实施例的半导体晶圆及芯片的制造方法接着是：对图3A的半导体晶圆30进行切割，以形成每个独立单一的芯片31，另外准备一支撑框34和一保护胶带33，但也可以使用其它等效支撑组件来替代。此时，利用机械手臂逐一吸取而将已各自独立的芯片31依序重新布置于此支撑框34的保护胶带33上，因而形成另一个重新布置排列位置的半导体晶圆38。在切割后，每二相邻芯片31之间各具有一间距32，接着对所述间距32进行注胶作业，以在所述间距32位置形成一绝缘连接区35(图3C)，所述绝缘连接区35例如为一环氧树脂层，其材料特别是可做为电路板绝缘层或封装胶材的环氧树脂化合物，但并不仅限于此。所述绝缘连接区35可以绝缘的连接及支撑所述数个芯片31，其中所述数个芯片31是概呈数组/矩阵状的等距排列在所述绝缘连接区32中。
请参照图3C所示，本实用新型第一实施例的半导体晶圆及芯片的制造方法接着是：使用封装基板(或晶圆)形成表面线路的工艺，在所述芯片31及绝缘连接区32的第一表面上分别形成数层交替堆栈的绝缘层及金属线路层，以共同构成一重布线层(redistribution layer，RDL)36。也就是，在所述数个芯片31及绝缘连接区32的第一表面上形成一重布线层36。所述重布线层36电性连接所述数个芯片31的表面电路层。
请参照图3D所示，本实用新型第一实施例的半导体晶圆及芯片的制造方法接着是：进行翻面使第二表面朝上，并撕去原来在第二表面上的保护胶带33及支撑框34。接着，再使用另一组保护胶带(未绘示)及支撑框34’改为贴附支撑所述数个芯片31及绝缘连接区32的第一表面，以便在所述数个芯片31及绝缘连接区32的第二表面上形成一金属层37。接着，在所述金属层37上，利用光刻胶层曝光显影形成窗口裸露每一芯片31的位置，并对裸露的金属层37进行电镀，因而对应于每一芯片31的位置形成一散热柱39，所述散热柱39优选是一金属散热柱。所述金属层37及所述散热柱39另详述于后。
请参照图3D及图4所示，沿所述间距32的延伸方向进行切割所述绝缘连接区32，以分离出数颗封装构造40，其中每一颗封装构造40皆包含：一芯片41、一绝缘区42、一金属层43及一重布线层44。所述芯片41即相等于图3C的芯片31，且具有一表面电路层412。所述封装构造40也可以视为是晶圆级芯片尺寸封装体(WLCSP)。所述表面电路层412例如为中央处理单元(CPU)、逻辑IC(logic IC)、微机电系统(MEMS)或整合式无源组件装置(IPD)的表面电路，或为动态随机存取内存(DRAM)或闪存内存(FLASH)的表面电路，但并不限于此。所述绝缘区42即是图3D的绝缘连接区32切割分离后的剩余部份，所述绝缘区42形成在所述芯片41的周边。所述重布线层44即是图3C的其中一重布线层36，所述金属层43即是图3D的其中一金属层37；所述散热柱50即是图3D的其中一散热柱39。
如图4，所述金属层43优选是由一钛粘着层(adhesive layer)及一铜种子层(seed layer)所组成，但并不限于此，在图4中是概括性的以一金属层43来概要示意钛粘着层及铜种子层，所述金属层43的厚度在纳米(nm)等级，所述金属层43用以增加结合所述散热柱50的结合强度。如图3D所示，本实施例可在所述光刻胶层露出的金属层43上利用电镀工艺形成所述散热柱50，其中所述散热柱50选自柱状凸块，例如铜柱凸块(Cu pillar bumps)或镍柱凸块。
再者，所述重布线层44形成在所述芯片41及绝缘区42的一第一表面上，并具有数条重分布线路440以电性连接所述芯片41的表面电路层412，且具有数个裸露的焊垫441。所述重布线层44的设置目的在于将所述芯片31的表面电路层412的焊垫(未绘示)通过所述重布线层44的金属线路向外延伸到所述绝缘区42的第一表面上，以便使最后的裸露的焊垫441具有适当焊垫尺寸及焊垫间距，以适合在后续应用中用于向外电性连接导线或凸块。
请参照图5所示，本实用新型第二实施例的半导体晶圆及封装构造相似于本实用新型第一实施例，并大致沿用相同于图4的组件名称及图号，但第二实施例不同于第一实施例的差异特征在于：所述第二实施例的半导体封装构造的金属层43只设置在芯片41裸露的上表面上，并且每一颗封装构造40上设有二个或以上的散热柱50，每一颗封装构造40上的数个散热柱50可以排列成各种型式，如一直行状，一数组(array)状或一圆圈状，但本实用新型并不限于此。
如上所述，相较于现有多芯片封装技术存在散热效果无法再进一步提高的技术问题，图3A至5的本实用新型的半导体晶圆的每一颗封装构造40皆包含：一芯片41、一绝缘区42、一金属层43及至少一散热柱50。在晶圆作业期间，在所述封装构造40的上表面形成所述金属层43，并于所述金属层43上形成所述至少一散热柱50。本实用新型通过所述散热柱50可大幅提高所述封装构造40的散热效率，并且所述散热柱50与所述封装构造40的结合稳固性良好。
本实用新型已由上述相关实施例加以描述，然而上述实施例仅为实施本实用新型的范例。必需指出的是，已公开的实施例并未限制本实用新型的范围。相反地，包含于权利要求书的精神及范围的修改及均等设置均包括于本实用新型的范围内。

Claims (10)

1.一种具有散热柱的半导体晶圆，其特征在于：所述半导体晶圆包含：
数个芯片；
一绝缘连接区，连接及支撑所述数个芯片，其中所述数个芯片是呈数组状的等距排列在所述绝缘连接区中；
一重布线层，形成在所述数个芯片及绝缘连接区的一第一表面上；
一金属层，形成在所述数个芯片及绝缘连接区的一第二表面上；以及
数个散热柱，对应每一芯片的位置形成在所述金属层上。
2.如权利要求1所述的半导体晶圆，其特征在于：所述第一表面电路层选自中央处理单元、逻辑集成电路、微机电系统、整合式无源组件装置、动态随机存取内存或闪存内存的表面电路。
3.如权利要求1所述的半导体晶圆，其特征在于：所述芯片各为一硅芯片区，所述绝缘连接区为一环氧树脂层。
4.如权利要求1所述的半导体晶圆，其特征在于：所述金属层包含一钛粘着层及一铜种子层。
5.如权利要求1所述的半导体晶圆，其特征在于：所述散热柱选自柱状凸块，如铜柱凸块或镍柱凸块。
6.一种具有散热柱的半导体封装构造，其特征在于：所述半导体封装构造包含：
一芯片；
一绝缘区，形成在所述芯片的周边；
一重布线层，形成在所述芯片及绝缘区的一第一表面上；
一金属层，形成在所述芯片及绝缘区的一第二表面上；以及
至少一散热柱，形成在所述金属层上。
7.如权利要求6所述的半导体封装构造，其特征在于：所述金属层包含一钛粘着层及一铜种子层。
8.如权利要求6所述的半导体封装构造，其特征在于：所述散热柱选自柱状凸块，如铜柱凸块或镍柱凸块。
9.如权利要求6所述的半导体封装构造，其特征在于：所述散热柱为多个，排列成一直行状，一数组状或一圆圈状。
10.如权利要求6所述的半导体封装构造，其特征在于：所述绝缘区为一环氧树脂层。
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CN103594451A (zh) * 2013-11-18 2014-02-19 华进半导体封装先导技术研发中心有限公司 多层多芯片扇出结构及制作方法
CN105895623A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 用于半导体封装件的衬底设计及其形成方法
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CN103594451B (zh) * 2013-11-18 2016-03-16 华进半导体封装先导技术研发中心有限公司 多层多芯片扇出结构及制作方法
US10056267B2 (en) 2014-02-14 2018-08-21 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
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US10867949B2 (en) 2014-02-14 2020-12-15 Taiwan Semiconductor Manufacturing Company, Ltd. Substrate design for semiconductor packages and method of forming same
CN105895623A (zh) * 2015-02-13 2016-08-24 台湾积体电路制造股份有限公司 用于半导体封装件的衬底设计及其形成方法
CN105895623B (zh) * 2015-02-13 2019-07-16 台湾积体电路制造股份有限公司 用于半导体封装件的衬底设计及其形成方法
CN110620092A (zh) * 2018-06-20 2019-12-27 比亚迪股份有限公司 散热底板、散热元件及其制备方法和igbt模组

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