TWI389273B - 半導體晶粒總成 - Google Patents

半導體晶粒總成 Download PDF

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TWI389273B
TWI389273B TW094111358A TW94111358A TWI389273B TW I389273 B TWI389273 B TW I389273B TW 094111358 A TW094111358 A TW 094111358A TW 94111358 A TW94111358 A TW 94111358A TW I389273 B TWI389273 B TW I389273B
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assembly
die
substrate
conductive
conductive polymer
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TW094111358A
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TW200605298A (en
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Al Vindasius
Marc Robinson
Larry Jacobsen
Donald Almen
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Vertical Circuits Inc
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Description

半導體晶粒總成
本發明關係於用以堆疊及互連矽的積體電路晶粒及/或多晶粒片段，使用一導電聚合物或環氧樹脂，互連晶粒或多晶粒片段於堆疊邊緣上的設備。
很多年來，例如電晶體及積體電路的電氣元件已經使用包含矽及/或鍺的半導體材料晶圓加以完成。
積體電路已經使用各種如蝕刻、摻雜、及分層之技術而設置在晶圓上。已經被設在晶圓上的個別積體電路被稱為晶粒，並且，包含有被稱為黏結墊的接觸點，用以作外部電氣連接。典型地，在晶圓上的晶粒係藉由沿著定義晶粒的邊界，切割晶圓，而彼此分隔開。一旦晶粒由晶圓切開，則較佳地晶片或晶粒被封裝作進一步使用。於近年來，更強力電子系統的流行已經需要更高效能及更高密度的積體電路封裝。
用以增加高密度封裝的方法係想要以使用晶圓級整合(WSI)技術，在單一晶圓上建立整個電腦系統。WSI技術想要使用線以互連該晶粒，以水平地將在晶圓上的所有晶粒連線在一起。然而，為了增加在晶粒間之必須內連線，所以需要很多極端薄並且很難製造之線。再者，所得內連線晶粒在附著有晶圓級整合裝置的電子系統電路板上佔用一大面積或足跡。
建立較高密度封裝的第二方法想要藉由實體垂直堆疊晶片，而降低放置晶片於電路板上所需的面積。一晶片堆疊技術安裝個別晶粒在陶瓷載板上，密封晶粒及載板，堆疊載板，然後，將該堆疊安裝在一印刷電路板上。於此技術中，在堆疊中的所有晶粒係藉由經由金屬接腳而連接晶粒的引腳至印刷電路板而加以互連。因為高接腳數增加了任一接腳可能與電路板斷開的可能性，所以，此方法造成在電路板上的異常高接腳數，而降低了電路的可靠度。
另一晶片堆疊方法使用一更複雜製程以堆疊晶粒，如同於1992年四月14日所公開之美國專利第5,140,820號所述。此方法修改了個別晶片，使得它們可以藉由增加一所謂再配線引線的金屬化圖案至晶圓的表面而加以堆疊。再配線引線由晶片上的黏結墊延伸至新形成的黏結墊，並被安排使得所有再配線引線終止於修改晶片的一側上。每一修改晶片然後由晶圓切出，並被組合成一堆疊。該堆疊被組合成使得所有修改晶片的引線被沿著堆疊的同一側對準。具有引線的堆疊側然後被蝕刻及研磨，使得在每一修改晶片上的引線的剖面可以接觸到。在曝露出引線後，一金屬化層然後沿著堆疊側施加至引線上，以電氣連接在堆疊中之每一修改晶片。該堆疊然後安裝並連接至一基材，該隨後連接至傳統電路。
此再配線引線的方法提供優於先前技術的電路密度的改良，但較複雜並昂貴。另外，當修改晶片由晶圓切出時，延伸在鄰近晶粒上的再配線引線會被毀損。於此方法中，為了每一被修改的晶片，犧牲了多晶粒。
另一種建立較高密度電路的方法由整個晶圓建立堆疊以形成一晶圓陣列，而不是由個別晶片所建立堆疊。於部份裝置中，在堆疊中之晶圓係使用固體垂直柱的金屬導電導通體，例如銅，以電氣互連。由於熱循環中之熱膨脹係數不同，固體導通體用至互連晶圓可能造成對陣列的損害。再者，該程序成本很高，同時使得晶圓很難分開作修理。
其他用於晶圓的互連堆疊的方法也揭示於例如1990年六月30日公告之美國專利第4,897,708號及公告於1990年九月4日之第4,954,875號案中。該等方法提供在堆疊中之每一晶圓以錐形貫孔，其將晶圓上的黏結墊曝露出。在堆疊中之晶圓的黏結墊然後藉由以導電液填充貫孔或將符合導電材料插入貫孔中，以提供於晶圓間之連續垂直電氣連接。雖然避免了使用固體垂直柱金屬以互連晶圓的缺點，但導電液及導電材料的使用需要特殊工具，以填充貫孔。再者，對於部份應用中，由於電氣裝置尺寸上的限制，可能不想要使用整個晶圓的堆疊。
個別半導體晶粒典型被組合於封裝中，以允許積體電路晶粒被附著至印刷電路板，並允許在積體電路晶粒間完成電氣連接。用於此目的有很多類型的封裝。BGA封裝及TSOP封裝為兩常用封裝類型，用以組合記憶體晶粒及安裝所組裝晶粒至一印刷電路板上。有很多方法以堆疊封裝積體電路，但一般而言，由於必要長度及封裝間內連線所造成之加大寄生，所以，這些都有尺寸上的缺點，及效能上的缺點。由於封裝的大實體尺寸，所以對需要以堆疊在彼此上之封裝數量有限制，典型為2，以避免熱機械問題。封裝積體電路的堆疊近來已經流行，但仍佔用太多板空間，並太厚，並且，將不能操作於為例如DDR2及DDR3 DRAM之先進記憶體裝置所需之高速中。
因此，本發明之目的為提供一種改良方法及設備，用以堆疊及互連積體電路晶粒及多數晶粒片段。
本發明提供一設備，用以垂直地互連半導體晶粒、積體電路晶粒、或多數晶粒片段。延伸至晶粒或片段之一或多數側的金屬再配線內連線可以選用地加入至晶粒或多晶粒片段，以提供用於外電氣連接點的晶粒表面上的邊緣黏結墊。在金屬再配線內連線已經被加入至晶圓上的晶粒後，晶圓係被選用地切薄，並且，每一晶圓或多數晶粒片段係藉由切割或其他適當單一化方法，而由晶圓分開。在晶粒或多晶粒片段被單一化或由晶圓切開後，施加絕緣至該晶粒或多晶粒片段的所有表面上，在絕緣中的想要電氣連接墊上完成開口，及晶粒或多晶粒片段係被放置在彼此上，以形成一堆疊。在堆疊中之垂直鄰近片段係藉由附著一短撓性黏結線或黏結帶至晶圓週緣上的自晶粒水平突出的曝露電連接墊上，而電氣互連，並施加導電聚合物或環氧樹脂、絲線或線至堆疊的一或多數側。
依據本發明之另一態樣，設置有一導熱環氧樹脂預型片，使得片段堆疊被一起環氧化。導熱環氧樹脂預型物包含多數玻璃球，隨機地分佈在預型物內。
互連之晶粒堆疊然後被安裝並電氣連接至一基材的頂面，該基材由導電及絕緣層構成，並在對準已經沿著晶粒堆疊側形成的垂直絲或線下，基材頂面上，具有電連接點，並在基材的底部具有銲球，或其他連接機構，用以電氣連接及安裝基材的底部至一印刷電路板。
本發明之其他目的、特性及優點將由以下詳細說明配合上附圖加以明顯了解。
參考第1圖，半導體晶粒10具有原始連接墊60，連接墊60具有一絕緣層施加至所有晶粒的頂面30上，同時，所有晶粒係仍連接在一起呈一晶圓格式。一金屬層使用光微影被沉積來定義，以再配送來自原始連接墊60的電信號至晶粒邊緣的新位置。另一層絕緣材料被選用地施加至金屬層上，及在絕緣材料的頂層中在半導體晶圓邊緣的再定位墊位置作出開口，及選用地在晶粒的頂面中心下的原始墊位置處作出開口。
參考第2圖，半導體晶粒10已經被研磨或拋光變薄，並由半導體晶圓處單一化及該半導體晶粒已經被塗覆以一貼護絕緣塗層20。
參考第3圖，在塗層20中，在半導體晶粒10的原始連接墊60上，完成開口。
參考第4圖，顯示半導體晶粒70，具有連接墊80位在晶粒頂面的週緣旁。
參考第5圖，顯示在半導體晶粒上的位置90處的貼護塗層材料中的開口，半導體晶粒的電連接係位在晶粒表面之邊緣處。
第6圖顯示垂直堆疊總成元件5，其係由具有貼護塗層20的半導體晶粒10所構成。該半導體晶粒10具有一金屬導電元件61，其一端係連接至在晶粒10的週緣的電連接點，及金屬導電元件的另一端係內藏在垂直導電聚合物50中。該垂直導電聚合物50係鄰近晶粒堆疊的緣並電氣連接晶粒與在基材7上的頂部導電面94。
同時，在第6圖中也顯示一環氧樹脂預型物30，用以藉由黏結至每一晶粒上的貼護塗層20，而彼此積層晶粒10成為一堆疊。
第6圖顯示晶粒10的堆疊被以環氧樹脂預型物30加以彼此積層，並藉由水平導電元件61而電氣連接至垂直導電元件50，並安裝在基材7上。基材係被顯示具有：導電層94在其頂及底面、一核板70、防焊膜92在底面上、及錫球80連接至基板的底部。另外，一底膠材料40也被施加，使得其填滿堆疊之最底晶粒及基板70間之空間，並形成一具有堆疊緣的內緣填角，並填滿由預型物30之緣部到晶粒緣部之層間之間隙。
前述已經說明一高密度低寄生堆疊晶粒BGA或LGA元件總成。明顯地，各種元件可以用於本發明中。
例如，本發明可以包含一堆疊的半導體或積體電路晶粒安裝在一基材上並彼此積層在一起。該晶粒可以選用地具有一或多數金屬再配線層，以互連原始晶粒連接墊與在晶粒的頂面緣之新連接位置。新連接位置係想要用以垂直互連。
晶粒可以具有一貼護絕緣塗層，其中塗層可以為聚合物。聚合物塗層可以為聚對二甲苯基，及如特定元件設計所需，絕緣塗層可以在晶粒的頂面的邊緣之特定新連接位置上有開口。
開口可以例如藉由以雷射熔散移除聚合物及以電漿蝕刻機移除聚合物加以完成。
此開口可以藉由防止聚合物塗層沉積在晶粒上之連接墊上的選定區域中加以完成。晶粒可以以一電絕緣聚合物或環氧樹脂預型物被彼此積層在頂上。絕緣預型物可以導熱。
絕緣預型物可選用地包含球體，以維持於積層後，半導體晶粒間之固定間隔或間距。該等球體可以由玻璃、陶瓷、石英、塑膠、鐵氟龍、聚合物製造或具有一金屬塗層。
電絕緣聚合物可以為環氧樹脂。晶粒可以以一液體聚合物彼此積層於其頂上，該聚合物固化以在堆疊中之層間形成一固態黏結。絕緣聚合物可以選用地包含球體，以維持於積層後之半導體晶粒間之固定間隔或間距，其中球體可以由玻璃、陶瓷、石英、塑膠、鐵氟龍、聚合物及/或金屬塗層所作成。
電絕緣聚合物可以由環氧樹脂構成，其中晶粒可以為任意半導體晶粒，例如記憶體晶粒，其中記憶體晶粒可以為SDRAM、DDR－1、DDR－2、DDR－3或任意其他DRAM。記憶體晶粒可以為NAND快閃、NOR快閃、M－RAM、F－RAM、E2或其他非揮發記憶體。記憶體晶粒可以為SRAM。
堆疊可以垂直電氣連接，其中垂直電連接包含一導電聚合物。該導電聚合物可以為一導電環氧樹脂，例如填銀(具有混合有聚合物的銀粒子)、填金(具有混合有聚合物的金粒子)、導電環氧樹脂被填以金屬粒子(具有混合有聚合物的金屬粒子)。
電連接可以包含一或多數金屬導電元件黏結至在每一晶粒表面上的再定位墊位置，並由再定位墊實體及電氣延伸入垂直導體，使得導體的一端被內藏於導電聚合物內。金屬導電元件可以為一黏結線、黏結帶。金屬導電元件可以為金、鋁、銅、或鈀、或例如金、鋁、銅或鈀的導電材料的任意組合。金屬導電元件可以作成金屬引線架，具有黏結至晶粒的綁條，其後，金屬綁條被移除，以留下個別金屬導電元件或引線黏結至連接墊在晶粒上。架可以藉由在金屬薄板中穿孔加以形成。該架可以切割，以移除中心環或圖架，留下後面引線準備被附著至在晶粒上的黏結墊，或者，在引線被黏結至晶粒上的連接墊後，架也可以切割以移除外環或圖架。
所有連接墊可以同時”集團黏結”至晶粒上的連接墊。電連接也可以選擇地規劃，或配送獨特信號至為特定元件設計所需的半導體晶粒堆疊內的特定層半導體晶粒內。電連接可以連接至在堆疊中之一或多數另一晶粒上的對應連接，以一起連接在堆疊中之每一半導體晶粒的信號，如同特定元件設計所需。電氣連接可以扇出，使得來自堆疊中之不同晶粒的類似電連接可以在模組中之分開的特有連接點處取得(換句話說”並未共接”)。
半導體晶粒堆疊的安裝至基材上包含垂直內連線的電氣及實體連接至基材頂面上的電連接焊墊。電連接可以使用在晶粒堆疊垂直內連線與基材間之導電聚合物”點”或”水坑”加以完成。半導體晶粒堆疊的安裝至基材可以包含在堆疊中之最低晶粒的底部與基材頂面間之底膠黏著材料。底膠黏著材料可以為電絕緣材料、導熱材料，其中，底膠材料可以緩衝及吸收元件使用時，由於溫度變化所造成的部份物理應力。底膠材料可以延伸通過底部晶粒的緣部並在底晶粒及基材間形成一內圓填角。底膠材料可以延伸於底晶粒上，以在晶粒堆疊側與基材上的任意點與基材表面間，形成一內圓填角。底膠材料可以向上延伸於底晶粒，至晶粒堆疊中之第二、第三、第四或第n晶粒，或至堆疊的頂部。
堆疊的安裝至基材可以以預先形成在堆疊中之底晶粒及基材間之聚合物或環氧樹脂加以完成。在堆疊中之晶粒可以”朝上”、”朝下”、或”面對面”。基材可以具有多數導電層，用以信號、接地及電源連接，包含一或多數導電層。
基材可以包含一機構，用以完成於基材底部與一印刷電路板間之電氣連接，該電路板附著有堆疊晶粒元件的基材。基材可以具有錫球或凸塊，在底部上，用以連接至一印刷電路板。基材可以具有LGA接觸，用以連接至一印刷電路板，其中接觸具有一金表面、一焊錫塗層面、一銅面、一鋁面、一導電面(金屬面)。
基材可以具有撓性內連線接觸，用以連接至印刷電路板，包含平坦金屬連接墊(焊墊)，用以連接至一印刷電路板或用以附著錫球或凸塊。基材可以在頂面上具有電氣連接墊，用以至一堆疊的半導體晶粒。
基材可以具有電連接於在頂面上的墊與在基材底部上的錫球墊、錫凸塊墊、或平面連接墊(焊墊)之間。基材可以為多層，具有一或多數額外金屬層在底及頂導電層，並且，與頂及底導電層分隔開，並與接地面、電源面及其他在頂層之電路與在基材底層之電路間之信號連接。
一多層基材包含一或多數額外金屬層在頂及底導電層間，作散熱用。可以為多層之基材可以具有一或多數額外金屬層在頂及/或底導電層，作散熱用。基材可以包含有機材料，例如BT、FR4、聚醯亞胺或聚亞醯胺軟材。
該基材可以為撓性基材，例如軟帶或軟膜。基材可以由陶瓷材料、矽、晶片級基材所作成，其中晶片級基材為低於或等於1.2倍晶粒尺寸。
該總成可以選用地沒有任何其他塗層、模鑄、或覆蓋於晶粒上及垂直連接上。該總成的最上晶粒可以被覆蓋以一材料，以阻擋或衰減光，防止光碰撞及影響在總成中之半導體晶粒。該總成可以被塗覆以一貼護聚合物，例如聚對二甲苯基，其中貼護塗層可以為裝置的最終塗層。貼護塗層可以在進一步密封或轉移鑄模前被施加，例如裝置將被模鑄或密封。
該總成可以以聚合物、塑膠、或環氧樹脂加以模鑄，以完全地塗覆及覆蓋半導體晶粒堆疊及基材表面，使在基材底部的連接未被覆蓋並露出來，作電氣連接。總成可以在聚合物、塑膠或環氧樹脂中模鑄，以完全地覆蓋及密封半導體晶粒堆疊與元件的頂面。該模鑄可以為”轉移鑄模”程序。該總成可以為一散熱座所覆蓋、或在一鎧裝封裝中。
由於元件具有低電感、低電容、低直流電阻、及/或匹配交流阻抗，所以堆疊晶粒BGA元件係適用以高速電路。該元件可選用地具有接地及電源面包含在基材及/或晶粒內。
10．．．半導體晶粒
20．．．絕緣塗層
30．．．頂面
50．．．導電聚合物
60．．．連接墊
70．．．半導體晶粒
80．．．連接墊
90．．．位置
94．．．導電面
5．．．垂直堆疊總成元件
7．．．基材
70．．．核板
92‧‧‧防焊膜
40‧‧‧底膠
61‧‧‧導電元件
第1圖為一示意圖，顯示具有原始連接墊配置於晶粒中心，及再配線連接在晶粒中心的原始連接墊與在晶粒邊緣的新連接墊。
第2圖為半導體晶粒的剖面圖，顯示晶粒被塗覆以貼護絕緣塗層。
第3圖為半導體晶粒的剖面圖，顯示貼護塗層及在半導體晶粒中心原始連接墊上的貼護塗層中之開口。
第4圖為具有連接墊在晶粒週邊的半導體晶粒。
第5圖為具有週邊墊的半導體晶粒，該等週邊墊為原始或再配置並被塗覆以一貼護絕緣塗層，及在週邊配置電連接墊上的絕緣塗層中有開口。
第6圖為在BGA上的完成4層堆疊剖面圖，其可以被安裝並連接至適當基材。
5．．．垂直堆疊總成元件
7．．．基材
10．．．半導體晶粒
20．．．絕緣塗層
30．．．頂面
40．．．底膠
50．．．導電聚合物
60．．．連接墊
70．．．核板
80．．．連接墊
92．．．防焊膜
94．．．導電面

Claims (92)

  1. 一種半導體晶粒總成，包含至少一晶粒安裝在一基材上，該晶粒具有週邊電連接位置及該基材在其晶粒安裝側具有電連接焊墊，其中在該晶粒上之電連接位置係為一導電聚合物元件所電連接至在該基材上之電連接焊墊，其中該電連接位置係藉由導電元件電連接至該導電聚合物元件，該導電元件電連接至該晶粒上的連接位置並自該晶粒延伸入該導電聚合物元件。
  2. 如申請專利範圍第1項所述之總成，包含至少兩該晶粒彼此堆疊，及其中在該各個晶粒上之互連位置係為一導電聚合物元件所電連接至在該基材上之電連接焊墊，其中該電連接位置係為導電元件所電連接至該導電聚合物元件，該導電元件電連接至在該晶粒上的該連接位置並由該晶粒延伸進入該導電聚合物元件。
  3. 如申請專利範圍第1項所述之總成，更包含至少兩該晶粒，其中在該晶粒的第一晶粒上之一互連位置係被一導電聚合物元件所電連接至該晶粒的第二晶粒上之一互連位置，其中該電連接位置係為導電元件所電連接至該導電聚合物元件，該導電元件電連接至在該晶粒上的該連接位並由該晶粒延伸進入該導電聚合物元件。
  4. 如申請專利範圍第1項所述之總成，其中該在該晶粒上之該週邊互連位置包含原始週邊晶粒墊。
  5. 如申請專利範圍第1項所述之總成，其中該晶粒係被再配線以連接原始晶粒墊至週邊互連位置。
  6. 如申請專利範圍第1項所述之總成，更包含一電絕緣層位於該晶粒與該導電聚合物元件之間。
  7. 如申請專利範圍第6項所述之總成，其中該電絕緣層包含一保角塗層。
  8. 如申請專利範圍第7項所述之總成，其中該絕緣塗層在該互連位置之選定互連位置上有開口。
  9. 如申請專利範圍第7項所述之總成，其中該保角塗層包含聚合物。
  10. 如申請專利範圍第9項所述之總成，其中該保角塗層包含聚對二甲苯基。
  11. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件包含一絲線。
  12. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件包含一線。
  13. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件係定向大致垂直於該基材的該晶粒安裝側。
  14. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件包含一導電環氧樹脂。
  15. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件包含一填充環氧樹脂。
  16. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件包含一填銀環氧樹脂。
  17. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件包含一填金環氧樹脂。
  18. 如申請專利範圍第2項所述之總成，其中在該堆疊中之鄰接晶粒使用電絕緣材料加以彼此積層。
  19. 如申請專利範圍第18項所述之總成，其中該電絕緣材料包含導熱材料。
  20. 如申請專利範圍第18項所述之總成，其中該電絕緣材料包含聚合物。
  21. 如申請專利範圍第18項所述之總成，其中該電絕緣材料包含環氧樹脂。
  22. 如申請專利範圍第18項所述之總成，其中該電絕緣材料包含環氧樹脂預型物。
  23. 如申請專利範圍第18項所述之總成，其中該電絕緣材料包含間隔件。
  24. 如申請專利範圍第18項所述之總成，其中該電絕緣材料包含球型間隔件。
  25. 如申請專利範圍第23項所述之總成，其中該間隔件包含：玻璃、陶瓷、塑膠、鐵氟龍、聚合物、石英及其組合之一。
  26. 如申請專利範圍第20項所述之總成，其中該電絕緣材料更包含間隔件。
  27. 如申請專利範圍第26項所述之總成，其中該間隔件包含球體。
  28. 如申請專利範圍第26項所述之總成，其中該間 隔件包含：玻璃、陶瓷、塑膠、鐵氟龍、聚合物、石英及其組合之一。
  29. 如申請專利範圍第21項所述之總成，其中該電絕緣材料更包含間隔件。
  30. 如申請專利範圍第29項所述之總成，其中該間隔件包含球體。
  31. 如申請專利範圍第30項所述之總成，其中該間隔件包含：玻璃、陶瓷、塑膠、鐵氟龍、聚合物、石英及其組合之一。
  32. 如申請專利範圍第22項所述之總成，其中該環氧預型物包含間隔件。
  33. 如申請專利範圍第32項所述之總成，其中該間隔件包含球體。
  34. 如申請專利範圍第33項所述之總成，其中該間隔件包含：玻璃、陶瓷、塑膠、鐵氟龍、聚合物、石英及其組合之一。
  35. 如申請專利範圍第1項所述之總成，其中該導電元件包含一黏結線。
  36. 如申請專利範圍第1項所述之總成，其中該導電元件包含一黏結帶。
  37. 如申請專利範圍第1項所述之總成，其中該導電元件包含金屬。
  38. 如申請專利範圍第1項所述之總成，其中該導電元件包含金、鋁、銅及鈀、及其組合之一。
  39. 如申請專利範圍第1項所述之總成，其中該導電聚合物元件係為在該導電聚合物與基材間之導電材料所連接至該基材。
  40. 如申請專利範圍第39項所述之總成，其中該導電材料包含導電聚合物。
  41. 如申請專利範圍第1項所述之總成，更包含在該第一晶粒與該基材的該晶粒安裝面間之底膠。
  42. 如申請專利範圍第41項所述之總成，其中該底膠包含電絕緣材料。
  43. 如申請專利範圍第3項所述之總成，其中該導電聚合物元件係為該導電聚合物元件與基材間之導電材料所連接至該基材。
  44. 如申請專利範圍第43項所述之總成，其中該導電材料包含可導電聚合物。
  45. 如申請專利範圍第3項所述之總成，其中該至少兩晶粒包含一晶粒堆疊，並更包含在該晶粒堆疊中之第一晶粒與該基材之該晶粒安裝側間之一底膠。
  46. 如申請專利範圍第45項所述之總成，其中該底膠包含電絕緣材料。
  47. 如申請專利範圍第1項所述之總成，其中該晶粒被使用一黏著劑加以附著至該基材的該晶粒安裝側。
  48. 如申請專利範圍第1項所述之總成，其中該晶粒被使用一電絕緣黏著劑加以附著至該晶基材的該晶粒安裝側。
  49. 如申請專利範圍第3項所述之總成，其中該至少兩晶粒包含一晶粒堆疊，及其中該晶粒堆疊使用一黏著劑附著至該基材的該晶粒安裝側。
  50. 如申請專利範圍第3項所述之總成，其中該至少兩晶粒包含一晶粒堆疊，及其中該晶粒堆疊使用一電絕緣黏著劑附著至該基材的該晶粒安裝側。
  51. 如申請專利範圍第1項所述之總成，其中該基材包含至少一導電層及至少一介電層。
  52. 如申請專利範圍第1項所述之總成，其中該基材包含一多層基材。
  53. 如申請專利範圍第1項所述之總成，其中該基材包含至少兩導電層及至少一絕緣層。
  54. 如申請專利範圍第52項所述之總成，其中該基材包含一接地面。
  55. 如申請專利範圍第52項所述之總成，其中該基材包含一電源面。
  56. 如申請專利範圍第1項所述之總成，其中該基材包含散熱層。
  57. 如申請專利範圍第1項所述之總成，其中該基材為一焊墊柵陣列基材，在與該晶粒安裝側相反的一側上具有焊墊。
  58. 如申請專利範圍第1項所述之總成，其中該基材為一球柵陣列基材，在與該晶粒安裝側相反的一側上具有焊墊。
  59. 如申請專利範圍第1項所述之總成，其中該至少一晶粒係被定向使得該晶粒的該作用面背向該基材。
  60. 如申請專利範圍第1項所述之總成，其中該至少一晶粒係被定向使得該晶粒的該作用側面向該基材。
  61. 如申請專利範圍第1項所述之總成，其中該至少兩晶粒係被定向使得該晶粒的該作用側面向與該基材相同的方向。
  62. 如申請專利範圍第41項所述之總成，其中該底膠延伸通過該第一晶粒的緣。
  63. 如申請專利範圍第41項所述之總成，其中該底膠在該第一晶粒與該基材間形成內圓填角。
  64. 如申請專利範圍第63項所述之總成，其中該內圓填角延伸在該基材上並至該晶粒的一側。
  65. 如申請專利範圍第45項所述之總成，其中該底膠延伸通過該第一晶粒的緣部。
  66. 如申請專利範圍第45項所述之總成，其中該底膠在該晶粒堆疊的一側與該基材間形成一內圓填角。
  67. 如申請專利範圍第66項所述之總成，其中該內圓填角延伸在該基材上至該第一晶粒的一側。
  68. 如申請專利範圍第66項所述之總成，其中該內圓填角延伸在該基材上至該晶粒堆疊中之另一晶粒的一側。
  69. 如申請專利範圍第66項所述之總成，其中該內圓填角延伸在該基材上至該晶粒堆疊的一側。
  70. 如申請專利範圍第66項所述之總成，其中該內圓填角延伸在該基材上至該晶粒堆疊的一面。
  71. 如申請專利範圍第1項所述之總成，其中該總成被模鑄。
  72. 如申請專利範圍第71項所述之總成，其中該模鑄材料位於該第一晶粒與該基材之該晶粒安裝面之間。
  73. 如申請專利範圍第71項所述之總成，其中該模鑄材料覆蓋該晶粒的一側及至少該導電聚合物元件之一部份。
  74. 如申請專利範圍第71項所述之總成，其中該模鑄材料覆蓋所有的該晶粒。
  75. 如申請專利範圍第71項所述之總成，其中該模鑄使得該晶粒的一表面曝露。
  76. 如申請專利範圍第1項所述之總成，其中該總成被密封。
  77. 如申請專利範圍第76項所述之總成，其中該密封材料延伸於該第一晶粒與該基材的該晶粒安裝面之間。
  78. 如申請專利範圍第76項所述之總成，其中該密封材料覆蓋該晶粒的一側及至少該導電聚合物元件的一部份。
  79. 如申請專利範圍第76項所述之總成，其中該密封材料覆蓋所有的該晶粒。
  80. 如申請專利範圍第76項所述之總成，其中該密封使得該晶粒的一表面曝露。
  81. 如申請專利範圍第3項所述之總成，其中該總成被模鑄。
  82. 如申請專利範圍第81項所述之總成，其中該模鑄材料位於該第一晶粒與該基材的該晶粒安裝面之間。
  83. 如申請專利範圍第81項所述之總成，其中該模鑄材料覆蓋該晶粒堆疊的一側及至少該導電聚合物元件的一部份。
  84. 如申請專利範圍第81項所述之總成，其中該模鑄材料覆蓋在該晶粒堆疊中之所有的該晶粒。
  85. 如申請專利範圍第81項所述之總成，其中該模鑄使得該晶粒堆疊的一表面曝露。
  86. 如申請專利範圍第3項所述之總成，其中該總成被密封。
  87. 如申請專利範圍第86項所述之總成，其中該密封材料延伸於該第一晶粒與該基材的該晶粒安裝面之間。
  88. 如申請專利範圍第86項所述之總成，其中該密封材料覆蓋該晶粒堆疊的一側及至少該導電聚合物元件的一部份。
  89. 如申請專利範圍第86項所述之總成，其中該密封材料覆蓋所有在該晶粒堆疊中的該晶粒。
  90. 如申請專利範圍第86項所述之總成，其中該密封使得該晶粒的一表面曝露。
  91. 如申請專利範圍第1項所述之總成，更包含一保角總成塗層。
  92. 如申請專利範圍第3項所述之總成，更包含一保角總成塗層。
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JP5639052B2 (ja) 2008-06-16 2014-12-10 テッセラ，インコーポレイテッド ウェハレベルでの縁部の積重ね

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EP1763894A2 (en) 2007-03-21
US20070284716A1 (en) 2007-12-13
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US8729690B2 (en) 2014-05-20
US8357999B2 (en) 2013-01-22
US20050230802A1 (en) 2005-10-20
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