JPS61239649A - 高速集積回路パツケ−ジ - Google Patents

高速集積回路パツケ−ジ

Info

Publication number
JPS61239649A
JPS61239649A JP60077549A JP7754985A JPS61239649A JP S61239649 A JPS61239649 A JP S61239649A JP 60077549 A JP60077549 A JP 60077549A JP 7754985 A JP7754985 A JP 7754985A JP S61239649 A JPS61239649 A JP S61239649A
Authority
JP
Japan
Prior art keywords
integrated circuit
wirings
speed
wiring
semiconductor integrated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP60077549A
Other languages
English (en)
Other versions
JPH0325082B2 (ja
Inventor
Akira Miyauchi
彰 宮内
Hiroshi Nishimoto
央 西本
Tadashi Okiyama
沖山　正
Hiroo Kitasagami
北相模　博夫
Masahiro Sugimoto
杉本　正浩
Haruo Tamada
玉田　春男
Shinji Emori
江森　伸二
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP60077549A priority Critical patent/JPS61239649A/ja
Priority to CA000505739A priority patent/CA1249379A/en
Priority to KR1019860002694A priority patent/KR900007299B1/ko
Priority to AT86400782T priority patent/ATE61696T1/de
Priority to DE8686400782T priority patent/DE3678023D1/de
Priority to EP86400782A priority patent/EP0199635B1/en
Publication of JPS61239649A publication Critical patent/JPS61239649A/ja
Priority to US07/214,838 priority patent/US4827327A/en
Publication of JPH0325082B2 publication Critical patent/JPH0325082B2/ja
Priority to SG456/92A priority patent/SG45692G/en
Priority to HK469/92A priority patent/HK46992A/xx
Granted legal-status Critical Current

Links

Classifications

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    • H05K2201/10409—Screws
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10689—Leaded Integrated Circuit [IC] package, e.g. dual-in-line [DIL]
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/325—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by abutting or pinching, i.e. without alloying process; mechanical auxiliary parts therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Waveguide Connection Structure (AREA)
  • Waveguides (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔概要〕 半導体集積回路チップを搭載した多層配線基板に於ける
層間配線の接続部を、伝搬される信号の種類に対応して
インダクタンス成分が異なるように構成し、高速動作の
半導体集積回路チップによる動作特性を改善したもので
ある。
〔産業上の利用分野〕
本発明は、数Ｇビット／Ｓ程度の高速データを　　　　
　　゛　　□、□ 処理する半導体集積回路チップを多層配線基板上　　　
　　　　　６、。
に搭載して気密封止した高速集積回路パンケージ　　　
　　　　　′−゛□ ；、・ に関するものである。　　　　　　　　　　　　　　　
　　　　　　１ｓｔ（シリコン）やＧａＡｓ　　（ガリ
ウム砒素）７、等の半導体チップに複数のトランジスタ
等を形成　　　　　　　　゛して、数Ｇビット／Ｓ程度
の高速データ処理を行う半導体集積回路チップが製作さ
れており、このような半導体集積回路チップは、信頼性
確保の為にパッケージによって気密封止する必要がある
。
〔従来の技術〕
高速集積回路パッケージは、例えば、第３図の概略断面
図に示すように、多層配線基板１５上に半導体集積回路
チップ１８を搭載し、この半導体集積回路チップ１８と
外部端子となる配線１７とを金線等の接続線１９で接続
し、多層配線基板の周辺に絶縁体２０を介して金属のキ
ャンプ２１を接合して、半導体集積回路チップ１８を気
密封止するものである。なお、１６はアース等となる下
面の金属配線である。
半導体集積回路チップ１８を搭載する多層配線基板１５
は、例えば、グリーンシートの状態で所望の配線を施し
且つ」二下層の配線の接続用のスルーポールを形成し、
順次積層して焼成するものである。その場合の各層の配
線の幅は同一で且つ層間の配線を接続する為のスルーホ
ールの直径も同一である。
〔発明が解決しようとする問題点〕
多層配線基板１５には、半導体集積回路チ、ツブ１８上
のトランジスタ等に電源を供給する為の配線や、高速信
号が伝搬する配線が混在しているものであり、前述のよ
うに、これらの配線の幅及び各層の配線間を接続する為
の接続部の直径も同一　　□である。即ち、従来は、直
流電流が流れる径路も、高周波信号が流れる径路も同一
の構成のものである。その為、高速動作可能の半導体集
積回路チップ１８の特性を充分に引き出すことが困難で
あった。
１　　　　　′″Ｑ１９［・＊ＩＩ’／Ｉｔ（ＫＭ　（
７）ｉ’ｔｈ　ｌ　ｉ’ｋＨ（Ｄ　４７９’　９タンス
成分を小さくし、電源供給用の径路のインダクタンス成
分を大きくして、高速動作の半導体集積回路チップの特
性を充分に発揮させることを目的とするものである。
Ｃ問題点を解決するための手段〕 本発明の高速集積回路パッケージは、第１図を参照して
説明すると、半導体集積回路チップを搭載する多層配線
基板の高周波信号が伝搬する配線ｌａ、ｌｂ、Ｉｃ間を
接続する接続部４ａ、４ｂの直径を大きくしてインダク
タンス成分を小さくし、又電源供給用の配線２ａ、　　
２ｂ、２Ｃ間を接続する接続部５ａ、５ｂの直径を小さ
く或いは長さを長くしてインダクタンス成分を大きくし
たものである。
〔作用〕
高周波信号が伝搬する配線間は、インダクタンス成分の
小さい接続部４ａ、４ｂで接続されるので、伝搬遅延を
受けることが少なくなり、それによって高速動作の半導
体集積回路チップの特性を充分に引き出すことができ、
又電源供給用の配線間は、インダクタンス成分の大きい
接続部５ａ。
５ｂで接続されるので、電源供給用の配線に重畳される
高周波信号を減衰させ、異なる電源間のアイソレーショ
ン特性を向上させることができる。
〔実施例〕
以下図面を参照して、本発明の実施例について詳細に説
明する。
第１図は本発明の実施例の要部断面図であり、半導体集
積回路チップやキャップ等の図示を省略している。セラ
ミック等の絶縁基板６に、各層の配線１ａ、ｌｂ、ｌｃ
、２ａ、２ｂ、２ｃ、３ａ、３ｂが形成され、配線１ａ
、Ｉｂ、ｌｃには高周波信号が伝搬し、配線２ａ、２ｂ
、２ｃには電源供給用として直流電流が流れるものとす
ると、高周波信号が伝搬する配線１ａ、ｌ’ｂ’、ｌｃ
間を接続する接続部４ａ、４ｂの直径を大きくしてイン
ダクタンス成分を小さくし、又直流電流のみが流れる配
線２ａ、　　２ｂ、’ｌｃ間を接続する接続部５ａ、５
ｂの直径を小さく或いは長くしてインダクタンス成分を
大きくするものである。
高周波信号が伝搬する配線１ａ、ｌｂ、ｌｃ間はインダ
クタンス成分の小さい接続部４ａ、４ｂにより接続され
るものであるから、高速動作の半導体集積回路チップへ
の入力データ又は出力データの遅延や波形歪が小さくな
り、高速動作の半導体集積回路チップの特性を充分に引
き出すことができる。
又電源供給用としての配線２ａ、　　２ｂ、２Ｃ間はイ
ンダクタンス成分の大きい接続部５ａ、５ｂにより接続
されるものであるから、半導体集積回　　　　　　　１
路チツプに対する電源供給用の配線に於ける耐雑音特性
を向上することができる。この接続部５ａ　　　　　　
　゛。
、５ｂは、インダクタンス成分を大きくする為に、その
長さを５ｂのように長くすることもでき、　　　　　　
　　。
又接続用の孔内に螺旋、或いは折返線路を形成す　　　
　　　　。
ることもできる。
第２図は本発明の他の実施例の要部断面図であり、多層
配線基板のうちの一層について示すものである。同図に
於いて、１０は絶縁基板、１１゜１２は配線、１３はコ
イルである。これらの配線（６）　　　　　　　　　　
　　　　　　　゛・１１．１２間はコイル１３で接続さ
れている。このコイル１３はインダクタンス成分を大き
くする為のものであり、例えば、グリーンシートに配線
間の接続用の孔を開け、この孔中に微細コイルを捩じ込
んで構成することができる。この微細コイルは、積層し
たグリーンシートの焼成温度に耐えられるようなタング
ステンやモリブデン等により構成することが好適である
。又この微細コイルと配線１１．１２との接続は、例え
ば、グリーンシート上に配線１１．１２を形成する導電
性塗料を塗布し、接続用孔に捩じ込んだ微細コイルの端
部にも導電性塗料を塗布して焼成すれば良いことになる
。
コイルのインダクタンスＩ、は、 で表される。なお、Ｒはコイルの半径、Ｎは巻数、ｌは
コイルの長さ、μ、は比透磁率、Ｋは長岡係数である。
１　　　　　　　例えば、配線１１．１２間の絶縁基板
１０の厚さに対応して、コイルの長さｊ２−２５００μ
ｍ１接続用の孔の直径に対応して、コイルの半径Ｒを１
０００μｍ１巻数Ｎを１０とすると、インダクタンスし
は１２０　ｎ　Ｈとなり、１．８ＧＴ（ｚでは、インピ
ーダンスＺは１．３にΩとなるから、電源供給用の配線
に、ノイズ除去等のインダクタンスを挿入した場合と同
じ構成となり、高速動作の半導体集積回路チップへの電
源供給用として、耐雑音特性を向上することができる。
〔発明の効果〕
以上説明したように、本発明は、半導体集積回路チップ
１８を多層配線基板１５に搭載してキャンプ２１により
気密封止した高速集積回路パッケージに於いて、多層配
線基板１５に於ける高周波信号が伝搬する配線１ａ、ｌ
ｂ、ｌｃ間を直径を大きくしてインダクタンス成分を小
さくした接続部４ａ、４ｂで接続し、電源供給用の配線
２ａ。
２ｂ、２ｃ間を、直径を小さく、或いは長さを長くして
インダクタンス成分を太き（した接続部５ａ、５ｂで接
続したものであり、多層配線基板を製作する時に、配線
の種類に対応して異なる大きさの接続用孔を形成するこ
とになるが、高速動作の半導体集積回路チ・ノブ１８の
動作特性を阻害することなく、電源供給並びに信号の入
出力を行わせることができる利点がある。
【図面の簡単な説明】
第１図は本発明の実施例の要部断面図、第２図は本発明
の他の実施例の要部断面図、第３図は集積回路パッケー
ジの概略断面図である。 ｌａ、ｌｂ、ｌｃ、２ａ、２ｂ、２ｃ、３ａ。 ３ｂ、１１．１２は配線、４ａ、４ｂ、５ａ、５ｂは接
続部、６．１０は絶縁基板、１３はコイル、１５は多層
配線基板、１６．１７は配線、１８は半導体集積回路チ
ップ、１９は接続線、２０は絶縁体、２１はキャンプで
ある。

Claims (1)

  1. 【特許請求の範囲】 　半導体集積回路チップを多層配線基板に搭載してキャ
    ップにより気密封止した高速集積回路パッケージに於い
    て、 前記多層配線基板の高周波信号が伝搬する配線（１ａ、
    １ｂ、１ｃ）間をインダクタンス成分の小さい接続部（
    ４ａ、４ｂ）で接続し、 電源供給用の配線（２ａ、２ｂ、２ｃ）間をインダクタ
    ンス成分の大きい接続部（５ａ、５ｂ）で接続した ことを特徴とする高速集積回路パッケージ。
JP60077549A 1985-04-13 1985-04-13 高速集積回路パツケ−ジ Granted JPS61239649A (ja)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP60077549A JPS61239649A (ja) 1985-04-13 1985-04-13 高速集積回路パツケ−ジ
CA000505739A CA1249379A (en) 1985-04-13 1986-04-03 Integrated circuit device having stacked conductive layers connecting circuit elements therethrough
KR1019860002694A KR900007299B1 (ko) 1985-04-13 1986-04-09 회로소자 연결용 축적 도전층을 갖는 집적회로장치
EP86400782A EP0199635B1 (en) 1985-04-13 1986-04-11 Integrated circuit device having stacked conductive layers connecting circuit elements therethrough
DE8686400782T DE3678023D1 (de) 1985-04-13 1986-04-11 Integrierte schaltungsanordnung mit gestapelten leiterschichten zum verbinden von schaltungselementen.
AT86400782T ATE61696T1 (de) 1985-04-13 1986-04-11 Integrierte schaltungsanordnung mit gestapelten leiterschichten zum verbinden von schaltungselementen.
US07/214,838 US4827327A (en) 1985-04-13 1988-07-05 Integrated circuit device having stacked conductive layers connecting circuit elements therethrough
SG456/92A SG45692G (en) 1985-04-13 1992-04-24 Integrated circuit device having stacked conductive layers connecting circuit elements therethrough
HK469/92A HK46992A (en) 1985-04-13 1992-06-25 Integrated circuit device having stacked conductive layers connecting circuit elements therethrough

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60077549A JPS61239649A (ja) 1985-04-13 1985-04-13 高速集積回路パツケ−ジ

Publications (2)

Publication Number Publication Date
JPS61239649A true JPS61239649A (ja) 1986-10-24
JPH0325082B2 JPH0325082B2 (ja) 1991-04-05

Family

ID=13637092

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60077549A Granted JPS61239649A (ja) 1985-04-13 1985-04-13 高速集積回路パツケ−ジ

Country Status (9)

Country Link
US (1) US4827327A (ja)
EP (1) EP0199635B1 (ja)
JP (1) JPS61239649A (ja)
KR (1) KR900007299B1 (ja)
AT (1) ATE61696T1 (ja)
CA (1) CA1249379A (ja)
DE (1) DE3678023D1 (ja)
HK (1) HK46992A (ja)
SG (1) SG45692G (ja)

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JPH05501658A (ja) * 1989-11-28 1993-04-02 レオコーア　インコーポレーテッド 小輪郭カテーテル
JPH06291520A (ja) * 1992-04-03 1994-10-18 Matsushita Electric Ind Co Ltd 高周波多層集積回路
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JP2010500844A (ja) * 2006-08-22 2010-01-07 イー．エム．ダブリュ．アンテナ カンパニー リミテッド 伝送線路
JP4815535B2 (ja) * 2006-08-22 2011-11-16 イーエムダブリュ カンパニー リミテッド 伝送線路
JP2010050358A (ja) * 2008-08-22 2010-03-04 Sharp Corp 半導体装置
CN108447857A (zh) * 2013-12-20 2018-08-24 乾坤科技股份有限公司 三维空间封装结构及其制造方法
CN108447857B (zh) * 2013-12-20 2021-09-07 乾坤科技股份有限公司 三维空间封装结构及其制造方法

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CA1249379A (en) 1989-01-24
SG45692G (en) 1992-06-12
KR860008600A (ko) 1986-11-17
EP0199635B1 (en) 1991-03-13
EP0199635A3 (en) 1987-11-19
HK46992A (en) 1992-07-03
JPH0325082B2 (ja) 1991-04-05
US4827327A (en) 1989-05-02
ATE61696T1 (de) 1991-03-15
KR900007299B1 (ko) 1990-10-08
EP0199635A2 (en) 1986-10-29
DE3678023D1 (de) 1991-04-18

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