KR860008600A - 회로소자 연결용 축적 도전층을 갖는 집적회로 장치 - Google Patents
회로소자 연결용 축적 도전층을 갖는 집적회로 장치 Download PDFInfo
- Publication number
- KR860008600A KR860008600A KR1019860002694A KR860002694A KR860008600A KR 860008600 A KR860008600 A KR 860008600A KR 1019860002694 A KR1019860002694 A KR 1019860002694A KR 860002694 A KR860002694 A KR 860002694A KR 860008600 A KR860008600 A KR 860008600A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive
- integrated circuit
- layer
- circuit device
- conductive means
- Prior art date
Links
- 238000009825 accumulation Methods 0.000 claims 10
- 230000001939 inductive effect Effects 0.000 claims 5
- 239000004020 conductor Substances 0.000 claims 3
- 238000000034 method Methods 0.000 claims 3
- 230000001186 cumulative effect Effects 0.000 claims 1
- 238000012856 packing Methods 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 239000003566 sealing material Substances 0.000 claims 1
- 238000009413 insulation Methods 0.000 abstract 2
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
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- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/184—Components including terminals inserted in holes through the printed circuit board and connected to printed contacts on the walls of the holes or at the edges thereof or protruding over or into the holes
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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- H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
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- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
- H05K3/4046—Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Semiconductor Integrated Circuits (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Waveguide Connection Structure (AREA)
- Waveguides (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Abstract
내용 없음
Description
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 제2도의 선 X-X'를 취한 본 발명에 의한 일실시예의 집적회로 장치(IC)의 단면도.
제2도는 제1도의 선 H-H'를 취한 제1도의 IC장치의 평면도.
제3도는 제1도에 보인 IC장치의 회로도.
Claims (16)
- 절연층(11-1b)와 상기 절연층(11-1b)의 표면상에 형성되는 적어도 하나의 도전층띠(11-1a)를 각각 갖는 다수의 축적층들(11-1 내지 11-6)을 포함하는 축적층 수단(11)과, 다수의 회로소자들을 포함하는 상기 축적층수단(11)내의 상기 축적층들(11-1 내지 11-6)의 상기 절연층(11-1b)상에 장착되는 적어도 하나의 칩(3)과, 제1신호들을 상기 칩(3)내의 상기 회로소자들간에 전송시키도록 동작가능하게 연결시키는 인가되는 상기 제1신호용 저유도성분을 갖는 상기 축적층 수단(11)내에 형성되는 제1도 전수단(13)과, 제2신호들을 상기 칩(3)내의 상기 회로소자들간에 전송시키도록 동작가능하게 연결시키는 상기 제1도 전수단(13)의 것보다 상기 제1신호에 대해 더 큰 유도성분을 갖는 상기 축적층 수단(11)내에 형성되는 제2도전수단(14)와 그리고 상기 축적층수단(11), 상기 칩(3)과 상기 제1 및 제2도전수단(13 및 14)을 밀봉재로 봉합시키는 포장수단(21 내지 24)을 포함하는 것이 특징인 회로소자 연결용 축적도전층을 갖는 집적회로 장치.
- 제1항에서, 상기 제1도전수단(13)을 통하여 정송되는 상기 제1신호들은 고주파신호이고, 상기 제2도 전수단(14)을 통해 전송되는 상기 제2신호들은 저주파신호 또는 전원인 것이 특징인 회로소자 연결용 축적도전층을 갖는 집적회로 장치.
- 제2항에서 상기 제1 및 제2도전수단(13 및 14) 각각은 그의 일단부들에서 상이한 절연층들 (11-1b)상에 위치한 어떤 축적층에 있는 상기 도전층띠(11-1a)둘중 하나 또는 두 도전층띠들(11-1a)에 동작가능하게 연결되며 상기 축적층 수단(11)의 상기 절연층들(11-1b)내에 형성되는 경유공들(12-1 내지 12-3)을 포함하는 것이 특징인 회로소자 연결용 축적도전층을 갖는 집적회로 장치.
- 제3항에서, 상기 제1도전수단(13)의 각각은 큰 횡단면적을 갖고 있으며 또한 상기 제2도전수단(14)의 각각은 작은 횡단면적을 갖고있는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제4항에서, 상기 제1 및 제2도전수단(13 및 14)은 동일 도전재로 형성되는 것이 특징인 회로소자 연결용 축적도전층을 갖는 집적회로 장치.
- 제5항에서 상기 제1도전수단(13) 각각의 상기 횡단면적은 예정된 저유도성분이 상기 제1신호용으로 얻어지도록 한정되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제6항에서, 상기 제2도전수단(14) 각각의 상기 횡단면적은 예정된 고유도성분이 상기 제1신호용으로 얻어지도록 한정되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제3항에서, 상기 제1도전수단(13)의 각각은 상기 경유공(12-1 내지 12-3)의 축상선을 따라 짧은 거리를 가지며, 상기 제2도전수단 각각은 상기 축상선을 따라 긴 기장을 갖는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제8항에서, 상기 제1 및 제2도전수단(13 및 14)는 동일 도전재질로 형성되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제9항에서, 상기 제1도전수단(13) 각각의 상기 짧은 기장은 예정된 저유도성분이 상기 제1성분용으로 얻어지는 식으로 한정되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제10항에서, 상기 제2도전수단(14) 각각의 긴 기장은 예정된 고유도성분이 상기 제1신호용으로 얻어지도록 한정되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제3항에서, 상기 제1도전수단(13) 각각은 상기 경유공(12-1 내지 12-3)의 축상선을 따라 큰 횡단면적과 짧은 기장을 가지며, 상기 제2도전수단(14) 각각은 상기 축상선을 따라 작은 횡단면적과 긴 기장을 갖는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제12항에서, 상기 제1 및 제2도전수단(13 및 14)는 동일 도전재질로 형성되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제13항에서, 상기 제1도전수단(13) 각각의 상기 짧은 기장과 큰 횡단면적은 예정된 저 유도성분이 상기 제1신호용으로 얻어지는 식으로 한정되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제14항에서, 상기 제2도전소자(14) 각각의 상기 긴 기장과 작은 횡단면적은 예정된 고유도성분이 상기 제1신호용으로 얻어지는 식으로 한정되는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.
- 제3항에서, 상기 제2도전수단(14)은 고유도성분을 갖고 있으며 또한 관통공들(12-1 내지 12-3) 내에 삽입되는 코일들을 포함하는 것이 특징인 회로소자 연결용 축적 도전층을 갖는 집적회로 장치.※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
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JP77549 | 1985-04-13 | ||
JP60077549A JPS61239649A (ja) | 1985-04-13 | 1985-04-13 | 高速集積回路パツケ−ジ |
JP60-077549 | 1985-04-13 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR860008600A true KR860008600A (ko) | 1986-11-17 |
KR900007299B1 KR900007299B1 (ko) | 1990-10-08 |
Family
ID=13637092
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1019860002694A KR900007299B1 (ko) | 1985-04-13 | 1986-04-09 | 회로소자 연결용 축적 도전층을 갖는 집적회로장치 |
Country Status (9)
Country | Link |
---|---|
US (1) | US4827327A (ko) |
EP (1) | EP0199635B1 (ko) |
JP (1) | JPS61239649A (ko) |
KR (1) | KR900007299B1 (ko) |
AT (1) | ATE61696T1 (ko) |
CA (1) | CA1249379A (ko) |
DE (1) | DE3678023D1 (ko) |
HK (1) | HK46992A (ko) |
SG (1) | SG45692G (ko) |
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-
1985
- 1985-04-13 JP JP60077549A patent/JPS61239649A/ja active Granted
-
1986
- 1986-04-03 CA CA000505739A patent/CA1249379A/en not_active Expired
- 1986-04-09 KR KR1019860002694A patent/KR900007299B1/ko not_active IP Right Cessation
- 1986-04-11 AT AT86400782T patent/ATE61696T1/de not_active IP Right Cessation
- 1986-04-11 DE DE8686400782T patent/DE3678023D1/de not_active Expired - Fee Related
- 1986-04-11 EP EP86400782A patent/EP0199635B1/en not_active Expired - Lifetime
-
1988
- 1988-07-05 US US07/214,838 patent/US4827327A/en not_active Expired - Fee Related
-
1992
- 1992-04-24 SG SG456/92A patent/SG45692G/en unknown
- 1992-06-25 HK HK469/92A patent/HK46992A/xx unknown
Also Published As
Publication number | Publication date |
---|---|
CA1249379A (en) | 1989-01-24 |
JPH0325082B2 (ko) | 1991-04-05 |
EP0199635B1 (en) | 1991-03-13 |
KR900007299B1 (ko) | 1990-10-08 |
HK46992A (en) | 1992-07-03 |
US4827327A (en) | 1989-05-02 |
JPS61239649A (ja) | 1986-10-24 |
EP0199635A3 (en) | 1987-11-19 |
SG45692G (en) | 1992-06-12 |
ATE61696T1 (de) | 1991-03-15 |
EP0199635A2 (en) | 1986-10-29 |
DE3678023D1 (de) | 1991-04-18 |
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