KR840005921A - 전자 장치 - Google Patents

전자 장치 Download PDF

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Publication number
KR840005921A
KR840005921A KR1019830002968A KR830002968A KR840005921A KR 840005921 A KR840005921 A KR 840005921A KR 1019830002968 A KR1019830002968 A KR 1019830002968A KR 830002968 A KR830002968 A KR 830002968A KR 840005921 A KR840005921 A KR 840005921A
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KR
South Korea
Prior art keywords
insulating film
chip
semiconductor
base
metal
Prior art date
Application number
KR1019830002968A
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English (en)
Other versions
KR910007101B1 (ko
Inventor
오오루 이나반
Original Assignee
미쓰다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Application filed by 미쓰다 가쓰시게, 가부시기가이샤 히다찌세이사꾸쇼 filed Critical 미쓰다 가쓰시게
Publication of KR840005921A publication Critical patent/KR840005921A/ko
Application granted granted Critical
Publication of KR910007101B1 publication Critical patent/KR910007101B1/ko

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Insulated Metal Substrates For Printed Circuits (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

내용 없음

Description

전자 장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 실시예인 IC칩의 전형적 평면도.
제2도는 제1도의 도시한 IC칩에 있어서의 Ⅴ-Ⅴ선 절단 확대 단면도.
제3도는 마찬가지로 제1도의 칩에 있어서의 Ⅳ-Ⅳ선 절단 확대 단면도.

Claims (8)

  1. 기체와 그 기체 주면위에 형성된 전기적 절연막과 금속배선에 의해 배선 구조체와를 구비한 칩으로 되는 전자 장치로서 상기 첩 주변에 형성된 상기 금속 배선과의 사이에 상기 기체에 접속하는 금속으로 된 보호전극을 상기 전기적 절연막을 관통하여 설치된 것을 특징으로 하는 전자 장치.
  2. 특허 청구 범위 제1항에 있어서 전기적 절연막은 유기 수지에 의해 된다.
  3. 기체와 그 기체 주면위에 형성된 전기적 절연막과 금속 배선에 의해서된 배선 구조체와를 구비하는 칩으로 되는 전자 장치로서 상기 칩 외주와 상기 칩 주변에 형성된 상기 금속 배선과의 사이에 상기 기체의 주표면에 형성된 凹부 또는 단부에 접속하는 금속으로된 보호 전극을 상기 전기적 절연막을 관통하여 설치한 것을 특징으로 하는 전자 장치.
  4. 특허 청구 범위 제3항에 있어서, 전기적 절연막은 유기 수지에 의해 된다.
  5. 반도체 기체의 주면에 형성된 다수개의 반도체 소자를 전기적으로 접속하는 배선층과, 상기 반도체 기체 및 배선층을 덮어쓰것 같이 형성된 절연막과를 구비하는 반도체 칩으로 된 반도체 장치에 있어서, 칩의 외부와 칩 주변에 형성된 배선층과의 사이에 상기 반도체 기체에 접속하는 금속으로 된 보호전극을 상기절연막을 관통해서 설치한 것을 특징으로 한 반도체 장치.
  6. 특허 청구 범위 제5항에 있어서, 절연막은 유기 절연재료에 의해서 된는.
  7. 반도체 기체의 주면에 형성된 다수개의 반도체 소자를 전기적으로 접속하는 배선층과, 상기 반도체 기체 및 배선층을 덮어쓴 것 같이 형성된 절연막과를 구비하는 반도체 칩으로된 반도체 장치에 잇어서, 칩의 금속으로된 보호전극을 상기 절연막을 관통하여 설치한 것을 특징으로 하는 반도체 장치.
  8. 특허 청구 범위 제7항에 있어서, 절연막은 유기 절연재료에 의해 된다.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019830002968A 1982-09-24 1983-06-30 반도체 장치 KR910007101B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP164839 1982-09-24
JP57164839A JPS5955037A (ja) 1982-09-24 1982-09-24 半導体装置
JP?57-164839 1982-09-24

Publications (2)

Publication Number Publication Date
KR840005921A true KR840005921A (ko) 1984-11-19
KR910007101B1 KR910007101B1 (ko) 1991-09-18

Family

ID=15800899

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019830002968A KR910007101B1 (ko) 1982-09-24 1983-06-30 반도체 장치

Country Status (7)

Country Link
US (1) US4841354A (ko)
JP (1) JPS5955037A (ko)
KR (1) KR910007101B1 (ko)
DE (1) DE3331624C2 (ko)
FR (1) FR2533750B1 (ko)
GB (1) GB2128025B (ko)
IT (1) IT1168293B (ko)

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JPS60138940A (ja) * 1983-12-27 1985-07-23 Toshiba Corp 半導体装置の製造方法
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US5111276A (en) * 1985-03-19 1992-05-05 National Semiconductor Corp. Thick bus metallization interconnect structure to reduce bus area
JPS61283160A (ja) * 1985-06-10 1986-12-13 Mitsubishi Electric Corp 半導体記憶装置
JPH0715970B2 (ja) * 1985-09-26 1995-02-22 富士通株式会社 半導体装置の製造方法
JPS62194644A (ja) * 1986-02-20 1987-08-27 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2557898B2 (ja) * 1987-07-31 1996-11-27 株式会社東芝 半導体装置
JPH077783B2 (ja) * 1988-03-18 1995-01-30 株式会社東芝 電気的接続部に銅もしくは銅合金製金属細線を配置する半導体装置
US5187558A (en) * 1989-05-08 1993-02-16 Mitsubishi Denki Kabushiki Kaisha Stress reduction structure for a resin sealed semiconductor device
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JP3144817B2 (ja) * 1990-03-23 2001-03-12 株式会社東芝 半導体装置
JPH04256371A (ja) * 1991-02-08 1992-09-11 Toyota Autom Loom Works Ltd 半導体装置及びその製造方法
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US5430325A (en) * 1992-06-30 1995-07-04 Rohm Co. Ltd. Semiconductor chip having dummy pattern
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JP3504421B2 (ja) * 1996-03-12 2004-03-08 株式会社ルネサステクノロジ 半導体装置
TW448524B (en) * 1997-01-17 2001-08-01 Seiko Epson Corp Electronic component, semiconductor device, manufacturing method therefor, circuit board and electronic equipment
US6137155A (en) * 1997-12-31 2000-10-24 Intel Corporation Planar guard ring
US6562674B1 (en) * 1999-07-06 2003-05-13 Matsushita Electronics Corporation Semiconductor integrated circuit device and method of producing the same
US6614118B1 (en) * 1999-12-15 2003-09-02 Intel Corporation Structures to mechanically stabilize isolated top-level metal lines
DE10126955A1 (de) * 2001-06-01 2002-12-05 Philips Corp Intellectual Pty Integrierte Schaltung mit energieabsorbierender Struktur
JP4608208B2 (ja) * 2003-12-25 2011-01-12 セイコーエプソン株式会社 電子回路装置及びその製造方法
JP4501715B2 (ja) * 2005-02-16 2010-07-14 セイコーエプソン株式会社 Ｍｅｍｓ素子およびｍｅｍｓ素子の製造方法
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Also Published As

Publication number Publication date
KR910007101B1 (ko) 1991-09-18
JPS5955037A (ja) 1984-03-29
JPH0373136B2 (ko) 1991-11-20
FR2533750B1 (fr) 1986-01-24
GB2128025B (en) 1986-05-21
IT8322982A0 (it) 1983-09-23
IT1168293B (it) 1987-05-20
IT8322982A1 (it) 1985-03-23
DE3331624C2 (de) 1994-01-20
US4841354A (en) 1989-06-20
FR2533750A1 (fr) 1984-03-30
GB8324765D0 (en) 1983-10-19
DE3331624A1 (de) 1984-03-29
GB2128025A (en) 1984-04-18

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