KR910001947A - 반도체 디바이스 제조 방법 - Google Patents

반도체 디바이스 제조 방법 Download PDF

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KR910001947A
KR910001947A KR1019900009127A KR900009127A KR910001947A KR 910001947 A KR910001947 A KR 910001947A KR 1019900009127 A KR1019900009127 A KR 1019900009127A KR 900009127 A KR900009127 A KR 900009127A KR 910001947 A KR910001947 A KR 910001947A
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layer
attaching
pillar
silicon oxide
organic
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KR1019900009127A
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KR0157980B1 (ko
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도미니쿠스 요셉 베르하르 로베르투스
데 브루인 린데르트
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프레데릭 얀 스미트
엔. 브이. 필립스 글로아이람펜파브리켄
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76897—Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/1147—Manufacturing methods using a lift-off mask
    • H—ELECTRICITY
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1301—Shape
    • H01L2224/13016—Shape in side view
    • H01L2224/13017—Shape in side view being non uniform along the bump connector
    • H—ELECTRICITY
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

내용 없음

Description

반도체 디바이스 제조 방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도 내지 제5도는 본 발명의 방법에 따른 제1실시예를 설명하기 위한 반도체 디바이스의 부분 단면도.

Claims (7)

  1. 하나의 주요면 인접부에 절연 영역과 경계를 이루는 디바이스 영역을 갖는 반도체 본체를 제공하는 단계와, 상기 하나의 주요면상에 유기층을 형성하기 위하여 유동질의 유기물을 부착함으로서 디바이스 영역에 전기 접속부를 제공하는 단계와, 디바이스 영역의 접속부를 노출시키는 개구를 형성하기 위하여 상기 유기층을, 하층의 디바이스와 절연 영역에 대해 마스킹층내의 윈도우를 통해서 선별적으로 에칭하는 단계와, 개구내에 접속부와 접착된 전도성의 기둥을 형성하도록 전기 전도체를 부착하는 단계를 구비한 반도체 디바이스 제조 방법에 있어서, 전도성 기둥이 노출되도록 유기층을 제거하는 단계와, 상기 기둥을 덮도록 절연층을 제공하는 단계와, 기둥의 상부면이 노출되도록 절연층을 에칭하는 단계와, 상기 기둥에 접속되도록 전도체를 부착하는 단계를 특징으로 하는 반도체 디바이스 제조 방법.
  2. 제1항에 있어서, 중합체를 유동질의 유기질로서 사용하는 것을 특징으로 하는 반도체 디바이스 제조 방법.
  3. 제2항에 있어서, 마스킹층은 실리콘 산화물, 실리콘 질화물, 보로포스포실리사이트 글래스 및 스핀-온-글래스로 구성된 그룹으로부터 선정된 재질층으로 한정되고, 유기층은 반응성 이온 에칭 처리를 이용하여 마스킹층을 통해서 에칭하는 것을 특징으로 하는 반도체 디바이스 제조 방법.
  4. 제1항, 제2항 또는 제3항에 있어서, 전도성의 기둥을 형성하기 위하여 텅스텐을 선택적으로 부착하는 것을 특징으로 하는 반도체 디바이스 제조 방법.
  5. 제1항, 제2항 또는 제3항에 있어서, 유기층에 텅스텐을 부작함으로서 전도성 기둥을 형성한 후에, 개구내에서 전도성 기둥이 도출되는 유기층을 노출시키도록 텅스텐 층을 에칭하는 것을 특징으로 하는 반도체 디바이스 제조 방법.
  6. 제4항 또는 제5항에 있어서, 유동질의 유기질을 부착하기 전에 주요면상에 핵 형성층을 제공하고, 유기층을 제거한 후에 핵 형성층의 노출부분을 제거하는 것을 특징으로 하는 반도체 디바이스 제조 방법.
  7. 선행항중의 어느 한 항에 있어서, 실리콘 산화물층을 부착함으로서 절연층을 제공하고, 평판을 제공하기위해 실리콘 산화물층상에 저항층을 부착한 후에 그 위의 층을 에칭하여서, 실리콘 산화물층 및 저항층은 동일한 비율로 에칭하여서 전도성 기둥의 상부면의 노출부는 비교적 평면이 제공되는 것을 특징으로 하는 반도체 디바이스 제조 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019900009127A 1989-06-26 1990-06-21 반도체 디바이스 제조방법 KR0157980B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB8914626A GB2233494A (en) 1989-06-26 1989-06-26 Providing an electrode on a semiconductor device
GB8914626.0 1989-06-26

Publications (2)

Publication Number Publication Date
KR910001947A true KR910001947A (ko) 1991-01-31
KR0157980B1 KR0157980B1 (ko) 1999-02-01

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EP (1) EP0405660B1 (ko)
JP (1) JP2776960B2 (ko)
KR (1) KR0157980B1 (ko)
DE (1) DE69018884T2 (ko)
GB (1) GB2233494A (ko)

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Publication number Priority date Publication date Assignee Title
US5466636A (en) * 1992-09-17 1995-11-14 International Business Machines Corporation Method of forming borderless contacts using a removable mandrel
KR970007819B1 (en) * 1993-10-21 1997-05-17 Hyundai Electronics Ind Contact forming method of semiconductor device
KR0137978B1 (ko) * 1994-10-12 1998-06-15 김주용 반도체 소자 제조방법
EP0708481A3 (en) * 1994-10-20 1997-04-02 Hughes Aircraft Co Improved thermal bumps for higher performance flipchip type monolithic integrated circuits and manufacturing processes
FR2771854B1 (fr) * 1997-11-28 2001-06-15 Sgs Thomson Microelectronics Procede de realisation d'interconnexions metalliques dans des circuits integres
DE10021865C2 (de) * 2000-05-05 2002-08-01 Infineon Technologies Ag Elektronisches Bauteil mit einem Halbleiterchip und elektronisches Bauteil mit einer Teststruktur auf einem Halbleiterchip sowie Verfahren zu deren Herstellung
DE102006030267B4 (de) 2006-06-30 2009-04-16 Advanced Micro Devices, Inc., Sunnyvale Nano-Einprägetechnik mit erhöhter Flexibilität in Bezug auf die Justierung und die Formung von Strukturelementen
US9889239B2 (en) 2007-03-23 2018-02-13 Allegiance Corporation Fluid collection and disposal system and related methods
AU2008232361B2 (en) 2007-03-23 2013-05-16 Allegiance Corporation Fluid collection and disposal system and related methods
WO2011008961A1 (en) 2009-07-15 2011-01-20 Allegiance Corporation Fluid collection and disposal system and related methods

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JPS5476076A (en) * 1977-11-30 1979-06-18 Fujitsu Ltd Manufacture for semiconductor device
FR2476913B1 (fr) * 1980-02-25 1985-09-13 Nippon Electric Co Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit
US4541168A (en) * 1984-10-29 1985-09-17 International Business Machines Corporation Method for making metal contact studs between first level metal and regions of a semiconductor device compatible with polyimide-filled deep trench isolation schemes
EP0195977B1 (en) * 1985-03-15 1994-09-28 Hewlett-Packard Company Metal interconnection system with a planar surface
US4702792A (en) * 1985-10-28 1987-10-27 International Business Machines Corporation Method of forming fine conductive lines, patterns and connectors
EP0257948A3 (en) * 1986-08-25 1988-09-28 AT&T Corp. Conductive via plug for cmos devices
EP0262719B1 (en) * 1986-09-30 1993-12-15 Koninklijke Philips Electronics N.V. Method for manufacturing a planar electrical interconnection utilizing isotropic deposition of conductive material
US4751101A (en) * 1987-04-30 1988-06-14 International Business Machines Corporation Low stress tungsten films by silicon reduction of WF6

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GB2233494A (en) 1991-01-09
EP0405660A3 (en) 1992-01-02
EP0405660A2 (en) 1991-01-02
DE69018884T2 (de) 1995-12-07
JPH0334539A (ja) 1991-02-14
EP0405660B1 (en) 1995-04-26
JP2776960B2 (ja) 1998-07-16
DE69018884D1 (de) 1995-06-01
GB8914626D0 (en) 1989-08-16
KR0157980B1 (ko) 1999-02-01

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