FR2476913B1 - Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit - Google Patents

Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit

Info

Publication number
FR2476913B1
FR2476913B1 FR8103559A FR8103559A FR2476913B1 FR 2476913 B1 FR2476913 B1 FR 2476913B1 FR 8103559 A FR8103559 A FR 8103559A FR 8103559 A FR8103559 A FR 8103559A FR 2476913 B1 FR2476913 B1 FR 2476913B1
Authority
FR
France
Prior art keywords
manufacturing
same
scale integration
layered circuit
layered
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
FR8103559A
Other languages
English (en)
Other versions
FR2476913A1 (fr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2247180A external-priority patent/JPS56118396A/ja
Priority claimed from JP2247280A external-priority patent/JPS56118397A/ja
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Publication of FR2476913A1 publication Critical patent/FR2476913A1/fr
Application granted granted Critical
Publication of FR2476913B1 publication Critical patent/FR2476913B1/fr
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/01—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate comprising only passive thin-film or thick-film elements formed on a common insulating substrate
    • H01L27/016—Thin-film circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4644—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4647—Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits by applying an insulating layer around previously made via studs
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0315—Oxidising metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0703—Plating
    • H05K2203/0733—Method for plating stud vias, i.e. massive vias formed by plating the bottom of a hole without plating on the walls
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/11—Treatments characterised by their effect, e.g. heating, cooling, roughening
    • H05K2203/1142—Conversion of conductive material into insulating material or into dissolvable compound
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing the conductive pattern
    • H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
FR8103559A 1980-02-25 1981-02-23 Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit Expired FR2476913B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2247180A JPS56118396A (en) 1980-02-25 1980-02-25 Method of forming conductive layer of circuit board
JP2247280A JPS56118397A (en) 1980-02-25 1980-02-25 Method of forming conductive layer of circuit board

Publications (2)

Publication Number Publication Date
FR2476913A1 FR2476913A1 (fr) 1981-08-28
FR2476913B1 true FR2476913B1 (fr) 1985-09-13

Family

ID=26359700

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8103559A Expired FR2476913B1 (fr) 1980-02-25 1981-02-23 Circuit a plusieurs couches pour integration a grande echelle et procede de fabrication de ce circuit

Country Status (2)

Country Link
US (1) US4434544A (fr)
FR (1) FR2476913B1 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4494131A (en) * 1980-10-31 1985-01-15 Rikagaku Kenkyusho Josephson junction element and method of making the same
GB2111312A (en) * 1981-11-04 1983-06-29 Philips Electronic Associated Substrates for electrical circuits
US4628149A (en) * 1981-11-30 1986-12-09 Nippon Electric Co., Ltd. Substrate having a pattern of an alloy of gold and a noble and a base metal with the pattern isolated by oxides of the noble and the base metals
JPS5975695A (ja) * 1982-10-23 1984-04-28 日本碍子株式会社 セラミツク厚膜回路基板
DE3314879A1 (de) * 1983-04-25 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von stabilen, niederohmigen kontakten in integrierten halbleiterschaltungen
US4657778A (en) * 1984-08-01 1987-04-14 Moran Peter L Multilayer systems and their method of production
US4772935A (en) * 1984-12-19 1988-09-20 Fairchild Semiconductor Corporation Die bonding process
US4866008A (en) * 1987-12-11 1989-09-12 Texas Instruments Incorporated Methods for forming self-aligned conductive pillars on interconnects
KR920005459B1 (ko) * 1988-08-30 1992-07-04 가부시기가이샤 히다찌세이사꾸쇼 금속의 균질화방법 및 회로기판
GB2233494A (en) * 1989-06-26 1991-01-09 Philips Nv Providing an electrode on a semiconductor device
US5358902A (en) * 1989-06-26 1994-10-25 U.S. Philips Corporation Method of producing conductive pillars in semiconductor device
GB2233820A (en) * 1989-06-26 1991-01-16 Philips Nv Providing an electrode on a semiconductor device
US5127998A (en) * 1990-01-02 1992-07-07 General Electric Company Area-selective metallization process
JP2551224B2 (ja) * 1990-10-17 1996-11-06 日本電気株式会社 多層配線基板および多層配線基板の製造方法
US5143867A (en) * 1991-02-13 1992-09-01 International Business Machines Corporation Method for depositing interconnection metallurgy using low temperature alloy processes
JP3271272B2 (ja) * 1991-11-12 2002-04-02 日本電気株式会社 半導体装置の製造方法
US5361967A (en) * 1993-11-10 1994-11-08 Motorola, Inc. Monolithic circuit fabrication method
US6586683B2 (en) * 2001-04-27 2003-07-01 International Business Machines Corporation Printed circuit board with mixed metallurgy pads and method of fabrication
CN102962639B (zh) * 2012-11-10 2015-01-28 华中科技大学 一种真空扩散焊制备多层非晶合金微小零件的方法
US9147662B1 (en) * 2013-12-20 2015-09-29 Stats Chippac Ltd. Integrated circuit packaging system with fiber-less substrate and method of manufacture thereof
JP6904094B2 (ja) * 2016-06-23 2021-07-14 三菱マテリアル株式会社 絶縁回路基板の製造方法
CN115537722B (zh) * 2022-09-27 2023-08-11 深圳市黄金屋真空科技有限公司 同表面层导电黑和绝缘黑的制备工艺和产品

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3808049A (en) * 1972-06-02 1974-04-30 Microsystems Int Ltd Multi-layer thin-film circuits
DE2554691C2 (de) * 1974-12-10 1982-11-18 Western Electric Co., Inc., 10038 New York, N.Y. Verfahren zum Herstellen elektrischer Leiter auf einem isolierenden Substrat und danach hergestellte Dünnschichtschaltung

Also Published As

Publication number Publication date
US4434544A (en) 1984-03-06
FR2476913A1 (fr) 1981-08-28

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Legal Events

Date Code Title Description
ST Notification of lapse