KR890003000A - 반도체 장치의 제조방법 - Google Patents

반도체 장치의 제조방법 Download PDF

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Publication number
KR890003000A
KR890003000A KR1019880008344A KR880008344A KR890003000A KR 890003000 A KR890003000 A KR 890003000A KR 1019880008344 A KR1019880008344 A KR 1019880008344A KR 880008344 A KR880008344 A KR 880008344A KR 890003000 A KR890003000 A KR 890003000A
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KR
South Korea
Prior art keywords
polysilicon
film
manufacturing
semiconductor device
polyvinyl alcohol
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Application number
KR1019880008344A
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English (en)
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KR930001499B1 (ko
Inventor
모도기 고바야시
Original Assignee
하시모도 나미오
오끼뎅끼 고오교오 가부시끼가이샤
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Application filed by 하시모도 나미오, 오끼뎅끼 고오교오 가부시끼가이샤 filed Critical 하시모도 나미오
Publication of KR890003000A publication Critical patent/KR890003000A/ko
Application granted granted Critical
Publication of KR930001499B1 publication Critical patent/KR930001499B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only
    • H01L21/32136—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas
    • H01L21/32137—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Plasma & Fusion (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Weting (AREA)
  • Semiconductor Memories (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

내용 없음

Description

반도체 장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제 1 도(a) 내지 제 1 도 (d)는 본 발명의 반도체 장치의 제조 방법의 일 실시예를 설명하기 위한 공정 단면도. 제 2 도는 동상 실시예의 파묻음용 폴리실리콘의 평탄화를 설명하기 위한 단면도. 제 3 도는(a) 내지 제 3 도(c)는 종래의 반도체 장치의 제조 방법을 설명하기 위한 공정 단면도.

Claims (1)

  1. (a) 회로소자 혹은 전극 배선막을 설치한 반도체기판의 트랜치 구멍, 홈 등의 심구를 형성한 후 이 심구를 폴리실리콘으로서 파묻는 공정과, (b)폴리비닐알을 수용액에 의한 평탄화재로서 상기 폴리실리콘 상에 도포하여 폴리비닐알콜막을 형성하는 공정과, (c)상기 폴리비닐알콜막의 에칭속도와 상기 폴리실리콘막의 에칭 속도의 비가 1대1로부터 1대2가 되는 드라이 에칭 조건으로 상기 반도체 기판의 표면 전면을 에칭하는 공정과에 의하여 이루어지는 반도체 장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019880008344A 1987-07-07 1988-07-06 반도체 장치의 제조방법 KR930001499B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP16786487 1987-07-07
JP87-167864 1987-07-07

Publications (2)

Publication Number Publication Date
KR890003000A true KR890003000A (ko) 1989-04-12
KR930001499B1 KR930001499B1 (ko) 1993-03-02

Family

ID=15857499

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019880008344A KR930001499B1 (ko) 1987-07-07 1988-07-06 반도체 장치의 제조방법

Country Status (2)

Country Link
US (1) US4810669A (ko)
KR (1) KR930001499B1 (ko)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0834242B2 (ja) * 1988-12-08 1996-03-29 日本電気株式会社 半導体装置およびその製造方法
JP3216104B2 (ja) * 1991-05-29 2001-10-09 ソニー株式会社 メタルプラグ形成方法及び配線形成方法
US5317432A (en) * 1991-09-04 1994-05-31 Sony Corporation Liquid crystal display device with a capacitor and a thin film transistor in a trench for each pixel
US5292689A (en) * 1992-09-04 1994-03-08 International Business Machines Corporation Method for planarizing semiconductor structure using subminimum features
JP3724592B2 (ja) * 1993-07-26 2005-12-07 ハイニックス セミコンダクター アメリカ インコーポレイテッド 半導体基板の平坦化方法
JP2001326273A (ja) * 2000-05-16 2001-11-22 Denso Corp 半導体装置の製造方法
US6498381B2 (en) * 2001-02-22 2002-12-24 Tru-Si Technologies, Inc. Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same
US6639784B1 (en) * 2002-10-30 2003-10-28 National Semiconductor Corporation Wedge-shaped high density capacitor and method of making the capacitor
TWI365880B (en) * 2004-03-30 2012-06-11 Euro Celtique Sa Process for preparing oxycodone hydrochloride having less than 25 ppm 14-hydroxycodeinone and oxycodone hydrochloride composition,pharmaceutical dosage form,sustained release oeal dosage form and pharmaceutically acceptable package having less than 25 pp
JP2006019455A (ja) * 2004-06-30 2006-01-19 Nec Electronics Corp 半導体装置およびその製造方法
CN103311112B (zh) * 2013-06-14 2016-01-27 矽力杰半导体技术(杭州)有限公司 在沟槽内形成多晶硅的方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4038110A (en) * 1974-06-17 1977-07-26 Ibm Corporation Planarization of integrated circuit surfaces through selective photoresist masking
US4046595A (en) * 1974-10-18 1977-09-06 Matsushita Electronics Corporation Method for forming semiconductor devices
JPS574172A (en) * 1980-06-09 1982-01-09 Canon Inc Light conductive member
JPS60170951A (ja) * 1984-02-16 1985-09-04 Nec Corp 素子分離方法
JPS60226128A (ja) * 1984-04-25 1985-11-11 Matsushita Electronics Corp 半導体装置の製造方法
JPS60226141A (ja) * 1984-04-25 1985-11-11 Matsushita Electronics Corp 半導体装置の製造方法
US4627988A (en) * 1985-07-29 1986-12-09 Motorola Inc. Method for applying material to a semiconductor wafer
US4741926A (en) * 1985-10-29 1988-05-03 Rca Corporation Spin-coating procedure
JPS6377122A (ja) * 1986-09-19 1988-04-07 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
KR930001499B1 (ko) 1993-03-02
US4810669A (en) 1989-03-07

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