KR910013507A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR910013507A
KR910013507A KR1019890019283A KR890019283A KR910013507A KR 910013507 A KR910013507 A KR 910013507A KR 1019890019283 A KR1019890019283 A KR 1019890019283A KR 890019283 A KR890019283 A KR 890019283A KR 910013507 A KR910013507 A KR 910013507A
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KR
South Korea
Prior art keywords
layer
forming
insulating
manufacturing
semiconductor device
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KR1019890019283A
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English (en)
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KR930001658B1 (ko
Inventor
다다시 야마모토
다케시 다나카
유수케 고오야마
Original Assignee
아오이 죠이치
가부시키가이샤 도시바
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Publication of KR910013507A publication Critical patent/KR910013507A/ko
Application granted granted Critical
Publication of KR930001658B1 publication Critical patent/KR930001658B1/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Semiconductor Memories (AREA)

Abstract

내용 없음.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 1실시예에 관계되는 반도체장치의 제조방법을 도시한 단면도.

Claims (4)

  1. 반도체기판(101)을 선택적으로 에칭하여 그 반도체기판(101)에 구(105)를 형성하는 공정과, 상기 구(105)의 측면 및 저면에 도전성 제1층(107)을 형성하는 공정과, 상기 도전성 제1층(107) 윗면 및 상기 반도체기판(101)의 윗면에 절연성 제2층(108)을 형성하는 공정과, 상기 절연성 제2층(108) 위에 도전성 제3층(109)을 형성하는 공정과, 상기 도전성 제3층(109)을 패터닝 하여 캐패시터용 전극을 형성하는 공정과, 상기 캐패시터용 전극을 피복하는 절연성 제4층(110)을 형성하는 공정과, 상기 절연성 제4층(110) 위에 상기 구(105)를 매립하는 제5층(111)을 형성하는 공정과, 상기 제5층(111)이 상기 구(105)내에만 잔존하도록 제5층(111)을 에칭하는 공정과, 상기 제5층(111) 위에 절연성 제6층(112)을 형성하는 공정을 구비한 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 절연성 제2층이 실리콘 산화막, 실리콘질화막 및 실리콘 산화막으로 이루어진 3층 구성으로 형성된 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제1항에 있어서, 상기 제5층(111)이 다결정성실리콘층으로 된 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제1항에 있어서, 상기 제5층(111)이 스핀도포법에 의해 형성된 실리콘산화막으로 된 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019890019283A 1988-07-25 1989-12-22 반도체장치의 제조방법 KR930001658B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP63185083A JP2593524B2 (ja) 1988-07-25 1988-07-25 半導体装置の製造方法
JP63-185083 1988-07-25

Publications (2)

Publication Number Publication Date
KR910013507A true KR910013507A (ko) 1991-08-08
KR930001658B1 KR930001658B1 (ko) 1993-03-08

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
KR1019890019283A KR930001658B1 (ko) 1988-07-25 1989-12-22 반도체장치의 제조방법

Country Status (3)

Country Link
US (1) US5066609A (ko)
JP (1) JP2593524B2 (ko)
KR (1) KR930001658B1 (ko)

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US5225698A (en) * 1989-08-12 1993-07-06 Samsung Electronics Co., Inc. Semi-conductor device with stacked trench capacitor
KR970001894B1 (en) * 1991-09-13 1997-02-18 Nippon Electric Kk Semiconductor memory device
JP2601176B2 (ja) * 1993-12-22 1997-04-16 日本電気株式会社 半導体記憶装置
JPH07254640A (ja) * 1993-12-30 1995-10-03 Texas Instr Inc <Ti> スタック・トレンチ・コンデンサ形成工程におけるトレンチ分離構造形成方法
US5451809A (en) * 1994-09-07 1995-09-19 Kabushiki Kaisha Toshiba Smooth surface doped silicon film formation
US5936271A (en) * 1994-11-15 1999-08-10 Siemens Aktiengesellschaft Unit cell layout and transfer gate design for high density DRAMs having a trench capacitor with signal electrode composed of three differently doped polysilicon layers
US6020609A (en) * 1997-10-31 2000-02-01 Texas Instruments - Acer Incorporated DRAM cell with a rugged stacked trench (RST) capacitor
KR100253406B1 (ko) * 1998-01-20 2000-04-15 김영환 반도체 파워 집적회로에서의 소자격리구조 및 그 방법
US6093606A (en) * 1998-03-05 2000-07-25 Taiwan Semiconductor Manufacturing Company Method of manufacture of vertical stacked gate flash memory device
US6271557B1 (en) * 1999-10-05 2001-08-07 Infineon Technologies Ag Center node for deep trench capacitors
US9608130B2 (en) * 2011-12-27 2017-03-28 Maxim Integrated Products, Inc. Semiconductor device having trench capacitor structure integrated therein

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JPS56157044A (en) * 1980-05-09 1981-12-04 Hitachi Ltd Insulating isolation of semiconductor element
JPS57204133A (en) * 1981-06-10 1982-12-14 Hitachi Ltd Manufacture of semiconductor integrated circuit
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JPH0666436B2 (ja) * 1983-04-15 1994-08-24 株式会社日立製作所 半導体集積回路装置
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JPS60213053A (ja) * 1984-04-09 1985-10-25 Oki Electric Ind Co Ltd 半導体メモリ素子
JPS60234361A (ja) * 1984-05-07 1985-11-21 Nec Corp Ｍｉｓ型半導体記憶装置の製造方法
JPS60253263A (ja) * 1984-05-30 1985-12-13 Hitachi Ltd 半導体装置
KR900000170B1 (ko) * 1984-06-05 1990-01-23 가부시끼가이샤 도오시바 다이내믹형 메모리셀과 그 제조방법
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JPS61152062A (ja) * 1984-12-26 1986-07-10 Hitachi Ltd 半導体装置の製造方法
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Also Published As

Publication number Publication date
KR930001658B1 (ko) 1993-03-08
JP2593524B2 (ja) 1997-03-26
JPH0234962A (ja) 1990-02-05
US5066609A (en) 1991-11-19

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