KR970030682A - 반도체장치 및 그 제조방법 - Google Patents

반도체장치 및 그 제조방법 Download PDF

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KR970030682A
KR970030682A KR1019960057884A KR19960057884A KR970030682A KR 970030682 A KR970030682 A KR 970030682A KR 1019960057884 A KR1019960057884 A KR 1019960057884A KR 19960057884 A KR19960057884 A KR 19960057884A KR 970030682 A KR970030682 A KR 970030682A
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dielectric film
resin material
forming
semiconductor device
containing silicon
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순페이 야마자끼
타케시 후쿠나가
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순페이 야마자끼
가부시키가이샤 한도오따이 에네루기 켄큐쇼
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Abstract

신뢰성 있는 전극 접촉부를 가지는 반도체 장치는 첫째로, 중간층 유전체 막이 수지 물질로 형성되고, 다음에, 창문 홀이 형성된다. 중간층 유전체 막은 산소 플라즈마에 의해서 리세스된다. 이것은 창문 홀을 테이퍼링하게 한다. 이것으로 비록 회로 패턴이 복잡할지라도 접촉이 용이하게 된다.

Description

반도체장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음

Claims (13)

  1. 반도체장치에 있어서, 상기 반도체장치는; 수지 물질로 제조되는 상부층을 포함하는 다층 유전체막과; 상기 다층 유전체막 내에 형성된 접촉 홀로 구성되며, 상기 접촉홀은 상기 수지 물질의 상기 상부층 내에서 과잉 에칭되는 것을 특징으로 하는 반도체 장치.
  2. 제 1항에 있어서, 수지 물질로 제조되는 상기 상부층은 평평한 표면을 가지는 것을 특징으로 하는 반도체장치.
  3. 반도체장치에 있어서, 상기 반도체장치는; 실리콘을 포함하는 한 유전체막과, 수지 물질로 제조되는 다른 유전체막으로 구성되는 다층 유전체막을 포함하며, 수지 물질로 제조되는 상기 다른 유전체막이 상기 한 유전체막에 적층되며, 상기 다층 유전체막의 최하위 층이 실리콘을 함유하는 것을 특징으로 하는 반도체장치.
  4. 제 3항에 있어서, 실리콘을 함유한 상기 한 유전체 막은 실리콘 산화, 실리콘 질화, 및 실리콘 산질화 물질을 구성하는 그룹으로부터 선택되는 물질을 포함하는 것을 특징으로 하는 반도체장치.
  5. 반도체장치를 제조하는 방법에 있어서, 상기 방법은; 실리콘을 함유한 유전체 막을 형성하는 단계와; 실리콘을 함유한 상기 유전체 막에 수지 물질로부터 제 2유전체 막을 형성하는 단계와, 그것에 의해서 실리콘을 함유한 상기 유전체 막 및 상기 제 2유전체 막을 포함하는 다층막을 형성하게 되며; 상기 다층 막내에 접촉 홀을 형성하는 단계와; 상기 접촉 홀내에 개구를 확대하기 위해서 상기 수지 물질을 선택적으로 에칭하기 위한 수단을 이용하여 상기 수지 물질을 균등하게 에칭하는 단계를 포함하는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  6. 제 5항에 있어서, 상기 개구를 확대하기 위해서 상기 수지 물질을 균등하게 에칭하기 위한 상기 단계가 상기 접촉 홀을 형성하기 위해서 이용되는 저항 마스크를 균등하게 에칭함으로서 수행되는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  7. 반도체장치를 제조하는 방법에 있어서, 상기 방법은; 실리콘을 함유한 유전체 막을 형성하는 단계와; 실리콘을 함유한 상기 유전체 막에 수지 물질로부터 제 2유전체 막을 형성하는 단계와, 그것에 의해서 실리콘을 함유한 상기 유전체 막 및 상기 제 2유전체 막을 포함하는 다층막을 형성하게 되며; 상기 다층 막내에 접촉 홀을 형성하는 단계와; 상기 접촉 홀 주위에 테이퍼링하는 창문홀을 형성하기 위해서 상기 수지 물질을 선택적으로 에칭하기 위한 수단을 이용하여 상기 수지 물질을 균등하게 에칭하는 단계를 포함하는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  8. 제 7항에 있어서, 상기 수지 물질으 상기 제 2유전체 막은 평평화 표면을 가지는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  9. 제 7항에 있어서, 실리콘을 함유한 상기 한 유전체 막은 실리콘 산화, 실리콘 질화, 및 실리콘 산질화 물질을 구성하는 그룹으로부터 선택되는 물질을 포함하는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  10. 반도체장치를 제조하는 방법에 있어서, 상기 방법은; 실리콘을 함유한 유전체 막을 형성하는 단계와; 실리콘을 함유한 상기 유전체 막에 수지 물질로부터 제 2유전체 막을 형성하는 단계와, 그것에 의해서 실리콘을 함유한 상기 유전체 막 및 상기 제 2유전체 막을 포함하는 다층막을 형성하게 되며; 상기 다층 막에 얇은 금속 막을 형성하는 단계와; 상기 얇은 금속막을 선택적으로 에칭하는 단계와; 마스크로서 상기 얇은 금속 막을 이용하여, 상기 다층 막내에 접촉 홀을 형성하는 단계와; 상기 수지 물질을 선택적으로 에칭하기 위한 수단을 이용하여, 상기 수지 물질을 균등하게 에칭하는 단계를 포함하는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  11. 제 10항에 있어서, 상기 접촉 홀을 형성하는 단계 및 상기 수지 물질을 균등하게 에칭하는 단계는 대기에 노출하지 않고 건식 에칭에 의해서 연속하여 수행되는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  12. 반도체장치를 제조하는 방법에 있어서, 상기 방법은; 실리콘을 함유한 유전체 막을 형성하는 단계와; 실리콘을 함유한 상기 유전체 막에 수지 물질로부터 제 2유전체 막을 형성하는 단계와, 그것에 의해서 실리콘을 함유한 상기 유전체 막 및 상기 제 2유전체 막을 포함하는 다층막을 형성하게 되며; 상기 다층 막에 실리콘을 함유하는 제 3유전체 막을 형성하는 단계와; 실리콘을 함유하는 제 3유전체 막을 선택적으로 에칭하는 단계와; 마스크로서 상기 에칭된 제 3유전체 막을 이용하여, 상기 다층 막내에 접촉홀을 형성하는 단계와; 상기 수지물질을 선택적으로 에칭하기 위한 수단을 이용하여, 상기 수지 물질을 균등하게 에칭하는 단계를 포함하는 것을 특징으로 하는 반도체장치를 제조하는 방법.
  13. 제 12항에 있어서, 상기 접촉 홀을 형성하는 단계 및 상기 수지 물질을 균등하게 에칭하는 단계는 대기에 노출하지 않고 건식 에칭에 의해서 연속하여 수행되는 것을 특징으로 하는 반도체장치를 제조하는 방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019960057884A 1995-11-27 1996-11-27 반도체장치및그제조방법 KR100318839B1 (ko)

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US5814529A (en) * 1995-01-17 1998-09-29 Semiconductor Energy Laboratory Co., Ltd. Method for producing a semiconductor integrated circuit including a thin film transistor and a capacitor
US6800875B1 (en) * 1995-11-17 2004-10-05 Semiconductor Energy Laboratory Co., Ltd. Active matrix electro-luminescent display device with an organic leveling layer
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