KR950015677A - 반도체장치의 제조방법 - Google Patents

반도체장치의 제조방법 Download PDF

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Publication number
KR950015677A
KR950015677A KR1019940028918A KR19940028918A KR950015677A KR 950015677 A KR950015677 A KR 950015677A KR 1019940028918 A KR1019940028918 A KR 1019940028918A KR 19940028918 A KR19940028918 A KR 19940028918A KR 950015677 A KR950015677 A KR 950015677A
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South Korea
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organic film
etching
connecting electrode
manufacturing
semiconductor device
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KR1019940028918A
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English (en)
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KR0142136B1 (ko
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다게시 와까바야시
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가시오 가즈오
가시오 게이상기 가부시끼가이샤
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Publication of KR950015677A publication Critical patent/KR950015677A/ko
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Publication of KR0142136B1 publication Critical patent/KR0142136B1/ko

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Abstract

본 발명은 반도체장치의 제조방법에 있어서 수지 등의 유기재료로 구성되는 유기막의 표면층이 처리공정에서 변질하여 절연성이 저하해도 이 변질에 의한 악영향이 생기지 않도록 할 수 있는 제조방법을 개시하는 것으로, 이 반도체장치의 제조방법에서는 반도체기판의 일면에 설치되고, 유기재료로 구성되는 유기막의 개구부를 통하여 노출된 접속용전극의 표면산화막을 알곤을 이용한 드라이에칭으로 제거할 때에 이 처리에 의해 유기막의 표면층이 변질하여 절연성이 저하하지만, 이 후, 접속용전극의 위에 돌기전극을 형성한 후에 유기막의 변질된 표면층을 산소를 이용한 드라이에칭에 의해 제거한다.
이 결과, 유기막의 표면에 변질한 표면층이 잔존하지 않으므로 절연불량의 악영향이 생기지 않는다.

Description

반도체장치의 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1E도는 포토레지스트와 중간접속막형성용 막 및 금박막형성용 박막의 불필요부분을 제거한 상태를 도시한다.

Claims (10)

  1. 반도체기관(1)의 일면에 접속용전극(4)을 설치하는 공정, 상기 접속용전극(4)의 표면에 적어도 일부를 노출하는 개구부(8)를 갖는 유기막(7)을 상기 기판(1)의 일면에 설치하는 공정, 상기 접속용전극(4)의 노출된 표면을 에칭하는 공정, 상기 접속용전극(4)에 적층하여 돌기전극(14)을 설치하는 공정, 상기 유기막(7)의 표면을 에칭하는 공정, 으로 구성되는 것을 특징으로 하는 반도체장치의 제조방법.
  2. 제1항에 있어서, 상기 접속용전극(4)의 노출된 표면을 에칭하는 공정에 있어서, 그 처리는 드라이에칭에 의해 실행됨과 동시에 상기 유기막(7)의 표면을 에칭하는 공정에 있어서, 그 처리는 드라이에칭에 의해 실행되는 것을 특징으로 하는 반도체장치의 제조방법.
  3. 제2항에 있어서, 상기 접속용전극(4)의 노출된 표면을 에칭하는 공정에 있어서, 그 처리의 드라이에칭은 알곤을 이용하여 실행됨과 동시에 상기 유기막(7)의 표면을 에칭하는 공정에 있어서 그 처리의 드라이에칭은 산소를 이용하여 실행되는 것을 특징으로 하는 반도체장치의 제조방법.
  4. 제3항에 있어서, 상기 유기막(7)을 상기 기판(1)에 설치하는 공정에 있어서, 상기 유기막(7)은 폴리이미드수지로 구성되는 것을 특징으로 하는 반도체장치의 제조방법.
  5. 제3항에 있어서, 상기 접속용전극(4)을 설치하는 공정에 있어서, 상기 접속용전극(4)은 비금속으로 구성되는 것을 특징으로 하는 반도체장치의 제조방법.
  6. 반도체기판(1)의 일면에 접속용전극(4)을 설치하는 공정, 상기 접속용전극(4)의 표면의 적어도 일부를 노출하는 개구부(6)를 갖는 유기막(5)을 상기 기판(1)의 일면에 설치하는 공정, 상기 접속용전극(4)의 표면의 적어도 일부를 노출하는 개구부(8)를 갖는 유기막(7)을 상기 기판(1)의 일면에 설치하는 공정, 상기 접속용전극(4)의 노출된 표면을 에칭하는 공정, 상기 접속용전극(4)에 적층하여 돌기전극(14)을 설치하는 공정, 상기 유기막(7)의 표면을 에칭하는 공정, 으로 구성되는 것을 특징으로 하는 반도체장치의 제조방법.
  7. 제6항에 있어서, 상기 접속용전극(4)의 노출된 표면을 에칭하는 공정에 있어서, 그 처리는 드라이에칭에 의해 실행됨과 동시에 상기 유기막(7)의 표면을 에칭하는 공정에 있어서 그 처리는 드라이에칭에 의해 실행되는 것을 특징으로 하는 반도체장치의 제조방법.
  8. 제7항에 있어서, 상기 접속용전극(4)의 노출된 표면을 에칭하는 공정에 있어서, 그 처리의 드라이에칭은 알곤을 이용하여 실행됨과 동시에 상기 유기막(7)의 표면을 에칭하는 공정에 있어서 그 처리의 드라이에칭은 산소를 이용하여 실행되는 것을 특징으로 하는 반도체장치의 제조방법.
  9. 제8항에 있어서, 상기 유기막(7)을 상기 기판(1)에 설치하는 공정에 있어서, 상기 유기막(7)은 폴리이미드수지로 구성되는 것을 특징으로 하는 반도체장치의 제조방법.
  10. 제8항에 있어서, 상기 접속용전극(4)을 설치하는 공정에 있어서, 상기 접속용전극(4)은 비금속으로 구성되는 것을 특징으로 하는 반도체장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940028918A 1993-11-05 1994-11-04 반도체장치의 제조방법 KR0142136B1 (ko)

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US5705856A (en) 1998-01-06
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US5538920A (en) 1996-07-23
EP0652590A1 (en) 1995-05-10
MY112712A (en) 2001-08-30
DE69415927D1 (de) 1999-02-25
JPH07130750A (ja) 1995-05-19
CN1108806A (zh) 1995-09-20
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