DE69415927D1 - Verfahren zur Herstellung eines Halbleiterbauelements mit einer Höckerelectrode - Google Patents

Verfahren zur Herstellung eines Halbleiterbauelements mit einer Höckerelectrode

Info

Publication number
DE69415927D1
DE69415927D1 DE69415927T DE69415927T DE69415927D1 DE 69415927 D1 DE69415927 D1 DE 69415927D1 DE 69415927 T DE69415927 T DE 69415927T DE 69415927 T DE69415927 T DE 69415927T DE 69415927 D1 DE69415927 D1 DE 69415927D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor component
bump electrode
bump
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69415927T
Other languages
English (en)
Other versions
DE69415927T2 (de
Inventor
Takeshi Wakabayashi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Application granted granted Critical
Publication of DE69415927D1 publication Critical patent/DE69415927D1/de
Publication of DE69415927T2 publication Critical patent/DE69415927T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Wire Bonding (AREA)
DE69415927T 1993-11-05 1994-11-03 Verfahren zur Herstellung eines Halbleiterbauelements mit einer Höckerelectrode Expired - Lifetime DE69415927T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5299057A JP2698827B2 (ja) 1993-11-05 1993-11-05 バンプ電極を備えた半導体装置の製造方法

Publications (2)

Publication Number Publication Date
DE69415927D1 true DE69415927D1 (de) 1999-02-25
DE69415927T2 DE69415927T2 (de) 1999-05-27

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
DE69415927T Expired - Lifetime DE69415927T2 (de) 1993-11-05 1994-11-03 Verfahren zur Herstellung eines Halbleiterbauelements mit einer Höckerelectrode

Country Status (8)

Country Link
US (2) US5538920A (de)
EP (1) EP0652590B1 (de)
JP (1) JP2698827B2 (de)
KR (1) KR0142136B1 (de)
CN (1) CN1042986C (de)
DE (1) DE69415927T2 (de)
MY (1) MY112712A (de)
TW (2) TW368685B (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3383329B2 (ja) * 1992-08-27 2003-03-04 株式会社東芝 半導体装置の製造方法
JP2698827B2 (ja) * 1993-11-05 1998-01-19 カシオ計算機株式会社 バンプ電極を備えた半導体装置の製造方法
JPH1032244A (ja) * 1996-07-16 1998-02-03 Nec Corp 半導体装置及びその製造方法
US5817540A (en) * 1996-09-20 1998-10-06 Micron Technology, Inc. Method of fabricating flip-chip on leads devices and resulting assemblies
EP1048483B1 (de) * 1997-12-22 2007-07-11 Hitachi, Ltd. Kartenförmige vorrichtung mit einem halbleiterelement
US6214716B1 (en) * 1998-09-30 2001-04-10 Micron Technology, Inc. Semiconductor substrate-based BGA interconnection and methods of farication same
US6715663B2 (en) * 2002-01-16 2004-04-06 Intel Corporation Wire-bond process flow for copper metal-six, structures achieved thereby, and testing method
JP2004119430A (ja) * 2002-09-24 2004-04-15 Tadatomo Suga 接合装置および方法
JP3877717B2 (ja) * 2003-09-30 2007-02-07 三洋電機株式会社 半導体装置およびその製造方法
JP2006222232A (ja) * 2005-02-09 2006-08-24 Fujitsu Ltd 半導体装置およびその製造方法
JP2006270031A (ja) * 2005-02-25 2006-10-05 Casio Comput Co Ltd 半導体装置およびその製造方法
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TW368685B (en) 1999-09-01
DE69415927T2 (de) 1999-05-27
US5705856A (en) 1998-01-06
TW368710B (en) 1999-09-01
CN1042986C (zh) 1999-04-14
CN1108806A (zh) 1995-09-20
JPH07130750A (ja) 1995-05-19
JP2698827B2 (ja) 1998-01-19
EP0652590B1 (de) 1999-01-13
KR0142136B1 (ko) 1998-07-15
KR950015677A (ko) 1995-06-17
EP0652590A1 (de) 1995-05-10
US5538920A (en) 1996-07-23
MY112712A (en) 2001-08-30

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