DE69333099D1 - Verfahren zur Herstellung eines Halbleiter-Bauteils mit zylindrischer Elektrode - Google Patents

Verfahren zur Herstellung eines Halbleiter-Bauteils mit zylindrischer Elektrode

Info

Publication number
DE69333099D1
DE69333099D1 DE69333099T DE69333099T DE69333099D1 DE 69333099 D1 DE69333099 D1 DE 69333099D1 DE 69333099 T DE69333099 T DE 69333099T DE 69333099 T DE69333099 T DE 69333099T DE 69333099 D1 DE69333099 D1 DE 69333099D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor component
cylindrical electrode
electrode
cylindrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69333099T
Other languages
English (en)
Inventor
Takanori Saeki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Electronics Corp
Original Assignee
NEC Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Electronics Corp filed Critical NEC Electronics Corp
Application granted granted Critical
Publication of DE69333099D1 publication Critical patent/DE69333099D1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/31—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor
    • H10B12/318—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells having a storage electrode stacked over the transistor the storage electrode having multiple segments
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
DE69333099T 1992-10-30 1993-10-29 Verfahren zur Herstellung eines Halbleiter-Bauteils mit zylindrischer Elektrode Expired - Lifetime DE69333099D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4292831A JP2953220B2 (ja) 1992-10-30 1992-10-30 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE69333099D1 true DE69333099D1 (de) 2003-08-21

Family

ID=17786921

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69333099T Expired - Lifetime DE69333099D1 (de) 1992-10-30 1993-10-29 Verfahren zur Herstellung eines Halbleiter-Bauteils mit zylindrischer Elektrode

Country Status (5)

Country Link
US (1) US5438010A (de)
EP (1) EP0595360B1 (de)
JP (1) JP2953220B2 (de)
KR (1) KR0120917B1 (de)
DE (1) DE69333099D1 (de)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR960006030A (ko) * 1994-07-18 1996-02-23 김주용 반도체소자의 캐패시터 제조방법
US5488011A (en) * 1994-11-08 1996-01-30 Micron Technology, Inc. Method of forming contact areas between vertical conductors
EP1202331A3 (de) * 1995-02-28 2002-07-31 Micron Technology, Inc. Verfahren zur Herstellung einer Struktur durch Wiederablagerung
JP2682509B2 (ja) * 1995-04-28 1997-11-26 日本電気株式会社 半導体装置の製造方法
US5604147A (en) * 1995-05-12 1997-02-18 Micron Technology, Inc. Method of forming a cylindrical container stacked capacitor
KR100238615B1 (ko) * 1996-06-04 2000-01-15 가네꼬 히사시 스택된 캐패시터를 갖는 반도체 기억장치의 제조 방법
US5652165A (en) * 1996-06-10 1997-07-29 Vanguard International Semiconductor Corporation Method of forming a stacked capacitor with a double wall crown shape
TW312037B (en) * 1996-08-07 1997-08-01 United Microelectronics Corp Manufacturing method of capacitor of dynamic random access memory
US5739060A (en) * 1996-08-16 1998-04-14 United Microelecrtronics Corporation Method of fabricating a capacitor structure for a semiconductor memory device
JP3024676B2 (ja) * 1996-08-16 2000-03-21 ユナイテッド マイクロエレクトロニクス コープ ツリー型コンデンサを備えた半導体メモリ素子の製造方法
GB2321771A (en) * 1996-08-16 1998-08-05 United Microelectronics Corp Stacked capacitor
JP2930110B2 (ja) * 1996-11-14 1999-08-03 日本電気株式会社 半導体記憶装置およびその製造方法
KR100244305B1 (ko) * 1997-04-18 2000-02-01 김영환 반도체 메모리장치의 제조방법
US6027860A (en) 1997-08-13 2000-02-22 Micron Technology, Inc. Method for forming a structure using redeposition of etchable layer
KR100275818B1 (ko) * 1997-12-29 2001-01-15 김영환 반도체소자의커패시터제조방법
JP3214449B2 (ja) 1998-06-12 2001-10-02 日本電気株式会社 半導体記憶装置の製造方法
GB2341271B (en) * 1998-09-01 2001-04-18 United Semiconductor Corp Method of fabricating capacitor
KR100346450B1 (ko) * 1999-12-30 2002-07-27 주식회사 하이닉스반도체 반도체소자의 캐패시터 형성방법
KR100466982B1 (ko) * 2002-03-11 2005-01-24 삼성전자주식회사 캐패시터를 갖는 반도체 장치 및 그 제조방법
JP2005057263A (ja) * 2003-07-31 2005-03-03 Samsung Electronics Co Ltd 半導体素子を製造するためのエッチング方法
KR100546381B1 (ko) 2003-09-22 2006-01-26 삼성전자주식회사 습식식각 공정을 포함하는 반도체 소자의 제조방법
JP4908748B2 (ja) * 2003-09-22 2012-04-04 三星電子株式会社 半導体素子を製造するためのエッチング方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5140389A (en) * 1988-01-08 1992-08-18 Hitachi, Ltd. Semiconductor memory device having stacked capacitor cells
JPH0357262A (ja) * 1989-07-26 1991-03-12 Mitsubishi Electric Corp キャパシタ
JPH0379072A (ja) * 1989-08-22 1991-04-04 Toshiba Corp 半導体記憶装置及びその製造方法
JPH0391957A (ja) * 1989-09-04 1991-04-17 Sony Corp メモリ装置の製造方法
DD299990A5 (de) * 1990-02-23 1992-05-14 Dresden Forschzentr Mikroelek Ein-Transistor-Speicherzellenanordnung und Verfahren zu deren Herstellung
JPH04212449A (ja) * 1990-04-02 1992-08-04 Matsushita Electric Ind Co Ltd 半導体メモリ装置及びその製造方法
JPH04264767A (ja) * 1991-02-20 1992-09-21 Fujitsu Ltd 半導体装置及びその製造方法
US5266512A (en) * 1991-10-23 1993-11-30 Motorola, Inc. Method for forming a nested surface capacitor
US5150276A (en) * 1992-01-24 1992-09-22 Micron Technology, Inc. Method of fabricating a vertical parallel cell capacitor having a storage node capacitor plate comprising a center fin effecting electrical communication between itself and parallel annular rings

Also Published As

Publication number Publication date
JPH06151747A (ja) 1994-05-31
EP0595360B1 (de) 2003-07-16
EP0595360A1 (de) 1994-05-04
KR940010342A (ko) 1994-05-26
KR0120917B1 (ko) 1997-10-27
US5438010A (en) 1995-08-01
JP2953220B2 (ja) 1999-09-27

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Legal Events

Date Code Title Description
8332 No legal effect for de