DE69333282D1 - Verfahren zur Herstellung eines Halbleitersubstrats - Google Patents

Verfahren zur Herstellung eines Halbleitersubstrats

Info

Publication number
DE69333282D1
DE69333282D1 DE69333282T DE69333282T DE69333282D1 DE 69333282 D1 DE69333282 D1 DE 69333282D1 DE 69333282 T DE69333282 T DE 69333282T DE 69333282 T DE69333282 T DE 69333282T DE 69333282 D1 DE69333282 D1 DE 69333282D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor substrate
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69333282T
Other languages
English (en)
Other versions
DE69333282T2 (de
Inventor
Takao Yonehara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Canon Inc
Original Assignee
Canon Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Inc filed Critical Canon Inc
Application granted granted Critical
Publication of DE69333282D1 publication Critical patent/DE69333282D1/de
Publication of DE69333282T2 publication Critical patent/DE69333282T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/83894—Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/012—Bonding, e.g. electrostatic for strain gauges
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
DE69333282T 1992-08-25 1993-08-24 Verfahren zur Herstellung eines Halbleitersubstrats Expired - Fee Related DE69333282T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP24717392A JP3192000B2 (ja) 1992-08-25 1992-08-25 半導体基板及びその作製方法
JP24717392 1992-08-25

Publications (2)

Publication Number Publication Date
DE69333282D1 true DE69333282D1 (de) 2003-12-11
DE69333282T2 DE69333282T2 (de) 2004-08-26

Family

ID=17159530

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69333282T Expired - Fee Related DE69333282T2 (de) 1992-08-25 1993-08-24 Verfahren zur Herstellung eines Halbleitersubstrats

Country Status (4)

Country Link
US (1) US5755914A (de)
EP (1) EP0584778B1 (de)
JP (1) JP3192000B2 (de)
DE (1) DE69333282T2 (de)

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US6146979A (en) 1997-05-12 2000-11-14 Silicon Genesis Corporation Pressurized microbubble thin film separation process using a reusable substrate
US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
US6291313B1 (en) 1997-05-12 2001-09-18 Silicon Genesis Corporation Method and device for controlled cleaving process
US6033974A (en) * 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
US6054369A (en) * 1997-06-30 2000-04-25 Intersil Corporation Lifetime control for semiconductor devices
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
FR2766620B1 (fr) * 1997-07-22 2000-12-01 Commissariat Energie Atomique Realisation de microstructures ou de nanostructures sur un support
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US6224668B1 (en) * 1998-06-02 2001-05-01 Shin-Etsu Handotai Co., Ltd. Method for producing SOI substrate and SOI substrate
US6291326B1 (en) 1998-06-23 2001-09-18 Silicon Genesis Corporation Pre-semiconductor process implant and post-process film separation
US6423614B1 (en) * 1998-06-30 2002-07-23 Intel Corporation Method of delaminating a thin film using non-thermal techniques
US6534381B2 (en) * 1999-01-08 2003-03-18 Silicon Genesis Corporation Method for fabricating multi-layered substrates
TW502458B (en) * 1999-06-09 2002-09-11 Toshiba Corp Bonding type semiconductor substrate, semiconductor light emission element and manufacturing method thereof
US6403447B1 (en) 1999-07-07 2002-06-11 Elantec Semiconductor, Inc. Reduced substrate capacitance high performance SOI process
EP1212787B1 (de) * 1999-08-10 2014-10-08 Silicon Genesis Corporation Spaltprozess für die herstellung mehrlagiger substrate mit geringer implantationsdosis
US6221740B1 (en) 1999-08-10 2001-04-24 Silicon Genesis Corporation Substrate cleaving tool and method
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
US6500694B1 (en) 2000-03-22 2002-12-31 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6984571B1 (en) 1999-10-01 2006-01-10 Ziptronix, Inc. Three dimensional device integration method and integrated device
US6544862B1 (en) 2000-01-14 2003-04-08 Silicon Genesis Corporation Particle distribution method and resulting structure for a layer transfer process
US6902987B1 (en) 2000-02-16 2005-06-07 Ziptronix, Inc. Method for low temperature bonding and bonded structure
US6563133B1 (en) * 2000-08-09 2003-05-13 Ziptronix, Inc. Method of epitaxial-like wafer bonding at low temperature and bonded structure
KR20020060457A (ko) * 2001-01-11 2002-07-18 송오성 에스오아이 기판의 제조방법
DE10107405A1 (de) * 2001-02-14 2002-09-12 Rainer Schork Direktprozessierbare Halbleiterfolie
US8187377B2 (en) 2002-10-04 2012-05-29 Silicon Genesis Corporation Non-contact etch annealing of strained layers
RU2217842C1 (ru) * 2003-01-14 2003-11-27 Институт физики полупроводников - Объединенного института физики полупроводников СО РАН Способ изготовления структуры кремний-на-изоляторе
US7399681B2 (en) * 2003-02-18 2008-07-15 Corning Incorporated Glass-based SOI structures
US7176528B2 (en) * 2003-02-18 2007-02-13 Corning Incorporated Glass-based SOI structures
US7622363B2 (en) * 2003-05-06 2009-11-24 Canon Kabushiki Kaisha Semiconductor substrate, semiconductor device, light emitting diode and producing method therefor
JP2004335642A (ja) * 2003-05-06 2004-11-25 Canon Inc 基板およびその製造方法
US7109092B2 (en) 2003-05-19 2006-09-19 Ziptronix, Inc. Method of room temperature covalent bonding
JP4730645B2 (ja) * 2004-02-13 2011-07-20 株式会社Ｓｕｍｃｏ Ｓｏｉウェーハの製造方法
JP4771510B2 (ja) * 2004-06-23 2011-09-14 キヤノン株式会社 半導体層の製造方法及び基板の製造方法
JP4950047B2 (ja) * 2004-07-22 2012-06-13 ボード オブ トラスティーズ オブ ザ レランド スタンフォード ジュニア ユニバーシティ ゲルマニウムの成長方法及び半導体基板の製造方法
FR2890489B1 (fr) * 2005-09-08 2008-03-07 Soitec Silicon On Insulator Procede de fabrication d'une heterostructure de type semi-conducteur sur isolant
FR2895391B1 (fr) * 2005-12-27 2008-01-25 Commissariat Energie Atomique Procede d'elaboration de nanostructures ordonnees
US20080012087A1 (en) * 2006-04-19 2008-01-17 Henri Dautet Bonded wafer avalanche photodiode and method for manufacturing same
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US7811900B2 (en) * 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
JP5171016B2 (ja) 2006-10-27 2013-03-27 キヤノン株式会社 半導体部材、半導体物品の製造方法、その製造方法を用いたｌｅｄアレイ
CN101210377B (zh) * 2006-12-30 2011-02-02 海尔集团公司 干衣机滚筒的前支撑装置
JP2009094144A (ja) * 2007-10-04 2009-04-30 Canon Inc 発光素子の製造方法
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
EP3442006A3 (de) 2011-01-25 2019-02-20 EV Group E. Thallner GmbH Verfahren zum permanenten bonden von wafern
JP2014516470A (ja) 2011-04-08 2014-07-10 エーファウ・グループ・エー・タルナー・ゲーエムベーハー ウェハを恒久的にボンディングするための方法
SG2014009930A (en) * 2012-07-24 2014-05-29 Ev Group E Thallner Gmbh Method and device for permanent bonding of wafers
KR101972728B1 (ko) 2017-03-31 2019-04-25 엔지케이 인슐레이터 엘티디 접합체 및 탄성파 소자

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JPS6051700A (ja) * 1983-08-31 1985-03-23 Toshiba Corp シリコン結晶体の接合方法
NL8501773A (nl) * 1985-06-20 1987-01-16 Philips Nv Werkwijze voor het vervaardigen van halfgeleiderinrichtingen.
JPH0715942B2 (ja) * 1986-08-25 1995-02-22 日本電気株式会社 集積回路基板の製造方法
US4774196A (en) * 1987-08-25 1988-09-27 Siliconix Incorporated Method of bonding semiconductor wafers
JPH01230255A (ja) * 1988-03-10 1989-09-13 Sony Corp 半導体基板の製造方法
JP2762462B2 (ja) * 1988-05-31 1998-06-04 ソニー株式会社 半導体基板の製造方法
DE3829906A1 (de) * 1988-09-02 1990-03-15 Siemens Ag Verfahren zum herstellen von halbleiter-bauelementen
US4939101A (en) * 1988-09-06 1990-07-03 General Electric Company Method of making direct bonded wafers having a void free interface
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JPH0719839B2 (ja) * 1989-10-18 1995-03-06 株式会社東芝 半導体基板の製造方法
JP3112106B2 (ja) * 1991-10-11 2000-11-27 キヤノン株式会社 半導体基材の作製方法
JP3191371B2 (ja) * 1991-12-11 2001-07-23 ソニー株式会社 半導体ウェハの張り合せ方法
JP2602597B2 (ja) * 1991-12-27 1997-04-23 信越半導体株式会社 薄膜ｓｏｉ基板の製造方法
US5427638A (en) * 1992-06-04 1995-06-27 Alliedsignal Inc. Low temperature reaction bonding
US5407506A (en) * 1992-06-04 1995-04-18 Alliedsignal Inc. Reaction bonding through activation by ion bombardment

Also Published As

Publication number Publication date
DE69333282T2 (de) 2004-08-26
EP0584778A3 (en) 1997-10-08
EP0584778A2 (de) 1994-03-02
JPH0677101A (ja) 1994-03-18
JP3192000B2 (ja) 2001-07-23
US5755914A (en) 1998-05-26
EP0584778B1 (de) 2003-11-05

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee