DE69528611D1 - Verfahren zur Herstellung eines Halbleitersubstrates - Google Patents
Verfahren zur Herstellung eines HalbleitersubstratesInfo
- Publication number
- DE69528611D1 DE69528611D1 DE69528611T DE69528611T DE69528611D1 DE 69528611 D1 DE69528611 D1 DE 69528611D1 DE 69528611 T DE69528611 T DE 69528611T DE 69528611 T DE69528611 T DE 69528611T DE 69528611 D1 DE69528611 D1 DE 69528611D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor substrate
- semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136277—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon
- G02F1/136281—Active matrix addressed cells formed on a semiconductor substrate, e.g. of silicon having a transmissive semiconductor substrate
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/012—Bonding, e.g. electrostatic for strain gauges
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP07039694A JP3542376B2 (ja) | 1994-04-08 | 1994-04-08 | 半導体基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69528611D1 true DE69528611D1 (de) | 2002-11-28 |
DE69528611T2 DE69528611T2 (de) | 2003-06-26 |
Family
ID=13430255
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69528611T Expired - Fee Related DE69528611T2 (de) | 1994-04-08 | 1995-04-04 | Verfahren zur Herstellung eines Halbleitersubstrates |
Country Status (4)
Country | Link |
---|---|
US (1) | US5773355A (de) |
EP (1) | EP0676796B1 (de) |
JP (1) | JP3542376B2 (de) |
DE (1) | DE69528611T2 (de) |
Families Citing this family (43)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0706203A1 (de) * | 1994-09-14 | 1996-04-10 | Nippon Telegraph And Telephone Corporation | Verfahren zur Herstellung eines SOI-Substrates |
EP0759634A1 (de) * | 1995-08-17 | 1997-02-26 | Shin-Etsu Handotai Company Limited | SOI-Scheibe und Verfahren zu ihrer Herstellung |
JPH09331049A (ja) * | 1996-04-08 | 1997-12-22 | Canon Inc | 貼り合わせsoi基板の作製方法及びsoi基板 |
US6287900B1 (en) * | 1996-08-13 | 2001-09-11 | Semiconductor Energy Laboratory Co., Ltd | Semiconductor device with catalyst addition and removal |
SG65697A1 (en) * | 1996-11-15 | 1999-06-22 | Canon Kk | Process for producing semiconductor article |
JPH10275905A (ja) * | 1997-03-31 | 1998-10-13 | Mitsubishi Electric Corp | シリコンウェーハの製造方法およびシリコンウェーハ |
US6027956A (en) * | 1998-02-05 | 2000-02-22 | Integration Associates, Inc. | Process for producing planar dielectrically isolated high speed pin photodiode |
US6458619B1 (en) | 1998-02-05 | 2002-10-01 | Integration Associates, Inc. | Process for producing an isolated planar high speed pin photodiode with improved capacitance |
US6303967B1 (en) | 1998-02-05 | 2001-10-16 | Integration Associates, Inc. | Process for producing an isolated planar high speed pin photodiode |
US6548878B1 (en) | 1998-02-05 | 2003-04-15 | Integration Associates, Inc. | Method for producing a thin distributed photodiode structure |
US6753586B1 (en) | 1998-03-09 | 2004-06-22 | Integration Associates Inc. | Distributed photodiode structure having majority dopant gradient and method for making same |
US6344838B1 (en) * | 1998-04-06 | 2002-02-05 | Em Microelectronic-Marlin Sa | Control device for a liquid crystal display cell |
JP3635200B2 (ja) | 1998-06-04 | 2005-04-06 | 信越半導体株式会社 | Soiウェーハの製造方法 |
JP3385972B2 (ja) | 1998-07-10 | 2003-03-10 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法および貼り合わせウェーハ |
TW444266B (en) | 1998-07-23 | 2001-07-01 | Canon Kk | Semiconductor substrate and method of producing same |
US6346978B1 (en) * | 1999-07-13 | 2002-02-12 | Sharp Laboratories Of America, Inc. | SOI TFT array substrate for LCD projection display |
US6690078B1 (en) | 1999-08-05 | 2004-02-10 | Integration Associates, Inc. | Shielded planar dielectrically isolated high speed pin photodiode and method for producing same |
JP2002110949A (ja) | 2000-09-28 | 2002-04-12 | Canon Inc | Soiの熱処理方法及び製造方法 |
US6660606B2 (en) | 2000-09-29 | 2003-12-09 | Canon Kabushiki Kaisha | Semiconductor-on-insulator annealing method |
JP2002110688A (ja) | 2000-09-29 | 2002-04-12 | Canon Inc | Soiの熱処理方法及び製造方法 |
US6498073B2 (en) * | 2001-01-02 | 2002-12-24 | Honeywell International Inc. | Back illuminated imager with enhanced UV to near IR sensitivity |
GB2375887A (en) * | 2001-02-23 | 2002-11-27 | Fuji Electric Co Ltd | MEMS device with reduced stiction |
JP4653374B2 (ja) * | 2001-08-23 | 2011-03-16 | セイコーエプソン株式会社 | 電気光学装置の製造方法 |
KR100425582B1 (ko) * | 2001-11-22 | 2004-04-06 | 한국전자통신연구원 | 얕은 소오스/드레인 접합 영역을 갖는 모스 트랜지스터의제조방법 |
US20030134486A1 (en) * | 2002-01-16 | 2003-07-17 | Zhongze Wang | Semiconductor-on-insulator comprising integrated circuitry |
US6743662B2 (en) * | 2002-07-01 | 2004-06-01 | Honeywell International, Inc. | Silicon-on-insulator wafer for RF integrated circuit |
JP4518886B2 (ja) * | 2004-09-09 | 2010-08-04 | シャープ株式会社 | 半導体素子の製造方法 |
US7244659B2 (en) * | 2005-03-10 | 2007-07-17 | Micron Technology, Inc. | Integrated circuits and methods of forming a field effect transistor |
JP2007059704A (ja) * | 2005-08-25 | 2007-03-08 | Sumco Corp | 貼合せ基板の製造方法及び貼合せ基板 |
JP2008004821A (ja) * | 2006-06-23 | 2008-01-10 | Sumco Corp | 貼り合わせウェーハの製造方法 |
US7557002B2 (en) * | 2006-08-18 | 2009-07-07 | Micron Technology, Inc. | Methods of forming transistor devices |
WO2008050176A1 (en) * | 2006-10-27 | 2008-05-02 | S.O.I.Tec Silicon On Insulator Technologies | Improved process for transfer of a thin layer formed in a substrate with vacancy clusters |
US7989322B2 (en) * | 2007-02-07 | 2011-08-02 | Micron Technology, Inc. | Methods of forming transistors |
JP5433927B2 (ja) * | 2007-03-14 | 2014-03-05 | 株式会社Sumco | 貼り合わせウェーハの製造方法 |
JP5220335B2 (ja) * | 2007-04-11 | 2013-06-26 | 信越化学工業株式会社 | Soi基板の製造方法 |
KR20100076223A (ko) * | 2008-12-26 | 2010-07-06 | 주식회사 동부하이텍 | 피모스 트랜지스터 및 이를 제조하는 방법 |
US7985658B2 (en) * | 2009-06-08 | 2011-07-26 | Aptina Imaging Corporation | Method of forming substrate for use in imager devices |
EP2282332B1 (de) * | 2009-08-04 | 2012-06-27 | S.O.I. TEC Silicon | Herstellungsverfahren eines Halbleitersubstrat |
US10224233B2 (en) | 2014-11-18 | 2019-03-05 | Globalwafers Co., Ltd. | High resistivity silicon-on-insulator substrate comprising a charge trapping layer formed by He-N2 co-implantation |
EP3739620B1 (de) * | 2015-06-01 | 2022-02-16 | GlobalWafers Co., Ltd. | Silicium-germanium-auf-isolator-struktur |
US10529616B2 (en) | 2015-11-20 | 2020-01-07 | Globalwafers Co., Ltd. | Manufacturing method of smoothing a semiconductor surface |
CN112262467B (zh) | 2018-06-08 | 2024-08-09 | 环球晶圆股份有限公司 | 将硅薄层移转的方法 |
US20230154761A1 (en) * | 2020-05-26 | 2023-05-18 | Shin-Etsu Handotai Co., Ltd. | Method for manufacturing soi wafer |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2596605B2 (ja) * | 1988-05-20 | 1997-04-02 | 日本電信電話株式会社 | Soi基板の製造方法 |
US4939101A (en) * | 1988-09-06 | 1990-07-03 | General Electric Company | Method of making direct bonded wafers having a void free interface |
US5362667A (en) * | 1992-07-28 | 1994-11-08 | Harris Corporation | Bonded wafer processing |
US5098861A (en) * | 1991-01-08 | 1992-03-24 | Unitrode Corporation | Method of processing a semiconductor substrate including silicide bonding |
JP3237888B2 (ja) * | 1992-01-31 | 2001-12-10 | キヤノン株式会社 | 半導体基体及びその作製方法 |
US5213986A (en) * | 1992-04-10 | 1993-05-25 | North American Philips Corporation | Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning |
US5234535A (en) * | 1992-12-10 | 1993-08-10 | International Business Machines Corporation | Method of producing a thin silicon-on-insulator layer |
US5455193A (en) * | 1994-11-17 | 1995-10-03 | Philips Electronics North America Corporation | Method of forming a silicon-on-insulator (SOI) material having a high degree of thickness uniformity |
-
1994
- 1994-04-08 JP JP07039694A patent/JP3542376B2/ja not_active Expired - Fee Related
-
1995
- 1995-04-04 EP EP95302253A patent/EP0676796B1/de not_active Expired - Lifetime
- 1995-04-04 DE DE69528611T patent/DE69528611T2/de not_active Expired - Fee Related
-
1997
- 1997-05-29 US US08/864,904 patent/US5773355A/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0676796A3 (de) | 1996-03-06 |
US5773355A (en) | 1998-06-30 |
EP0676796A2 (de) | 1995-10-11 |
DE69528611T2 (de) | 2003-06-26 |
JP3542376B2 (ja) | 2004-07-14 |
EP0676796B1 (de) | 2002-10-23 |
JPH07283380A (ja) | 1995-10-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |