JP5220335B2 - Soi基板の製造方法 - Google Patents
Soi基板の製造方法 Download PDFInfo
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- JP5220335B2 JP5220335B2 JP2007103579A JP2007103579A JP5220335B2 JP 5220335 B2 JP5220335 B2 JP 5220335B2 JP 2007103579 A JP2007103579 A JP 2007103579A JP 2007103579 A JP2007103579 A JP 2007103579A JP 5220335 B2 JP5220335 B2 JP 5220335B2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76256—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques using silicon etch back techniques, e.g. BESOI, ELTRAN
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
Description
11 高濃度ボロン添加p層
12 ボロン添加p層
20 石英基板
Claims (6)
- 最表面に深さLの高濃度ボロン添加p層を有するシリコン基板と絶縁性基板の表面同士を貼り合わせる工程Aと、少なくとも化学的エッチングの工程を含む薄板化手法により前記貼り合わせ後のシリコン基板を裏面から薄板化して該シリコン基板の厚みをL以下とする工程Bと、前記L以下の厚みのシリコン層に水素含有雰囲気中で熱処理を施す工程Cとを備え、
前記高濃度ボロン添加p層のシリコン基板最表面からの深さLは3μm以上10μm以下であり、該高濃度ボロン添加p層の比抵抗は0.01Ωcm以下である、
ことを特徴とするSOI基板の製造方法。 - 前記化学的エッチングに用いられるエッチャントは、KOH、NaOH、CsOH、NH4OH、EDP(Ethylenediamine-pyrocatechol)、またはTMAH(Tetramethyl ammonium hydroxide)を含有するアルカリ溶液である請求項1に記載のSOI基板の製造方法。
- 前記水素含有雰囲気中での熱処理温度が700℃乃至1250℃である請求項1又は2に記載のSOI基板の製造方法。
- 前記工程Aは、前記絶縁性基板と前記シリコン基板の少なくとも一方の表面に活性化処理を施す表面処理工程と、前記絶縁性基板と前記シリコン基板の表面同士を室温で接合する工程とを備えている請求項1乃至3の何れか1項に記載のSOI基板の製造方法。
- 前記活性化処理がプラズマ処理又はオゾン処理の少なくとも一方である請求項4に記載のSOI基板の製造方法。
- 前記絶縁性基板は、石英、サファイア、ホウ珪酸ガラス、結晶化ガラス、または炭化珪素の何れかである請求項1乃至5の何れか1項に記載のSOI基板の製造方法。
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007103579A JP5220335B2 (ja) | 2007-04-11 | 2007-04-11 | Soi基板の製造方法 |
US12/076,923 US7615456B2 (en) | 2007-04-11 | 2008-03-25 | Method for manufacturing SOI substrate |
EP08006093.2A EP1981079B1 (en) | 2007-04-11 | 2008-03-28 | Method for manufacturing an SOI substrate |
CN2008100886676A CN101286442B (zh) | 2007-04-11 | 2008-04-10 | Soi基板的制造方法 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2007103579A JP5220335B2 (ja) | 2007-04-11 | 2007-04-11 | Soi基板の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2008263009A JP2008263009A (ja) | 2008-10-30 |
JP5220335B2 true JP5220335B2 (ja) | 2013-06-26 |
Family
ID=39658042
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2007103579A Active JP5220335B2 (ja) | 2007-04-11 | 2007-04-11 | Soi基板の製造方法 |
Country Status (4)
Country | Link |
---|---|
US (1) | US7615456B2 (ja) |
EP (1) | EP1981079B1 (ja) |
JP (1) | JP5220335B2 (ja) |
CN (1) | CN101286442B (ja) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5496598B2 (ja) * | 2008-10-31 | 2014-05-21 | 信越化学工業株式会社 | シリコン薄膜転写絶縁性ウェーハの製造方法 |
EP2282332B1 (en) * | 2009-08-04 | 2012-06-27 | S.O.I. TEC Silicon | Method for fabricating a semiconductor substrate |
KR101569567B1 (ko) | 2010-05-04 | 2015-11-16 | 이 아이 듀폰 디 네모아 앤드 캄파니 | 납-텔루륨-붕소-산화물을 함유하는 후막 페이스트, 및 반도체 소자의 제조에서의 그의 용도 |
JP5585319B2 (ja) * | 2010-09-03 | 2014-09-10 | 信越半導体株式会社 | 貼り合わせsoiウェーハの製造方法 |
US8440544B2 (en) | 2010-10-06 | 2013-05-14 | International Business Machines Corporation | CMOS structure and method of manufacture |
CN104022018A (zh) * | 2014-06-19 | 2014-09-03 | 无锡宏纳科技有限公司 | 一种干法刻蚀等离子损伤修复工艺 |
JP6834932B2 (ja) * | 2017-12-19 | 2021-02-24 | 株式会社Sumco | 貼り合わせウェーハ用の支持基板の製造方法および貼り合わせウェーハの製造方法 |
Family Cites Families (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2735079B2 (ja) * | 1989-03-30 | 1998-04-02 | 信越半導体 株式会社 | ホウ素ドーピング方法 |
FR2681472B1 (fr) | 1991-09-18 | 1993-10-29 | Commissariat Energie Atomique | Procede de fabrication de films minces de materiau semiconducteur. |
JP3237888B2 (ja) * | 1992-01-31 | 2001-12-10 | キヤノン株式会社 | 半導体基体及びその作製方法 |
US5213986A (en) | 1992-04-10 | 1993-05-25 | North American Philips Corporation | Process for making thin film silicon-on-insulator wafers employing wafer bonding and wafer thinning |
JPH06338604A (ja) * | 1993-05-31 | 1994-12-06 | Toshiba Corp | 半導体基板の製造方法 |
FR2715501B1 (fr) * | 1994-01-26 | 1996-04-05 | Commissariat Energie Atomique | Procédé de dépôt de lames semiconductrices sur un support. |
JP3257580B2 (ja) * | 1994-03-10 | 2002-02-18 | キヤノン株式会社 | 半導体基板の作製方法 |
JP3542376B2 (ja) | 1994-04-08 | 2004-07-14 | キヤノン株式会社 | 半導体基板の製造方法 |
JPH08139297A (ja) * | 1994-09-14 | 1996-05-31 | Nippon Telegr & Teleph Corp <Ntt> | Soi基板の製造方法 |
EP0706203A1 (en) | 1994-09-14 | 1996-04-10 | Nippon Telegraph And Telephone Corporation | Method of manufacturing SOI substrate |
US5985728A (en) | 1995-09-01 | 1999-11-16 | Elantec Semiconductor, Inc. | Silicon on insulator process with recovery of a device layer from an etch stop layer |
US6582999B2 (en) * | 1997-05-12 | 2003-06-24 | Silicon Genesis Corporation | Controlled cleavage process using pressurized fluid |
EP0926709A3 (en) * | 1997-12-26 | 2000-08-30 | Canon Kabushiki Kaisha | Method of manufacturing an SOI structure |
US6263941B1 (en) | 1999-08-10 | 2001-07-24 | Silicon Genesis Corporation | Nozzle for cleaving substrates |
US6818529B2 (en) * | 2002-09-12 | 2004-11-16 | Applied Materials, Inc. | Apparatus and method for forming a silicon film across the surface of a glass substrate |
JP4730581B2 (ja) * | 2004-06-17 | 2011-07-20 | 信越半導体株式会社 | 貼り合わせウェーハの製造方法 |
JP2006080314A (ja) | 2004-09-09 | 2006-03-23 | Canon Inc | 結合基板の製造方法 |
JP2006210899A (ja) * | 2004-12-28 | 2006-08-10 | Shin Etsu Chem Co Ltd | Soiウエーハの製造方法及びsoiウェーハ |
JP2007073878A (ja) * | 2005-09-09 | 2007-03-22 | Shin Etsu Chem Co Ltd | Soiウエーハおよびsoiウエーハの製造方法 |
-
2007
- 2007-04-11 JP JP2007103579A patent/JP5220335B2/ja active Active
-
2008
- 2008-03-25 US US12/076,923 patent/US7615456B2/en active Active
- 2008-03-28 EP EP08006093.2A patent/EP1981079B1/en active Active
- 2008-04-10 CN CN2008100886676A patent/CN101286442B/zh not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
EP1981079A2 (en) | 2008-10-15 |
CN101286442B (zh) | 2012-01-04 |
EP1981079B1 (en) | 2018-05-02 |
CN101286442A (zh) | 2008-10-15 |
US20080254597A1 (en) | 2008-10-16 |
EP1981079A3 (en) | 2009-09-23 |
JP2008263009A (ja) | 2008-10-30 |
US7615456B2 (en) | 2009-11-10 |
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