DE69231777D1 - Verfahren zur Herstellung eines Halbleitersubstrats - Google Patents
Verfahren zur Herstellung eines HalbleitersubstratsInfo
- Publication number
- DE69231777D1 DE69231777D1 DE69231777T DE69231777T DE69231777D1 DE 69231777 D1 DE69231777 D1 DE 69231777D1 DE 69231777 T DE69231777 T DE 69231777T DE 69231777 T DE69231777 T DE 69231777T DE 69231777 D1 DE69231777 D1 DE 69231777D1
- Authority
- DE
- Germany
- Prior art keywords
- manufacturing
- semiconductor substrate
- semiconductor
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02002—Preparing wafers
- H01L21/02005—Preparing bulk and homogeneous wafers
- H01L21/0203—Making porous regions on the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
- H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
- H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/116—Oxidation, differential
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S438/00—Semiconductor device manufacturing: process
- Y10S438/928—Front and rear surface processing
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Element Separation (AREA)
- Recrystallisation Techniques (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP00325391A JP3176072B2 (ja) | 1991-01-16 | 1991-01-16 | 半導体基板の形成方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69231777D1 true DE69231777D1 (de) | 2001-05-17 |
DE69231777T2 DE69231777T2 (de) | 2001-08-23 |
Family
ID=11552303
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69231777T Expired - Fee Related DE69231777T2 (de) | 1991-01-16 | 1992-01-15 | Verfahren zur Herstellung eines Halbleitersubstrats |
Country Status (5)
Country | Link |
---|---|
US (1) | US5258322A (de) |
EP (1) | EP0501119B1 (de) |
JP (1) | JP3176072B2 (de) |
CA (1) | CA2059368C (de) |
DE (1) | DE69231777T2 (de) |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6171512B1 (en) | 1991-02-15 | 2001-01-09 | Canon Kabushiki Kaisha | Etching solution for etching porous silicon, etching method using the etching solution and method of preparing semiconductor member using the etching solution |
JP3092761B2 (ja) * | 1991-12-02 | 2000-09-25 | キヤノン株式会社 | 画像表示装置及びその製造方法 |
JP3416163B2 (ja) * | 1992-01-31 | 2003-06-16 | キヤノン株式会社 | 半導体基板及びその作製方法 |
JPH05217824A (ja) * | 1992-01-31 | 1993-08-27 | Canon Inc | 半導体ウエハ及びその製造方法 |
US5331180A (en) * | 1992-04-30 | 1994-07-19 | Fujitsu Limited | Porous semiconductor light emitting device |
JPH06244389A (ja) * | 1992-12-25 | 1994-09-02 | Canon Inc | 半導体基板の作製方法及び該方法により作製された半導体基板 |
JP2907125B2 (ja) * | 1996-06-11 | 1999-06-21 | 日本電気株式会社 | 裏面照射型固体撮像素子の製造方法 |
CA2231625C (en) * | 1997-03-17 | 2002-04-02 | Canon Kabushiki Kaisha | Semiconductor substrate having compound semiconductor layer, process for its production, and electronic device fabricated on semiconductor substrate |
JPH11195775A (ja) | 1997-12-26 | 1999-07-21 | Sony Corp | 半導体基板および薄膜半導体素子およびそれらの製造方法ならびに陽極化成装置 |
DE19802131B4 (de) * | 1998-01-21 | 2007-03-15 | Robert Bosch Gmbh | Verfahren zur Herstellung einer monokristallinen Schicht aus einem leitenden oder halbleitenden Material |
US6372601B1 (en) * | 1998-09-03 | 2002-04-16 | Micron Technology, Inc. | Isolation region forming methods |
US6284671B1 (en) * | 1998-11-19 | 2001-09-04 | National Research Council Of Canada | Selective electrochemical process for creating semiconductor nano-and micro-patterns |
EP1244139A2 (de) * | 2001-03-23 | 2002-09-25 | Matsushita Electric Industrial Co., Ltd. | Verfahren zur Herstellung eines Halbleiterfilms |
DE10143936A1 (de) | 2001-09-07 | 2003-01-09 | Infineon Technologies Ag | Verfahren zur Bildung eines SOI-Substrats, vertikaler Transistor und Speicherzelle mit vertikalem Transistor |
JP4554180B2 (ja) * | 2003-09-17 | 2010-09-29 | ソニー株式会社 | 薄膜半導体デバイスの製造方法 |
US7767541B2 (en) * | 2005-10-26 | 2010-08-03 | International Business Machines Corporation | Methods for forming germanium-on-insulator semiconductor structures using a porous layer and semiconductor structures formed by these methods |
US20080000521A1 (en) * | 2006-05-15 | 2008-01-03 | Siva Sivoththaman | Low-temperature doping processes for silicon wafer devices |
US20170092725A1 (en) * | 2015-09-29 | 2017-03-30 | International Business Machines Corporation | Activated thin silicon layers |
KR102436491B1 (ko) * | 2018-06-27 | 2022-08-25 | 이예순 | 호차 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS584818B2 (ja) * | 1977-04-30 | 1983-01-27 | 松下電器産業株式会社 | 半導体基体の製造方法 |
JPS592185B2 (ja) * | 1980-02-04 | 1984-01-17 | 日本電信電話株式会社 | 半導体基体内への絶縁領域の形成法 |
JPS5825245A (ja) * | 1981-07-23 | 1983-02-15 | Clarion Co Ltd | 半導体集積回路およびその製法 |
JPS59144149A (ja) * | 1983-02-08 | 1984-08-18 | Toko Inc | 誘電体分離基板の製造方法 |
US5098850A (en) * | 1989-06-16 | 1992-03-24 | Canon Kabushiki Kaisha | Process for producing substrate for selective crystal growth, selective crystal growth process and process for producing solar battery by use of them |
JP3253099B2 (ja) * | 1990-03-27 | 2002-02-04 | キヤノン株式会社 | 半導体基板の作製方法 |
-
1991
- 1991-01-16 JP JP00325391A patent/JP3176072B2/ja not_active Expired - Fee Related
-
1992
- 1992-01-14 US US07/820,371 patent/US5258322A/en not_active Expired - Fee Related
- 1992-01-15 DE DE69231777T patent/DE69231777T2/de not_active Expired - Fee Related
- 1992-01-15 EP EP92100607A patent/EP0501119B1/de not_active Expired - Lifetime
- 1992-01-15 CA CA002059368A patent/CA2059368C/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
CA2059368A1 (en) | 1992-07-17 |
JPH04241414A (ja) | 1992-08-28 |
DE69231777T2 (de) | 2001-08-23 |
JP3176072B2 (ja) | 2001-06-11 |
EP0501119B1 (de) | 2001-04-11 |
CA2059368C (en) | 1998-07-28 |
EP0501119A2 (de) | 1992-09-02 |
EP0501119A3 (de) | 1995-03-01 |
US5258322A (en) | 1993-11-02 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |