DE69305939D1 - Verfahren zur Herstellung eines keramischen Schaltungssubstrates - Google Patents

Verfahren zur Herstellung eines keramischen Schaltungssubstrates

Info

Publication number
DE69305939D1
DE69305939D1 DE69305939T DE69305939T DE69305939D1 DE 69305939 D1 DE69305939 D1 DE 69305939D1 DE 69305939 T DE69305939 T DE 69305939T DE 69305939 T DE69305939 T DE 69305939T DE 69305939 D1 DE69305939 D1 DE 69305939D1
Authority
DE
Germany
Prior art keywords
manufacturing
circuit substrate
ceramic circuit
ceramic
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE69305939T
Other languages
English (en)
Other versions
DE69305939T2 (de
Inventor
Junzo Fukuta
Masashi Fukaya
Hideaki Araki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Sumitomo Metal Ceramics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4245697A external-priority patent/JP2732171B2/ja
Priority claimed from JP4298095A external-priority patent/JP2817890B2/ja
Application filed by Sumitomo Metal Ceramics Inc filed Critical Sumitomo Metal Ceramics Inc
Publication of DE69305939D1 publication Critical patent/DE69305939D1/de
Application granted granted Critical
Publication of DE69305939T2 publication Critical patent/DE69305939T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4867—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/486—Via connections through the substrate with or without pins
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49158—Manufacturing circuit on or in base with molding of insulated base

Landscapes

  • Engineering & Computer Science (AREA)
  • Ceramic Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE69305939T 1992-08-21 1993-08-19 Verfahren zur Herstellung eines keramischen Schaltungssubstrates Expired - Lifetime DE69305939T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4245697A JP2732171B2 (ja) 1992-08-21 1992-08-21 セラミックス回路基板の製造方法
JP4298095A JP2817890B2 (ja) 1992-10-09 1992-10-09 セラミックス多層基板及びその製造方法

Publications (2)

Publication Number Publication Date
DE69305939D1 true DE69305939D1 (de) 1996-12-19
DE69305939T2 DE69305939T2 (de) 1997-09-18

Family

ID=26537363

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69305939T Expired - Lifetime DE69305939T2 (de) 1992-08-21 1993-08-19 Verfahren zur Herstellung eines keramischen Schaltungssubstrates

Country Status (3)

Country Link
US (1) US5456778A (de)
EP (1) EP0584726B1 (de)
DE (1) DE69305939T2 (de)

Families Citing this family (35)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5662755A (en) * 1993-10-15 1997-09-02 Matsushita Electric Industrial Co., Ltd. Method of making multi-layered ceramic substrates
JP3483012B2 (ja) * 1994-07-01 2004-01-06 新光電気工業株式会社 セラミック基板製造用焼結体、セラミック基板およびその製造方法
WO1996031102A1 (en) * 1995-03-30 1996-10-03 Ceraprint Arrangement for the manufacture of multilayers
US6709749B1 (en) 1995-06-06 2004-03-23 Lamina Ceramics, Inc. Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate
WO1996039298A1 (en) * 1995-06-06 1996-12-12 Sarnoff Corporation Method for the reduction of lateral shrinkage in multilayer circuit boards on a support
US6042667A (en) * 1996-03-13 2000-03-28 Sumotomo Metal Electronics Devices, Inc. Method of fabricating ceramic multilayer substrate
JP3780386B2 (ja) * 1996-03-28 2006-05-31 株式会社村田製作所 セラミック回路基板及びその製造方法
US5858145A (en) * 1996-10-15 1999-01-12 Sarnoff Corporation Method to control cavity dimensions of fired multilayer circuit boards on a support
JP3451868B2 (ja) * 1997-01-17 2003-09-29 株式会社デンソー セラミック積層基板の製造方法
US6241838B1 (en) * 1997-09-08 2001-06-05 Murata Manufacturing Co., Ltd. Method of producing a multi-layer ceramic substrate
US5933121A (en) 1998-04-07 1999-08-03 Harris Corporation Antenna array for sensing signals on conductors
DE69936329T2 (de) * 1998-04-24 2007-10-04 Matsushita Electric Industrial Co., Ltd., Kadoma Verfahren zur herstellung eines keramischen mehrschichtigen substrats
US6228196B1 (en) * 1998-06-05 2001-05-08 Murata Manufacturing Co., Ltd. Method of producing a multi-layer ceramic substrate
JP3771099B2 (ja) * 1999-01-27 2006-04-26 松下電器産業株式会社 グリーンシート及びその製造方法、多層配線基板の製造方法、両面配線基板の製造方法
JP3656484B2 (ja) * 1999-03-03 2005-06-08 株式会社村田製作所 セラミック多層基板の製造方法
JP3687484B2 (ja) * 1999-06-16 2005-08-24 株式会社村田製作所 セラミック基板の製造方法および未焼成セラミック基板
JP3646587B2 (ja) * 1999-10-27 2005-05-11 株式会社村田製作所 多層セラミック基板およびその製造方法
JP3554962B2 (ja) * 1999-10-28 2004-08-18 株式会社村田製作所 複合積層体およびその製造方法
JP2002084065A (ja) * 2000-09-07 2002-03-22 Murata Mfg Co Ltd 多層セラミック基板およびその製造方法ならびに電子装置
JP3591437B2 (ja) * 2000-09-07 2004-11-17 株式会社村田製作所 多層セラミック基板およびその製造方法ならびに電子装置
JP3807257B2 (ja) * 2001-06-25 2006-08-09 松下電器産業株式会社 セラミック部品の製造方法
GB2420909A (en) * 2003-08-21 2006-06-07 C Mac Microcircuits Ltd Method for ltcc zero x-y shrinkage
US7261841B2 (en) * 2003-11-19 2007-08-28 E. I. Du Pont De Nemours And Company Thick film conductor case compositions for LTCC tape
US7378049B2 (en) * 2003-12-08 2008-05-27 Matsushita Electric Industrial Co., Ltd. Method for producing ceramic substrate and electronic component module using ceramic substrate
US20050194085A1 (en) * 2004-03-02 2005-09-08 Matsushita Electric Industrial Co., Ltd. Method for producing ceramic multilayer substrate
US7652213B2 (en) * 2004-04-06 2010-01-26 Murata Manufacturing Co., Ltd. Internal conductor connection structure and multilayer substrate
US7279217B2 (en) * 2004-05-24 2007-10-09 Tdk Corporation Multilayer ceramic device, method for manufacturing the same, and ceramic device
US7731812B2 (en) * 2004-10-19 2010-06-08 E.I. Du Pont De Nemours And Company Thick film conductor case compositions for LTCC tape
US7136021B2 (en) * 2005-01-13 2006-11-14 Cirex Technology Corporation Ceramic chip antenna
US20080176103A1 (en) * 2005-03-28 2008-07-24 Ngk Insulators, Ltd. Conductive Paste and Electronic Parts
US7749592B2 (en) * 2007-02-06 2010-07-06 Tdk Corpoation Multilayer ceramic substrate
CN101543151B (zh) * 2007-04-20 2011-04-13 株式会社村田制作所 多层陶瓷基板及其制造方法以及电子器件
US9006028B2 (en) * 2008-09-12 2015-04-14 Ananda H. Kumar Methods for forming ceramic substrates with via studs
TWI382724B (zh) * 2008-11-11 2013-01-11 Chunghwa Telecom Co Ltd 用戶端設備自動供裝系統與方法
WO2019082714A1 (ja) * 2017-10-26 2019-05-02 株式会社村田製作所 多層基板、インターポーザおよび電子機器

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3953562A (en) * 1974-07-15 1976-04-27 International Business Machines Corporation Process for the elimination of dimensional changes in ceramic green sheets
JPS6014494A (ja) * 1983-07-04 1985-01-25 株式会社日立製作所 セラミツク多層配線基板およびその製造方法
JPS61155243A (ja) * 1984-12-28 1986-07-14 富士通株式会社 グリ−ンシ−ト組成物
US4795512A (en) * 1986-02-26 1989-01-03 Matsushita Electric Industrial Co., Ltd. Method of manufacturing a multilayer ceramic body
US4879156A (en) * 1986-05-02 1989-11-07 International Business Machines Corporation Multilayered ceramic substrate having solid non-porous metal conductors
US4753694A (en) * 1986-05-02 1988-06-28 International Business Machines Corporation Process for forming multilayered ceramic substrate having solid metal conductors
US5130067A (en) * 1986-05-02 1992-07-14 International Business Machines Corporation Method and means for co-sintering ceramic/metal mlc substrates
JPH01138792A (ja) * 1987-11-25 1989-05-31 Narumi China Corp セラミック多層回路基板
JPH0738493B2 (ja) * 1989-04-18 1995-04-26 株式会社住友金属セラミックス 同時焼成セラミック回路基板
US5162240A (en) * 1989-06-16 1992-11-10 Hitachi, Ltd. Method and apparatus of fabricating electric circuit pattern on thick and thin film hybrid multilayer wiring substrate
JP3087899B2 (ja) * 1989-06-16 2000-09-11 株式会社日立製作所 厚膜薄膜混成多層配線基板の製造方法
US5290375A (en) * 1989-08-05 1994-03-01 Nippondenso Co., Ltd. Process for manufacturing ceramic multilayer substrate
US5085720A (en) * 1990-01-18 1992-02-04 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of green ceramic bodies
DE69112119T2 (de) * 1990-05-09 1996-02-01 Matsushita Electric Ind Co Ltd Verbundplatte und Herstellungsverfahren von einer keramischen Leiterplatte unter Verwendung ersterer.
DE4113483C2 (de) * 1990-05-12 1995-10-26 Du Pont Deutschland Verfahren zur Erzeugung feiner Leiterbahnen auf einem keramischen Träger
KR100200902B1 (ko) * 1990-09-19 1999-06-15 가나이 쓰도무 다층세라믹 소결체 및 그 제조방법
JP2961859B2 (ja) * 1990-10-01 1999-10-12 松下電器産業株式会社 多層セラミック基板
US5254191A (en) * 1990-10-04 1993-10-19 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of ceramic bodies
JPH0746540B2 (ja) * 1991-07-24 1995-05-17 住友金属鉱山株式会社 ガラスセラミック基板の製造方法
EP0535711A3 (en) * 1991-10-04 1993-12-01 Matsushita Electric Ind Co Ltd Method for producing multilayered ceramic substrate

Also Published As

Publication number Publication date
EP0584726B1 (de) 1996-11-13
US5456778A (en) 1995-10-10
DE69305939T2 (de) 1997-09-18
EP0584726A1 (de) 1994-03-02

Similar Documents

Publication Publication Date Title
DE69305939D1 (de) Verfahren zur Herstellung eines keramischen Schaltungssubstrates
DE69333152D1 (de) Verfahren zur Herstellung eines Halbleitersubstrates
DE69331815D1 (de) Verfahren zur Herstellung eines Halbleitersubstrates
DE69331816D1 (de) Verfahren zur Herstellung eines Halbleitersubstrats
DE69228349D1 (de) Verfahren zur Herstellung eines Halbleitersubstrats
DE69528611D1 (de) Verfahren zur Herstellung eines Halbleitersubstrates
DE69631233D1 (de) Verfahren zur Herstellung eines Halbleitersubstrats
DE69309358D1 (de) Verfahren zur Herstellung eines Schaltungssubstrats
DE69332511D1 (de) Verfahren zur Herstellung eines Halbleitersubstrats
DE69333282D1 (de) Verfahren zur Herstellung eines Halbleitersubstrats
DE69427176D1 (de) Verfahren zur Herstellung einer Halbleiter-Kondensator-Elektrode
DE69317800D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69032773D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69330980D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69518548D1 (de) Verfahren zur Herstellung eines keramischen Substrates
DE69232432D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69231803D1 (de) Verfahren zur Herstellung einer Halbleiteranordnung
DE69130346D1 (de) Verfahren zur Herstellung von Halbleiteranordnungen
DE68929150D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69216752D1 (de) Verfahren zur Herstellung einer Halbleiter-Scheibe
DE69421592D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung
DE69233801D1 (de) Verfahren zur Herstellung eines Schaltungssubstrates mit einem montierten Halbleiterelement
DE69328390D1 (de) Verfahren zur Herstellung eines mehrlagigen Substrats
DE69306600D1 (de) Verfahren zur Herstellung eines mehrschichtigen Leitersubstrats
DE69323979D1 (de) Verfahren zur Herstellung einer Halbleitervorrichtung

Legal Events

Date Code Title Description
8327 Change in the person/name/address of the patent owner

Owner name: SUMITOMO METAL (SMI) ELECTRONICS DEVICES INC., MIN

8364 No opposition during term of opposition
8328 Change in the person/name/address of the agent

Representative=s name: KRAMER - BARSKE - SCHMIDTCHEN, 81245 MUENCHEN

8327 Change in the person/name/address of the patent owner

Owner name: MURATA MANUFACTURING CO., LTD., NAGAOKAKYO, KYOTO,