DE69328390D1 - Verfahren zur Herstellung eines mehrlagigen Substrats - Google Patents

Verfahren zur Herstellung eines mehrlagigen Substrats

Info

Publication number
DE69328390D1
DE69328390D1 DE69328390T DE69328390T DE69328390D1 DE 69328390 D1 DE69328390 D1 DE 69328390D1 DE 69328390 T DE69328390 T DE 69328390T DE 69328390 T DE69328390 T DE 69328390T DE 69328390 D1 DE69328390 D1 DE 69328390D1
Authority
DE
Germany
Prior art keywords
production
multilayer substrate
multilayer
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69328390T
Other languages
English (en)
Other versions
DE69328390T2 (de
Inventor
Yasuhiko Hakotani
Seiichi Nakatani
Tsuneharu Katada
Satoru Yuhaku
Kazuhiro Miura
Yoshifumi Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP4127159A external-priority patent/JP2855959B2/ja
Priority claimed from JP14463592A external-priority patent/JPH05343851A/ja
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Application granted granted Critical
Publication of DE69328390D1 publication Critical patent/DE69328390D1/de
Publication of DE69328390T2 publication Critical patent/DE69328390T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49822Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814Conductive parts
    • H01L21/4846Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857Multilayer substrates
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H01L23/49883Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials the conductive materials containing organic materials or pastes, e.g. for thick films
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/095Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
    • H01L2924/097Glass-ceramics, e.g. devitrified glass
    • H01L2924/09701Low temperature co-fired ceramic [LTCC]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/301Electrical effects
    • H01L2924/3011Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
DE69328390T 1992-05-20 1993-05-14 Verfahren zur Herstellung eines mehrlagigen Substrats Expired - Fee Related DE69328390T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP4127159A JP2855959B2 (ja) 1992-05-20 1992-05-20 多層セラミック基板の製造方法
JP14463592A JPH05343851A (ja) 1992-06-04 1992-06-04 多層セラミック基板の製造方法

Publications (2)

Publication Number Publication Date
DE69328390D1 true DE69328390D1 (de) 2000-05-25
DE69328390T2 DE69328390T2 (de) 2000-12-07

Family

ID=26463171

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69328390T Expired - Fee Related DE69328390T2 (de) 1992-05-20 1993-05-14 Verfahren zur Herstellung eines mehrlagigen Substrats

Country Status (3)

Country Link
US (1) US5370759A (de)
EP (1) EP0570855B1 (de)
DE (1) DE69328390T2 (de)

Families Citing this family (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5534290A (en) * 1990-04-03 1996-07-09 Visatech Corporation Surround print process for the manufacture of electrode embedded dielectric green sheets
US5561828A (en) * 1993-09-14 1996-10-01 Matsushita Electric Industrial Co., Ltd. Method of manufacturing a ceramic electronic part
JPH07302858A (ja) * 1994-04-28 1995-11-14 Toshiba Corp 半導体パッケージ
WO1996039298A1 (en) * 1995-06-06 1996-12-12 Sarnoff Corporation Method for the reduction of lateral shrinkage in multilayer circuit boards on a support
US6709749B1 (en) 1995-06-06 2004-03-23 Lamina Ceramics, Inc. Method for the reduction of lateral shrinkage in multilayer circuit boards on a substrate
US6042667A (en) * 1996-03-13 2000-03-28 Sumotomo Metal Electronics Devices, Inc. Method of fabricating ceramic multilayer substrate
JP3780386B2 (ja) * 1996-03-28 2006-05-31 株式会社村田製作所 セラミック回路基板及びその製造方法
US5858145A (en) * 1996-10-15 1999-01-12 Sarnoff Corporation Method to control cavity dimensions of fired multilayer circuit boards on a support
US6241838B1 (en) * 1997-09-08 2001-06-05 Murata Manufacturing Co., Ltd. Method of producing a multi-layer ceramic substrate
DE69936329T2 (de) * 1998-04-24 2007-10-04 Matsushita Electric Industrial Co., Ltd., Kadoma Verfahren zur herstellung eines keramischen mehrschichtigen substrats
US6228196B1 (en) * 1998-06-05 2001-05-08 Murata Manufacturing Co., Ltd. Method of producing a multi-layer ceramic substrate
US6447712B1 (en) * 1998-12-28 2002-09-10 University Of Washington Method for sintering ceramic tapes
JP3771099B2 (ja) * 1999-01-27 2006-04-26 松下電器産業株式会社 グリーンシート及びその製造方法、多層配線基板の製造方法、両面配線基板の製造方法
JP3656484B2 (ja) * 1999-03-03 2005-06-08 株式会社村田製作所 セラミック多層基板の製造方法
JP2000299561A (ja) * 1999-04-15 2000-10-24 Matsushita Electric Ind Co Ltd セラミック多層基板の製造方法
JP3687484B2 (ja) * 1999-06-16 2005-08-24 株式会社村田製作所 セラミック基板の製造方法および未焼成セラミック基板
JP3646587B2 (ja) * 1999-10-27 2005-05-11 株式会社村田製作所 多層セラミック基板およびその製造方法
JP3554962B2 (ja) * 1999-10-28 2004-08-18 株式会社村田製作所 複合積層体およびその製造方法
JP3633435B2 (ja) 2000-04-10 2005-03-30 株式会社村田製作所 多層セラミック基板、その製造方法および設計方法、ならびに電子装置
JP3591437B2 (ja) * 2000-09-07 2004-11-17 株式会社村田製作所 多層セラミック基板およびその製造方法ならびに電子装置
JP2002084065A (ja) * 2000-09-07 2002-03-22 Murata Mfg Co Ltd 多層セラミック基板およびその製造方法ならびに電子装置
JP3807257B2 (ja) * 2001-06-25 2006-08-09 松下電器産業株式会社 セラミック部品の製造方法
JP2003110238A (ja) * 2001-09-28 2003-04-11 Murata Mfg Co Ltd ガラスセラミック多層基板の製造方法
ATE364584T1 (de) * 2001-10-01 2007-07-15 Heraeus Inc Ungesintertes niedertemperaturglaskeramikband für elektronische mikrobauteile, verfahren zur herstellung und verwendung
JP4270792B2 (ja) * 2002-01-23 2009-06-03 富士通株式会社 導電性材料及びビアホールの充填方法
TW587067B (en) * 2002-03-07 2004-05-11 Yageo Corp Method for reducing shrinkage during sintering low-temperature ceramic and constrain layer
US7381283B2 (en) * 2002-03-07 2008-06-03 Yageo Corporation Method for reducing shrinkage during sintering low-temperature-cofired ceramics
US6835260B2 (en) * 2002-10-04 2004-12-28 International Business Machines Corporation Method to produce pedestal features in constrained sintered substrates
DE102004043273A1 (de) * 2003-09-09 2005-05-04 Ngk Spark Plug Co Verfahren zur Herstellung eines Keramiksubstrats und Keramiksubstrat
US7378049B2 (en) * 2003-12-08 2008-05-27 Matsushita Electric Industrial Co., Ltd. Method for producing ceramic substrate and electronic component module using ceramic substrate
US20050225012A1 (en) * 2004-04-13 2005-10-13 Alex Cooper Method of producing abrasive tools
US20070060970A1 (en) * 2005-09-15 2007-03-15 Burdon Jeremy W Miniaturized co-fired electrical interconnects for implantable medical devices
DE102006000935B4 (de) * 2006-01-05 2016-03-10 Epcos Ag Monolithisches keramisches Bauelement und Verfahren zur Herstellung
KR20090066862A (ko) * 2007-12-20 2009-06-24 삼성전기주식회사 다층 세라믹 기판의 제조 방법
US8105456B2 (en) * 2009-02-10 2012-01-31 Keng-Hsien Lin Method of making a breathable film laminate and a breathable film laminate produced therefrom
WO2010122822A1 (ja) * 2009-04-21 2010-10-28 株式会社村田製作所 多層セラミック基板の製造方法
US9205571B2 (en) 2012-04-18 2015-12-08 Nitto Denko Corporation Method and apparatus for sintering flat ceramics
US9206086B2 (en) 2012-04-18 2015-12-08 Nitto Denko Corporation Method and apparatus for sintering flat ceramics
US11950378B2 (en) * 2021-08-13 2024-04-02 Harbor Electronics, Inc. Via bond attachment

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3879509A (en) * 1971-09-07 1975-04-22 Gilbert James Elderbaum Method of producing thin ceramic sheets with minimal distortion
JPS60254697A (ja) * 1984-05-31 1985-12-16 富士通株式会社 多層セラミック回路基板および製法
JPS6116749A (ja) * 1984-07-03 1986-01-24 松井 孝嘉 脳室腹腔短絡器具
US4714570A (en) * 1984-07-17 1987-12-22 Matsushita Electric Industrial Co., Ltd. Conductor paste and method of manufacturing a multilayered ceramic body using the paste
JPS625848A (ja) * 1985-07-02 1987-01-12 松下電器産業株式会社 セラミツク多層基板の製造方法
US4753694A (en) * 1986-05-02 1988-06-28 International Business Machines Corporation Process for forming multilayered ceramic substrate having solid metal conductors
US5130067A (en) * 1986-05-02 1992-07-14 International Business Machines Corporation Method and means for co-sintering ceramic/metal mlc substrates
US4879156A (en) * 1986-05-02 1989-11-07 International Business Machines Corporation Multilayered ceramic substrate having solid non-porous metal conductors
JPH0728128B2 (ja) * 1988-03-11 1995-03-29 松下電器産業株式会社 セラミック多層配線基板とその製造方法
US5085720A (en) * 1990-01-18 1992-02-04 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of green ceramic bodies
US5254191A (en) * 1990-10-04 1993-10-19 E. I. Du Pont De Nemours And Company Method for reducing shrinkage during firing of ceramic bodies

Also Published As

Publication number Publication date
EP0570855A2 (de) 1993-11-24
US5370759A (en) 1994-12-06
EP0570855A3 (en) 1995-11-08
DE69328390T2 (de) 2000-12-07
EP0570855B1 (de) 2000-04-19

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP

8320 Willingness to grant licences declared (paragraph 23)
8339 Ceased/non-payment of the annual fee