DE69218069D1 - Verfahren zur Herstellung eines planarisierten Halbleiterbauelementes - Google Patents
Verfahren zur Herstellung eines planarisierten HalbleiterbauelementesInfo
- Publication number
- DE69218069D1 DE69218069D1 DE69218069T DE69218069T DE69218069D1 DE 69218069 D1 DE69218069 D1 DE 69218069D1 DE 69218069 T DE69218069 T DE 69218069T DE 69218069 T DE69218069 T DE 69218069T DE 69218069 D1 DE69218069 D1 DE 69218069D1
- Authority
- DE
- Germany
- Prior art keywords
- production
- semiconductor component
- planarized semiconductor
- planarized
- component
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76819—Smoothing of the dielectric
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/31051—Planarisation of the insulating layers
- H01L21/31053—Planarisation of the insulating layers involving a dielectric removal step
- H01L21/31055—Planarisation of the insulating layers involving a dielectric removal step the removal being a chemical etching step, e.g. dry etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- General Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP3212536A JP2913918B2 (ja) | 1991-08-26 | 1991-08-26 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69218069D1 true DE69218069D1 (de) | 1997-04-17 |
DE69218069T2 DE69218069T2 (de) | 1997-06-26 |
Family
ID=16624301
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE69218069T Expired - Fee Related DE69218069T2 (de) | 1991-08-26 | 1992-08-20 | Verfahren zur Herstellung eines planarisierten Halbleiterbauelementes |
Country Status (4)
Country | Link |
---|---|
US (1) | US5316980A (de) |
EP (1) | EP0529954B1 (de) |
JP (1) | JP2913918B2 (de) |
DE (1) | DE69218069T2 (de) |
Families Citing this family (20)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05243402A (ja) * | 1992-03-03 | 1993-09-21 | Nec Corp | 半導体装置の製造方法 |
US5461010A (en) * | 1994-06-13 | 1995-10-24 | Industrial Technology Research Institute | Two step etch back spin-on-glass process for semiconductor planarization |
US6297110B1 (en) | 1994-07-29 | 2001-10-02 | Stmicroelectronics, Inc. | Method of forming a contact in an integrated circuit |
US5567658A (en) * | 1994-09-01 | 1996-10-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for minimizing peeling at the surface of spin-on glasses |
KR0172539B1 (ko) * | 1995-05-22 | 1999-03-30 | 김주용 | 반도체 소자의 에스.오.지막 형성방법 |
US5814186A (en) * | 1995-08-28 | 1998-09-29 | Advanced Micro Devices, Inc. | SOG etchant gas and method for using same |
US5679211A (en) * | 1995-09-18 | 1997-10-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Spin-on-glass etchback planarization process using an oxygen plasma to remove an etchback polymer residue |
US5821163A (en) * | 1996-02-13 | 1998-10-13 | Vlsi Technology, Inc. | Method for achieving accurate SOG etchback selectivity |
US5792705A (en) * | 1996-06-28 | 1998-08-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Optimized planarization process for SOG filled vias |
US6051502A (en) * | 1997-10-20 | 2000-04-18 | Micron Technology, Inc. | Methods of forming conductive components and methods of forming conductive lines |
US6391786B1 (en) * | 1997-12-31 | 2002-05-21 | Lam Research Corporation | Etching process for organic anti-reflective coating |
TW398053B (en) * | 1998-07-31 | 2000-07-11 | United Microelectronics Corp | Manufacturing of shallow trench isolation |
US6080676A (en) * | 1998-09-17 | 2000-06-27 | Advanced Micro Devices, Inc. | Device and method for etching spacers formed upon an integrated circuit gate conductor |
US6281132B1 (en) | 1998-10-06 | 2001-08-28 | Advanced Micro Devices, Inc. | Device and method for etching nitride spacers formed upon an integrated circuit gate conductor |
JP2009016375A (ja) * | 2007-06-29 | 2009-01-22 | Oki Electric Ind Co Ltd | 半導体装置の製造方法及び装置 |
US9330910B2 (en) | 2010-11-01 | 2016-05-03 | The Board Of Trustees Of The University Of Illinois | Method of forming an array of nanostructures |
CN102543838B (zh) * | 2010-12-22 | 2014-01-29 | 中国科学院微电子研究所 | 半导体器件的制造方法 |
CN102569062B (zh) * | 2010-12-22 | 2015-06-03 | 中国科学院微电子研究所 | Sog层和光抗蚀剂层的反应离子刻蚀方法 |
CN102543839B (zh) | 2010-12-22 | 2014-01-08 | 中国科学院微电子研究所 | 层间电介质层的平面化方法 |
CN102903621B (zh) | 2011-07-29 | 2016-02-17 | 中国科学院微电子研究所 | 半导体器件的制造方法 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4511430A (en) * | 1984-01-30 | 1985-04-16 | International Business Machines Corporation | Control of etch rate ratio of SiO2 /photoresist for quartz planarization etch back process |
US4654113A (en) * | 1984-02-10 | 1987-03-31 | Fujitsu Limited | Process for fabricating a semiconductor device |
US4676868A (en) * | 1986-04-23 | 1987-06-30 | Fairchild Semiconductor Corporation | Method for planarizing semiconductor substrates |
US4676867A (en) * | 1986-06-06 | 1987-06-30 | Rockwell International Corporation | Planarization process for double metal MOS using spin-on glass as a sacrificial layer |
FR2627902B1 (fr) * | 1988-02-26 | 1990-06-22 | Philips Nv | Procede pour aplanir la surface d'un dispositif semiconducteur |
JPH03177022A (ja) * | 1989-12-06 | 1991-08-01 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
JPH04245628A (ja) * | 1991-01-31 | 1992-09-02 | Hitachi Ltd | 絶縁膜の形成方法 |
JPH04370934A (ja) * | 1991-06-20 | 1992-12-24 | Fujitsu Ltd | 半導体装置の製造方法 |
-
1991
- 1991-08-26 JP JP3212536A patent/JP2913918B2/ja not_active Expired - Fee Related
-
1992
- 1992-08-11 US US07/929,161 patent/US5316980A/en not_active Expired - Lifetime
- 1992-08-20 EP EP92307624A patent/EP0529954B1/de not_active Expired - Lifetime
- 1992-08-20 DE DE69218069T patent/DE69218069T2/de not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JP2913918B2 (ja) | 1999-06-28 |
DE69218069T2 (de) | 1997-06-26 |
EP0529954A1 (de) | 1993-03-03 |
JPH0555181A (ja) | 1993-03-05 |
EP0529954B1 (de) | 1997-03-12 |
US5316980A (en) | 1994-05-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8327 | Change in the person/name/address of the patent owner |
Owner name: NEC ELECTRONICS CORP., KAWASAKI, KANAGAWA, JP |
|
8339 | Ceased/non-payment of the annual fee |