DE69112119T2 - Verbundplatte und Herstellungsverfahren von einer keramischen Leiterplatte unter Verwendung ersterer. - Google Patents

Verbundplatte und Herstellungsverfahren von einer keramischen Leiterplatte unter Verwendung ersterer.

Info

Publication number
DE69112119T2
DE69112119T2 DE1991612119 DE69112119T DE69112119T2 DE 69112119 T2 DE69112119 T2 DE 69112119T2 DE 1991612119 DE1991612119 DE 1991612119 DE 69112119 T DE69112119 T DE 69112119T DE 69112119 T2 DE69112119 T2 DE 69112119T2
Authority
DE
Germany
Prior art keywords
former
manufacturing
ceramic circuit
circuit board
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE1991612119
Other languages
English (en)
Other versions
DE69112119D1 (de
Inventor
Yasuyuki Baba
Jun Shigemi
Shigetoshi Segawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP2119430A external-priority patent/JP2789782B2/ja
Priority claimed from JP32362590A external-priority patent/JP3074728B2/ja
Priority claimed from JP33244290A external-priority patent/JP2754914B2/ja
Priority claimed from JP4951591A external-priority patent/JP3003241B2/ja
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Publication of DE69112119D1 publication Critical patent/DE69112119D1/de
Application granted granted Critical
Publication of DE69112119T2 publication Critical patent/DE69112119T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H05K3/4629—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials laminating inorganic sheets comprising printed circuits, e.g. green ceramic sheets
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038—Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4053—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques
    • H05K3/4061—Through-connections; Vertical interconnect access [VIA] connections by thick-film techniques for via connections in inorganic insulating substrates
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H05K1/092—Dispersed materials, e.g. conductive pastes or inks
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/01—Tools for processing; Objects used during processing
    • H05K2203/0191—Using tape or non-metallic foil in a process, e.g. during filling of a hole with conductive paste
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0029—Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
DE1991612119 1990-05-09 1991-05-08 Verbundplatte und Herstellungsverfahren von einer keramischen Leiterplatte unter Verwendung ersterer. Expired - Lifetime DE69112119T2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
JP2119430A JP2789782B2 (ja) 1990-05-09 1990-05-09 セラミック配線基板の製造方法
JP32362590A JP3074728B2 (ja) 1990-11-26 1990-11-26 セラミック配線基板の製造方法
JP33244290A JP2754914B2 (ja) 1990-11-28 1990-11-28 セラミック配線基板の製造方法
JP4951591A JP3003241B2 (ja) 1991-03-14 1991-03-14 グリーンシートとプラスチックフィルムの複合体

Publications (2)

Publication Number Publication Date
DE69112119D1 DE69112119D1 (de) 1995-09-21
DE69112119T2 true DE69112119T2 (de) 1996-02-01

Family

ID=27462367

Family Applications (1)

Application Number Title Priority Date Filing Date
DE1991612119 Expired - Lifetime DE69112119T2 (de) 1990-05-09 1991-05-08 Verbundplatte und Herstellungsverfahren von einer keramischen Leiterplatte unter Verwendung ersterer.

Country Status (2)

Country Link
EP (1) EP0456243B1 (de)
DE (1) DE69112119T2 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04296086A (ja) * 1991-01-18 1992-10-20 Du Pont Japan Ltd セラミック多層基板用グリーンシートと、その製造方　法、および該グリーンシートを用いたセラミック多層基板の製造方法
CA2093407C (en) * 1992-04-06 1997-12-09 Jun Inasaka Method for fabricating a ceramic multi-layer substrate
US5456778A (en) * 1992-08-21 1995-10-10 Sumitomo Metal Ceramics Inc. Method of fabricating ceramic circuit substrate
US5948200A (en) * 1996-07-26 1999-09-07 Taiyo Yuden Co., Ltd. Method of manufacturing laminated ceramic electronic parts
DE19742072B4 (de) * 1997-09-24 2005-11-24 Robert Bosch Gmbh Verfahren zur Herstellung druckdichter Durchkontaktierungen
DE102009031983A1 (de) 2009-07-06 2011-01-13 Lti Drives Gmbh An eine Vakuumpumpe anschließbare elektrische Verbindungseinheit
CN104540320B (zh) * 2014-12-09 2018-02-02 江门崇达电路技术有限公司 一种pcb中树脂塞孔的制作方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3899554A (en) * 1973-12-14 1975-08-12 Ibm Process for forming a ceramic substrate

Also Published As

Publication number Publication date
EP0456243A3 (en) 1992-04-15
DE69112119D1 (de) 1995-09-21
EP0456243B1 (de) 1995-08-16
EP0456243A2 (de) 1991-11-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PANASONIC CORP., KADOMA, OSAKA, JP