DE3855861D1 - Verfahren zur Herstellung eines Halbleiterbauelementes mit einer isolierten Gitterstruktur - Google Patents
Verfahren zur Herstellung eines Halbleiterbauelementes mit einer isolierten GitterstrukturInfo
- Publication number
- DE3855861D1 DE3855861D1 DE3855861T DE3855861T DE3855861D1 DE 3855861 D1 DE3855861 D1 DE 3855861D1 DE 3855861 T DE3855861 T DE 3855861T DE 3855861 T DE3855861 T DE 3855861T DE 3855861 D1 DE3855861 D1 DE 3855861D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor component
- lattice structure
- isolated
- isolated lattice
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000004065 semiconductor Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
- H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
- H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
- H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
- H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
- H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
- H01L29/41725—Source or drain electrodes for field effect devices
- H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
- H01L29/7836—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with a significant overlap between the lightly doped extension and the gate electrode
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
- Y10S257/90—MOSFET type gate sidewall insulating spacer
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- High Energy & Nuclear Physics (AREA)
- Chemical & Material Sciences (AREA)
- Inorganic Chemistry (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US07/104,187 US4786609A (en) | 1987-10-05 | 1987-10-05 | Method of fabricating field-effect transistor utilizing improved gate sidewall spacers |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3855861D1 true DE3855861D1 (de) | 1997-05-15 |
DE3855861T2 DE3855861T2 (de) | 1997-10-23 |
Family
ID=22299114
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE3855861T Expired - Lifetime DE3855861T2 (de) | 1987-10-05 | 1988-09-28 | Verfahren zur Herstellung eines Halbleiterbauelementes mit einer isolierten Gitterstruktur |
Country Status (5)
Country | Link |
---|---|
US (1) | US4786609A (de) |
EP (1) | EP0315229B1 (de) |
JP (1) | JPH081957B2 (de) |
KR (1) | KR0136881B1 (de) |
DE (1) | DE3855861T2 (de) |
Families Citing this family (52)
Publication number | Priority date | Publication date | Assignee | Title |
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US5114530A (en) * | 1985-10-31 | 1992-05-19 | Texas Instruments Incorporated | Interlevel dielectric process |
US5028555A (en) * | 1987-12-02 | 1991-07-02 | Advanced Micro Devices, Inc. | Self-aligned semiconductor devices |
US5073595A (en) * | 1987-12-23 | 1991-12-17 | Minnesota Mining And Manufacturing Company | Epoxide resin compositions and method |
NL8800222A (nl) * | 1988-01-29 | 1989-08-16 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting waarbij op zelfregistrerende wijze metaalsilicide wordt aangebracht. |
US5030582A (en) * | 1988-10-14 | 1991-07-09 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a CMOS semiconductor device |
US5273914A (en) * | 1988-10-14 | 1993-12-28 | Matsushita Electric Industrial Co., Ltd. | Method of fabricating a CMOS semiconductor devices |
US5006477A (en) * | 1988-11-25 | 1991-04-09 | Hughes Aircraft Company | Method of making a latch up free, high voltage, CMOS bulk process for sub-half micron devices |
DE69029046T2 (de) * | 1989-03-16 | 1997-03-06 | Sgs Thomson Microelectronics | Kontakte für Halbleiter-Vorrichtungen |
JPH088318B2 (ja) * | 1990-05-09 | 1996-01-29 | 株式会社東芝 | 不揮発性半導体メモリ装置の製造方法 |
JPH0448640A (ja) * | 1990-06-14 | 1992-02-18 | Oki Electric Ind Co Ltd | Mosトランジスタの製造方法 |
US5045486A (en) * | 1990-06-26 | 1991-09-03 | At&T Bell Laboratories | Transistor fabrication method |
US5217912A (en) * | 1990-07-03 | 1993-06-08 | Sharp Kabushiki Kaisha | Method for manufacturing a semiconductor device |
JPH07118522B2 (ja) * | 1990-10-24 | 1995-12-18 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 基板表面を酸化処理するための方法及び半導体の構造 |
TW203148B (de) * | 1991-03-27 | 1993-04-01 | American Telephone & Telegraph | |
US5057450A (en) * | 1991-04-01 | 1991-10-15 | International Business Machines Corporation | Method for fabricating silicon-on-insulator structures |
JPH0582541A (ja) * | 1991-08-22 | 1993-04-02 | Rohm Co Ltd | 半導体装置の製造方法 |
JPH0582542A (ja) * | 1991-08-22 | 1993-04-02 | Rohm Co Ltd | 半導体装置の製造方法 |
US5348900A (en) * | 1991-10-11 | 1994-09-20 | Sharp Kabushiki Kaisha | Process for manufacturing a semiconductor device including heat treatment in ammonia or oxygen |
EP0540276B1 (de) * | 1991-10-31 | 1997-09-24 | STMicroelectronics, Inc. | Herstellungsverfahren eines selbstjustierenden Kontakts |
US5384287A (en) * | 1991-12-13 | 1995-01-24 | Nec Corporation | Method of forming a semiconductor device having self-aligned contact holes |
EP0549055A3 (en) * | 1991-12-23 | 1996-10-23 | Koninkl Philips Electronics Nv | Method of manufacturing a semiconductor device provided with a field effect transistor, and such a semiconductor device |
US5225357A (en) * | 1992-01-02 | 1993-07-06 | Chartered Semiconductor Manufacturing | Low P+ contact resistance formation by double implant |
US5256563A (en) * | 1992-04-16 | 1993-10-26 | Texas Instruments Incorporated | Doped well structure and method for semiconductor technologies |
JPH0697192A (ja) * | 1992-07-29 | 1994-04-08 | Kawasaki Steel Corp | 半導体装置及びその製造方法 |
US5439847A (en) * | 1993-11-05 | 1995-08-08 | At&T Corp. | Integrated circuit fabrication with a raised feature as mask |
US5439831A (en) * | 1994-03-09 | 1995-08-08 | Siemens Aktiengesellschaft | Low junction leakage MOSFETs |
JPH07249766A (ja) * | 1994-03-10 | 1995-09-26 | Fujitsu Ltd | 半導体装置及びその製造方法 |
US5488579A (en) * | 1994-04-29 | 1996-01-30 | Motorola Inc. | Three-dimensionally integrated nonvolatile SRAM cell and process |
US5482888A (en) * | 1994-08-12 | 1996-01-09 | United Microelectronics Corporation | Method of manufacturing a low resistance, high breakdown voltage, power MOSFET |
JP2720796B2 (ja) * | 1994-11-15 | 1998-03-04 | 日本電気株式会社 | 半導体装置の製造方法 |
US5679598A (en) * | 1994-12-30 | 1997-10-21 | Lsi Logic Corporation | Method of making a CMOS dynamic random-access memory (DRAM) |
US5858844A (en) * | 1995-06-07 | 1999-01-12 | Advanced Micro Devices, Inc. | Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process |
US5563096A (en) * | 1995-11-20 | 1996-10-08 | Digital Equipment Corporation | Semiconductor device fabrication with planar gate interconnect surface |
US5719425A (en) * | 1996-01-31 | 1998-02-17 | Micron Technology, Inc. | Multiple implant lightly doped drain (MILDD) field effect transistor |
US5739066A (en) * | 1996-09-17 | 1998-04-14 | Micron Technology, Inc. | Semiconductor processing methods of forming a conductive gate and line |
US5753557A (en) * | 1996-10-07 | 1998-05-19 | Vanguard International Semiconductor Company | Bridge-free self aligned silicide process |
US5783486A (en) * | 1996-10-18 | 1998-07-21 | Vanguard International Semiconductor Corporation | Bridge-free self aligned silicide process |
US20020137890A1 (en) * | 1997-03-31 | 2002-09-26 | Genentech, Inc. | Secreted and transmembrane polypeptides and nucleic acids encoding the same |
EP0869555A3 (de) * | 1997-04-01 | 1999-04-21 | STMicroelectronics, Inc. | Selbstjustierte Kontakte für integrierte Halbleiterschaltkreise und Verfahren zu ihrer Herstellung |
US5998274A (en) * | 1997-04-10 | 1999-12-07 | Micron Technology, Inc. | Method of forming a multiple implant lightly doped drain (MILDD) field effect transistor |
JPH1117000A (ja) * | 1997-06-27 | 1999-01-22 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6156613A (en) * | 1998-03-02 | 2000-12-05 | Texas Instruments - Acer Incorporated | Method to form MOSFET with an elevated source/drain |
US6022784A (en) * | 1998-04-06 | 2000-02-08 | Motorola, Inc. | Method for manufacturing a semiconductor device |
US6297170B1 (en) * | 1998-06-23 | 2001-10-02 | Vlsi Technology, Inc. | Sacrificial multilayer anti-reflective coating for mos gate formation |
US6143611A (en) | 1998-07-30 | 2000-11-07 | Micron Technology, Inc. | Semiconductor processing methods, methods of forming electronic components, and transistors |
US6743679B2 (en) | 1999-03-03 | 2004-06-01 | Koninklijke Philips Electronics N.V. | Integrated circuit devices with high and low voltage components and processes for manufacturing these devices |
US6346449B1 (en) * | 1999-05-17 | 2002-02-12 | Taiwan Semiconductor Manufacturing Company | Non-distort spacer profile during subsequent processing |
US6410210B1 (en) * | 1999-05-20 | 2002-06-25 | Philips Semiconductors | Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides |
JP2002110965A (ja) * | 2000-09-26 | 2002-04-12 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置 |
JP2002110967A (ja) * | 2000-09-26 | 2002-04-12 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置 |
JP2002110966A (ja) | 2000-09-26 | 2002-04-12 | Seiko Epson Corp | 半導体装置の製造方法および半導体装置 |
DE102008016429A1 (de) * | 2008-03-31 | 2009-10-01 | Advanced Micro Devices, Inc., Sunnyvale | Verfahren zur Herstellung dünner Schichten durch einen thermisch aktivierten Prozess unter Anwendung eines Temperaturgradienten über das Substrat hinweg |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3174638D1 (en) * | 1980-10-29 | 1986-06-19 | Fairchild Camera Instr Co | A method of fabricating a self-aligned integrated circuit structure using differential oxide growth |
NL187328C (nl) * | 1980-12-23 | 1991-08-16 | Philips Nv | Werkwijze ter vervaardiging van een halfgeleiderinrichting. |
US4486943A (en) * | 1981-12-16 | 1984-12-11 | Inmos Corporation | Zero drain overlap and self aligned contact method for MOS devices |
US4419810A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Self-aligned field effect transistor process |
US4419809A (en) * | 1981-12-30 | 1983-12-13 | International Business Machines Corporation | Fabrication process of sub-micrometer channel length MOSFETs |
JPS58158972A (ja) * | 1982-03-16 | 1983-09-21 | Toshiba Corp | 半導体装置の製造方法 |
DE3211761A1 (de) * | 1982-03-30 | 1983-10-06 | Siemens Ag | Verfahren zum herstellen von integrierten mos-feldeffekttransistorschaltungen in siliziumgate-technologie mit silizid beschichteten diffusionsgebieten als niederohmige leiterbahnen |
GB2123605A (en) * | 1982-06-22 | 1984-02-01 | Standard Microsyst Smc | MOS integrated circuit structure and method for its fabrication |
US4503601A (en) * | 1983-04-18 | 1985-03-12 | Ncr Corporation | Oxide trench structure for polysilicon gates and interconnects |
CA1252227A (en) * | 1984-07-09 | 1989-04-04 | Fairchild Camera And Instrument Corporation | Self-aligned silicide base contact for bipolar transistor |
JPS6143477A (ja) * | 1984-08-08 | 1986-03-03 | Hitachi Ltd | Mosトランジスタの製造方法 |
JPS6153773A (ja) * | 1984-08-24 | 1986-03-17 | Hitachi Ltd | 半導体装置およびその製造方法 |
JPS61212067A (ja) * | 1985-03-18 | 1986-09-20 | Sony Corp | 半導体装置の製法 |
JPS61214472A (ja) * | 1985-03-19 | 1986-09-24 | Oki Electric Ind Co Ltd | 半導体素子の製造方法 |
US4841347A (en) * | 1985-10-30 | 1989-06-20 | General Electric Company | MOS VLSI device having shallow junctions and method of making same |
JPS62118578A (ja) * | 1985-11-18 | 1987-05-29 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US4737472A (en) * | 1985-12-17 | 1988-04-12 | Siemens Aktiengesellschaft | Process for the simultaneous production of self-aligned bipolar transistors and complementary MOS transistors on a common silicon substrate |
US4701423A (en) * | 1985-12-20 | 1987-10-20 | Ncr Corporation | Totally self-aligned CMOS process |
US4703551A (en) * | 1986-01-24 | 1987-11-03 | Ncr Corporation | Process for forming LDD MOS/CMOS structures |
JPS62173763A (ja) * | 1986-01-27 | 1987-07-30 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
JPS6373667A (ja) * | 1986-09-17 | 1988-04-04 | Sanyo Electric Co Ltd | Mos半導体装置の製造方法 |
-
1987
- 1987-10-05 US US07/104,187 patent/US4786609A/en not_active Expired - Lifetime
-
1988
- 1988-09-28 DE DE3855861T patent/DE3855861T2/de not_active Expired - Lifetime
- 1988-09-28 EP EP88202104A patent/EP0315229B1/de not_active Expired - Lifetime
- 1988-10-03 JP JP63249704A patent/JPH081957B2/ja not_active Expired - Lifetime
- 1988-10-05 KR KR1019880012953A patent/KR0136881B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
EP0315229B1 (de) | 1997-04-09 |
DE3855861T2 (de) | 1997-10-23 |
EP0315229A2 (de) | 1989-05-10 |
EP0315229A3 (de) | 1991-04-17 |
US4786609A (en) | 1988-11-22 |
JPH081957B2 (ja) | 1996-01-10 |
JPH01134972A (ja) | 1989-05-26 |
KR0136881B1 (ko) | 1998-04-29 |
KR890007366A (ko) | 1989-06-19 |
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