DE69231655T2 - Verfahren zur Herstellung einer Graberstruktur in einem Halbleitersubstrat - Google Patents

Verfahren zur Herstellung einer Graberstruktur in einem Halbleitersubstrat

Info

Publication number
DE69231655T2
DE69231655T2 DE69231655T DE69231655T DE69231655T2 DE 69231655 T2 DE69231655 T2 DE 69231655T2 DE 69231655 T DE69231655 T DE 69231655T DE 69231655 T DE69231655 T DE 69231655T DE 69231655 T2 DE69231655 T2 DE 69231655T2
Authority
DE
Germany
Prior art keywords
producing
semiconductor substrate
grab structure
grab
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69231655T
Other languages
English (en)
Other versions
DE69231655D1 (de
Inventor
Syd R Wilson
Yee-Chaung See
Han-Bin Kuo Liang
Thomas Zirkle
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Motorola Solutions Inc
Original Assignee
Motorola Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Motorola Inc filed Critical Motorola Inc
Application granted granted Critical
Publication of DE69231655D1 publication Critical patent/DE69231655D1/de
Publication of DE69231655T2 publication Critical patent/DE69231655T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Element Separation (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
DE69231655T 1991-09-27 1992-09-24 Verfahren zur Herstellung einer Graberstruktur in einem Halbleitersubstrat Expired - Fee Related DE69231655T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/766,316 US5112772A (en) 1991-09-27 1991-09-27 Method of fabricating a trench structure

Publications (2)

Publication Number Publication Date
DE69231655D1 DE69231655D1 (de) 2001-03-01
DE69231655T2 true DE69231655T2 (de) 2001-06-28

Family

ID=25076076

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69231655T Expired - Fee Related DE69231655T2 (de) 1991-09-27 1992-09-24 Verfahren zur Herstellung einer Graberstruktur in einem Halbleitersubstrat

Country Status (4)

Country Link
US (1) US5112772A (de)
EP (1) EP0534746B1 (de)
JP (1) JPH05206262A (de)
DE (1) DE69231655T2 (de)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5332920A (en) * 1988-02-08 1994-07-26 Kabushiki Kaisha Toshiba Dielectrically isolated high and low voltage substrate regions
JPH05152429A (ja) * 1991-11-28 1993-06-18 Nec Corp 半導体装置の製造方法
US5292683A (en) * 1993-06-09 1994-03-08 Micron Semiconductor, Inc. Method of isolating semiconductor devices and arrays of memory integrated circuitry
DE4341171C2 (de) * 1993-12-02 1997-04-17 Siemens Ag Verfahren zur Herstellung einer integrierten Schaltungsanordnung
US5604159A (en) * 1994-01-31 1997-02-18 Motorola, Inc. Method of making a contact structure
US5994718A (en) * 1994-04-15 1999-11-30 National Semiconductor Corporation Trench refill with selective polycrystalline materials
US5693971A (en) * 1994-07-14 1997-12-02 Micron Technology, Inc. Combined trench and field isolation structure for semiconductor devices
US5786263A (en) * 1995-04-04 1998-07-28 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
KR0186083B1 (ko) * 1995-08-12 1999-04-15 문정환 반도체 소자의 소자격리방법
KR100214068B1 (ko) * 1995-11-21 1999-08-02 김영환 반도체 장치의 소자분리막 형성방법
KR100236097B1 (ko) * 1996-10-30 1999-12-15 김영환 반도체 장치의 격리막 형성방법
US5858830A (en) * 1997-06-12 1999-01-12 Taiwan Semiconductor Manufacturing Company, Ltd. Method of making dual isolation regions for logic and embedded memory devices
US5989977A (en) * 1998-04-20 1999-11-23 Texas Instruments - Acer Incorporated Shallow trench isolation process
KR100289749B1 (ko) * 1998-05-12 2001-05-15 윤종용 도전패드형성방법
EP0978872B1 (de) * 1998-08-03 2011-10-12 STMicroelectronics Srl Ein preiswertes Verfahren zur Herstellung eines SOI-Wafers
US6225171B1 (en) 1998-11-16 2001-05-01 Taiwan Semiconductor Manufacturing Company Shallow trench isolation process for reduced for junction leakage
US6010948A (en) * 1999-02-05 2000-01-04 Taiwan Semiconductor Manufacturing Company Shallow trench isolation process employing a BPSG trench fill
US6284626B1 (en) * 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6524931B1 (en) 1999-07-20 2003-02-25 Motorola, Inc. Method for forming a trench isolation structure in an integrated circuit
JP2002076113A (ja) * 2000-08-31 2002-03-15 Matsushita Electric Ind Co Ltd 半導体装置およびその製造方法
US6828211B2 (en) * 2002-10-01 2004-12-07 Taiwan Semiconductor Manufacturing Co., Ltd. Shallow trench filled with two or more dielectrics for isolation and coupling or for stress control
US6974755B2 (en) * 2003-08-15 2005-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure with nitrogen-containing liner and methods of manufacture
US20060264054A1 (en) * 2005-04-06 2006-11-23 Gutsche Martin U Method for etching a trench in a semiconductor substrate
US8505110B2 (en) * 2007-10-10 2013-08-06 Eloret Corporation Apparatus and process for controlled nanomanufacturing using catalyst retaining structures
CN110120365A (zh) * 2019-05-14 2019-08-13 德淮半导体有限公司 隔离结构及其形成方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5961045A (ja) * 1982-09-29 1984-04-07 Fujitsu Ltd 半導体装置の製造方法
US5061653A (en) * 1989-02-22 1991-10-29 Texas Instruments Incorporated Trench isolation process
US4994406A (en) * 1989-11-03 1991-02-19 Motorola Inc. Method of fabricating semiconductor devices having deep and shallow isolation structures

Also Published As

Publication number Publication date
EP0534746B1 (de) 2001-01-24
EP0534746A3 (en) 1994-08-17
EP0534746A2 (de) 1993-03-31
DE69231655D1 (de) 2001-03-01
US5112772A (en) 1992-05-12
JPH05206262A (ja) 1993-08-13

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee