DE4391302T1 - Verfahren zur Herstellung eines Halbleiters mit einer guten Intrinsic-Getterung - Google Patents

Verfahren zur Herstellung eines Halbleiters mit einer guten Intrinsic-Getterung

Info

Publication number
DE4391302T1
DE4391302T1 DE4391302T DE4391302T DE4391302T1 DE 4391302 T1 DE4391302 T1 DE 4391302T1 DE 4391302 T DE4391302 T DE 4391302T DE 4391302 T DE4391302 T DE 4391302T DE 4391302 T1 DE4391302 T1 DE 4391302T1
Authority
DE
Germany
Prior art keywords
semiconductor
producing
intrinsic gettering
good intrinsic
good
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
DE4391302T
Other languages
English (en)
Other versions
DE4391302B4 (de
Inventor
Alain Comeau
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Microsemi Semiconductor ULC
Original Assignee
Mitel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitel Corp filed Critical Mitel Corp
Publication of DE4391302T1 publication Critical patent/DE4391302T1/de
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • H01L21/3221—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections of silicon bodies, e.g. for gettering
    • H01L21/3225—Thermally inducing defects using oxygen present in the silicon body for intrinsic gettering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
DE4391302T 1992-03-31 1993-03-26 Verfahren zur Herstellung eines Halbleiters mit einer guten Intrinsic-Getterung Pending DE4391302T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CA002064486A CA2064486C (en) 1992-03-31 1992-03-31 Method of preparing semiconductor wafer with good intrinsic gettering
PCT/CA1993/000123 WO1993020582A1 (en) 1992-03-31 1993-03-26 Method of preparing semiconductor with good intrinsic gettering

Publications (1)

Publication Number Publication Date
DE4391302T1 true DE4391302T1 (de) 1995-04-13

Family

ID=4149527

Family Applications (2)

Application Number Title Priority Date Filing Date
DE4391302A Expired - Lifetime DE4391302B4 (de) 1992-03-31 1993-03-26 Verfahren zur Herstellung eines Halbleiters mit einer guten Intrinsic-Getterung
DE4391302T Pending DE4391302T1 (de) 1992-03-31 1993-03-26 Verfahren zur Herstellung eines Halbleiters mit einer guten Intrinsic-Getterung

Family Applications Before (1)

Application Number Title Priority Date Filing Date
DE4391302A Expired - Lifetime DE4391302B4 (de) 1992-03-31 1993-03-26 Verfahren zur Herstellung eines Halbleiters mit einer guten Intrinsic-Getterung

Country Status (7)

Country Link
US (1) US5587325A (de)
JP (1) JPH07508613A (de)
KR (1) KR950701138A (de)
CA (1) CA2064486C (de)
DE (2) DE4391302B4 (de)
GB (1) GB2280312B (de)
WO (1) WO1993020582A1 (de)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2874834B2 (ja) * 1994-07-29 1999-03-24 三菱マテリアル株式会社 シリコンウェーハのイントリンシックゲッタリング処理法
US5593494A (en) * 1995-03-14 1997-01-14 Memc Electronic Materials, Inc. Precision controlled precipitation of oxygen in silicon
DE19538983A1 (de) * 1995-10-19 1997-04-24 Siemens Ag Verfahren zum Beseitigen von Kristallfehlern in Siliziumscheiben
US6004868A (en) 1996-01-17 1999-12-21 Micron Technology, Inc. Method for CMOS well drive in a non-inert ambient
KR100881511B1 (ko) * 2001-07-10 2009-02-05 신에쯔 한도타이 가부시키가이샤 실리콘웨이퍼의 제조방법, 실리콘 에피텍셜 웨이퍼의제조방법 및 실리콘 에피텍셜 웨이퍼
US6444551B1 (en) * 2001-07-23 2002-09-03 Taiwan Semiconductor Manufacturing Company N-type buried layer drive-in recipe to reduce pits over buried antimony layer
ATE493755T1 (de) 2007-05-02 2011-01-15 Siltronic Ag Siliciumwafer und herstellungsverfahren dafür
US8258042B2 (en) * 2009-08-28 2012-09-04 Macronix International Co., Ltd. Buried layer of an integrated circuit
KR101231412B1 (ko) * 2009-12-29 2013-02-07 실트로닉 아게 실리콘 웨이퍼 및 그 제조 방법
CN102543675B (zh) * 2010-12-31 2014-11-05 中芯国际集成电路制造(上海)有限公司 玻璃衬底的处理方法
CN102842642A (zh) * 2011-06-23 2012-12-26 吉林庆达新能源电力股份有限公司 一种太阳能电池生产中单晶硅的扩散方法
US11881405B2 (en) 2022-02-04 2024-01-23 Applied Materials, Inc. Methods for forming N-type buried layer in a substrate by performing non-doping implant through oxide layer formed over the substrate

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4597804A (en) * 1981-03-11 1986-07-01 Fujitsu Limited Methods of forming denuded zone in wafer by intrinsic gettering and forming bipolar transistor therein
DE3280219D1 (de) * 1981-03-11 1990-08-30 Fujitsu Ltd Verfahren zur herstellung einer halbleiteranordnung mit ausgluehen eines halbleiterkoerpers.
JPS57197827A (en) * 1981-05-29 1982-12-04 Hitachi Ltd Semiconductor substrate
JPS5814538A (ja) * 1981-07-17 1983-01-27 Fujitsu Ltd 半導体装置の製造方法
EP0098406A1 (de) * 1982-07-06 1984-01-18 Texas Instruments Incorporated Wachsende Keimbildung von Änderungen in fester Phase
US4548654A (en) * 1983-06-03 1985-10-22 Motorola, Inc. Surface denuding of silicon wafer
JPS60133734A (ja) * 1983-12-21 1985-07-16 Mitsubishi Electric Corp 半導体装置の製造方法
JPS618931A (ja) * 1984-06-25 1986-01-16 Hitachi Ltd 半導体装置の製造方法
US4622082A (en) * 1984-06-25 1986-11-11 Monsanto Company Conditioned semiconductor substrates
JPS6120337A (ja) * 1984-07-09 1986-01-29 Nec Corp 半導体装置の製造方法
DD286460A5 (de) * 1987-03-19 1991-01-24 Akademie Der Wissenschaften Der Ddr,De Verfahren zur herstellung von mos-bauelementen mit sio tief 2/si tief 3n tief 4-isolatorschichten
US4851358A (en) * 1988-02-11 1989-07-25 Dns Electronic Materials, Inc. Semiconductor wafer fabrication with improved control of internal gettering sites using rapid thermal annealing
JPH03185831A (ja) * 1989-12-15 1991-08-13 Komatsu Denshi Kinzoku Kk 半導体装置の製造方法
US5141887A (en) * 1990-07-02 1992-08-25 Motorola, Inc. Low voltage, deep junction device and method
US5286658A (en) * 1991-03-05 1994-02-15 Fujitsu Limited Process for producing semiconductor device
JPH05308076A (ja) * 1992-03-03 1993-11-19 Fujitsu Ltd シリコンウエーハの酸素析出方法

Also Published As

Publication number Publication date
DE4391302B4 (de) 2007-07-26
WO1993020582A1 (en) 1993-10-14
KR950701138A (ko) 1995-02-20
KR100298067B1 (de) 2001-12-01
JPH07508613A (ja) 1995-09-21
CA2064486C (en) 2001-08-21
US5587325A (en) 1996-12-24
GB2280312A (en) 1995-01-25
GB9419512D0 (en) 1994-11-16
GB2280312B (en) 1996-03-06
CA2064486A1 (en) 1993-10-01

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