DE69232038T2 - Verfahren zur Herstellung einer Halbleiteranordnung mit Isolationszonen in einem Halbleitersubstrat - Google Patents
Verfahren zur Herstellung einer Halbleiteranordnung mit Isolationszonen in einem HalbleitersubstratInfo
- Publication number
- DE69232038T2 DE69232038T2 DE1992632038 DE69232038T DE69232038T2 DE 69232038 T2 DE69232038 T2 DE 69232038T2 DE 1992632038 DE1992632038 DE 1992632038 DE 69232038 T DE69232038 T DE 69232038T DE 69232038 T2 DE69232038 T2 DE 69232038T2
- Authority
- DE
- Germany
- Prior art keywords
- producing
- semiconductor
- isolation zones
- semiconductor substrate
- arrangement
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000004065 semiconductor Substances 0.000 title 2
- 238000002955 isolation Methods 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 239000000758 substrate Substances 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Element Separation (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US66334991A | 1991-03-04 | 1991-03-04 |
Publications (2)
Publication Number | Publication Date |
---|---|
DE69232038D1 DE69232038D1 (de) | 2001-10-11 |
DE69232038T2 true DE69232038T2 (de) | 2002-01-31 |
Family
ID=24661438
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE1992632038 Expired - Lifetime DE69232038T2 (de) | 1991-03-04 | 1992-02-28 | Verfahren zur Herstellung einer Halbleiteranordnung mit Isolationszonen in einem Halbleitersubstrat |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0502663B1 (de) |
JP (1) | JPH05102133A (de) |
DE (1) | DE69232038T2 (de) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5470783A (en) * | 1994-06-06 | 1995-11-28 | At&T Ipm Corp. | Method for integrated circuit device isolation |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0052948A1 (de) * | 1980-11-24 | 1982-06-02 | Motorola, Inc. | Herstellung von Oxid-Isolationen |
US4580330A (en) * | 1984-06-15 | 1986-04-08 | Texas Instruments Incorporated | Integrated circuit isolation |
US4923563A (en) * | 1987-06-15 | 1990-05-08 | Ncr Corporation | Semiconductor field oxide formation process using a sealing sidewall of consumable nitride |
-
1992
- 1992-02-28 JP JP7574592A patent/JPH05102133A/ja active Pending
- 1992-02-28 EP EP19920301710 patent/EP0502663B1/de not_active Expired - Lifetime
- 1992-02-28 DE DE1992632038 patent/DE69232038T2/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0502663B1 (de) | 2001-09-05 |
EP0502663A2 (de) | 1992-09-09 |
EP0502663A3 (en) | 1993-09-08 |
DE69232038D1 (de) | 2001-10-11 |
JPH05102133A (ja) | 1993-04-23 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8328 | Change in the person/name/address of the agent |
Representative=s name: FIENER, J., PAT.-ANW., 87719 MINDELHEIM |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: HYNIX SEMICONDUCTOR INC., ICHON, KYONGGI, KR Owner name: NCR INTERNATIONAL, INC., DAYTON, OHIO, US |
|
8327 | Change in the person/name/address of the patent owner |
Owner name: MAGNACHIP SEMICONDUCTOR, LTD., CHEONGJU, KR Owner name: NCR INTERNATIONAL, INC., DAYTON, OHIO, US |