DE3783799D1 - Verfahren zur herstellung einer halbleiteranordnung. - Google Patents

Verfahren zur herstellung einer halbleiteranordnung.

Info

Publication number
DE3783799D1
DE3783799D1 DE8787200371T DE3783799T DE3783799D1 DE 3783799 D1 DE3783799 D1 DE 3783799D1 DE 8787200371 T DE8787200371 T DE 8787200371T DE 3783799 T DE3783799 T DE 3783799T DE 3783799 D1 DE3783799 D1 DE 3783799D1
Authority
DE
Germany
Prior art keywords
producing
semiconductor arrangement
semiconductor
arrangement
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8787200371T
Other languages
English (en)
Other versions
DE3783799T2 (de
Inventor
Wilhelmus J M J Josquin
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Application granted granted Critical
Publication of DE3783799D1 publication Critical patent/DE3783799D1/de
Publication of DE3783799T2 publication Critical patent/DE3783799T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/082Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including bipolar components only
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66234Bipolar junction transistors [BJT]
    • H01L29/66272Silicon vertical transistors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Bipolar Transistors (AREA)
  • Junction Field-Effect Transistors (AREA)
DE8787200371T 1986-03-26 1987-03-02 Verfahren zur herstellung einer halbleiteranordnung. Expired - Fee Related DE3783799T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
NL8600769A NL8600769A (nl) 1986-03-26 1986-03-26 Werkwijze voor het vervaardigen van een halfgeleiderinrichting.

Publications (2)

Publication Number Publication Date
DE3783799D1 true DE3783799D1 (de) 1993-03-11
DE3783799T2 DE3783799T2 (de) 1993-07-01

Family

ID=19847771

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8787200371T Expired - Fee Related DE3783799T2 (de) 1986-03-26 1987-03-02 Verfahren zur herstellung einer halbleiteranordnung.

Country Status (7)

Country Link
EP (1) EP0242893B1 (de)
JP (1) JPS62232164A (de)
KR (1) KR950010052B1 (de)
CA (1) CA1288527C (de)
DE (1) DE3783799T2 (de)
ES (1) ES2038986T3 (de)
NL (1) NL8600769A (de)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01120847A (ja) * 1987-11-05 1989-05-12 Fujitsu Ltd 半導体装置
US5247197A (en) * 1987-11-05 1993-09-21 Fujitsu Limited Dynamic random access memory device having improved contact hole structures
US6091129A (en) * 1996-06-19 2000-07-18 Cypress Semiconductor Corporation Self-aligned trench isolated structure
US5830797A (en) * 1996-06-20 1998-11-03 Cypress Semiconductor Corporation Interconnect methods and apparatus
US6004874A (en) * 1996-06-26 1999-12-21 Cypress Semiconductor Corporation Method for forming an interconnect
US5911887A (en) * 1996-07-19 1999-06-15 Cypress Semiconductor Corporation Method of etching a bond pad

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS567463A (en) * 1979-06-29 1981-01-26 Hitachi Ltd Semiconductor device and its manufacture
JPS5870570A (ja) * 1981-09-28 1983-04-27 Fujitsu Ltd 半導体装置の製造方法
US4507171A (en) * 1982-08-06 1985-03-26 International Business Machines Corporation Method for contacting a narrow width PN junction region
JPS60163446A (ja) * 1984-02-02 1985-08-26 Pioneer Electronic Corp スル−ホ−ルの形成方法
JPS60194570A (ja) * 1984-03-16 1985-10-03 Toshiba Corp 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0242893B1 (de) 1993-01-27
ES2038986T3 (es) 1993-08-16
DE3783799T2 (de) 1993-07-01
EP0242893A1 (de) 1987-10-28
KR870009475A (ko) 1987-10-27
KR950010052B1 (en) 1995-09-06
CA1288527C (en) 1991-09-03
NL8600769A (nl) 1987-10-16
JPS62232164A (ja) 1987-10-12

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8327 Change in the person/name/address of the patent owner

Owner name: PHILIPS ELECTRONICS N.V., EINDHOVEN, NL

8339 Ceased/non-payment of the annual fee