DE3672570D1 - Verfahren zur herstellung einer planaren halbleiteranordnung mit graeben. - Google Patents
Verfahren zur herstellung einer planaren halbleiteranordnung mit graeben.Info
- Publication number
- DE3672570D1 DE3672570D1 DE8686114710T DE3672570T DE3672570D1 DE 3672570 D1 DE3672570 D1 DE 3672570D1 DE 8686114710 T DE8686114710 T DE 8686114710T DE 3672570 T DE3672570 T DE 3672570T DE 3672570 D1 DE3672570 D1 DE 3672570D1
- Authority
- DE
- Germany
- Prior art keywords
- trenches
- producing
- semiconductor arrangement
- planar semiconductor
- planar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31127—Etching organic layers
- H01L21/31133—Etching organic layers by chemical means
- H01L21/31138—Etching organic layers by chemical means by dry-etching
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/793,400 US4654120A (en) | 1985-10-31 | 1985-10-31 | Method of making a planar trench semiconductor structure |
Publications (1)
Publication Number | Publication Date |
---|---|
DE3672570D1 true DE3672570D1 (de) | 1990-08-16 |
Family
ID=25159837
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686114710T Expired - Fee Related DE3672570D1 (de) | 1985-10-31 | 1986-10-23 | Verfahren zur herstellung einer planaren halbleiteranordnung mit graeben. |
Country Status (5)
Country | Link |
---|---|
US (1) | US4654120A (de) |
EP (1) | EP0224039B1 (de) |
JP (1) | JPS62106644A (de) |
CA (1) | CA1267349A (de) |
DE (1) | DE3672570D1 (de) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4725562A (en) * | 1986-03-27 | 1988-02-16 | International Business Machines Corporation | Method of making a contact to a trench isolated device |
US4836885A (en) * | 1988-05-03 | 1989-06-06 | International Business Machines Corporation | Planarization process for wide trench isolation |
JPH02183552A (ja) * | 1989-01-09 | 1990-07-18 | Nec Corp | 集積回路の製造方法 |
DE3914065A1 (de) * | 1989-04-28 | 1990-10-31 | Leybold Ag | Vorrichtung zur durchfuehrung von plasma-aetzverfahren |
DE4300765C1 (de) * | 1993-01-14 | 1993-12-23 | Bosch Gmbh Robert | Verfahren zum Planarisieren grabenförmiger Strukturen |
US5521422A (en) * | 1994-12-02 | 1996-05-28 | International Business Machines Corporation | Corner protected shallow trench isolation device |
US5705428A (en) * | 1995-08-03 | 1998-01-06 | Chartered Semiconductor Manufacturing Pte, Ltd. | Method for preventing titanium lifting during and after metal etching |
JP2687948B2 (ja) * | 1995-10-05 | 1997-12-08 | 日本電気株式会社 | 半導体装置の製造方法 |
US5863828A (en) * | 1996-09-25 | 1999-01-26 | National Semiconductor Corporation | Trench planarization technique |
US5994202A (en) * | 1997-01-23 | 1999-11-30 | International Business Machines Corporation | Threshold voltage tailoring of the corner of a MOSFET device |
US5880005A (en) * | 1997-10-23 | 1999-03-09 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for forming a tapered profile insulator shape |
US6365968B1 (en) | 1998-08-07 | 2002-04-02 | Corning Lasertron, Inc. | Polyimide/silicon oxide bi-layer for bond pad parasitic capacitance control in semiconductor electro-optical device |
WO2001026193A1 (en) * | 1999-10-01 | 2001-04-12 | Corning Lasertron, Inc. | Method for making a ridge waveguide semiconductor device |
US6251747B1 (en) * | 1999-11-02 | 2001-06-26 | Philips Semiconductors, Inc. | Use of an insulating spacer to prevent threshold voltage roll-off in narrow devices |
US6593210B1 (en) * | 2000-10-24 | 2003-07-15 | Advanced Micro Devices, Inc. | Self-aligned/maskless reverse etch process using an inorganic film |
CN100461433C (zh) * | 2007-01-04 | 2009-02-11 | 北京京东方光电科技有限公司 | 一种tft阵列结构及其制造方法 |
US8017493B2 (en) * | 2008-05-12 | 2011-09-13 | Texas Instruments Incorporated | Method of planarizing a semiconductor device |
JP5679626B2 (ja) * | 2008-07-07 | 2015-03-04 | セイコーインスツル株式会社 | 半導体装置 |
Family Cites Families (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2629996A1 (de) * | 1976-07-03 | 1978-01-05 | Ibm Deutschland | Verfahren zur passivierung und planarisierung eines metallisierungsmusters |
US4318751A (en) * | 1980-03-13 | 1982-03-09 | International Business Machines Corporation | Self-aligned process for providing an improved high performance bipolar transistor |
US4389281A (en) * | 1980-12-16 | 1983-06-21 | International Business Machines Corporation | Method of planarizing silicon dioxide in semiconductor devices |
JPS57204133A (en) * | 1981-06-10 | 1982-12-14 | Hitachi Ltd | Manufacture of semiconductor integrated circuit |
JPS59158534A (ja) * | 1983-02-28 | 1984-09-08 | Oki Electric Ind Co Ltd | 半導体装置の製造方法 |
US4519128A (en) * | 1983-10-05 | 1985-05-28 | International Business Machines Corporation | Method of making a trench isolated device |
JPS60120723A (ja) * | 1983-11-30 | 1985-06-28 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | 電子装置 |
US4545852A (en) * | 1984-06-20 | 1985-10-08 | Hewlett-Packard Company | Planarization of dielectric films on integrated circuits |
-
1985
- 1985-10-31 US US06/793,400 patent/US4654120A/en not_active Expired - Fee Related
-
1986
- 1986-05-05 CA CA000508351A patent/CA1267349A/en not_active Expired - Fee Related
- 1986-09-19 JP JP61219917A patent/JPS62106644A/ja active Granted
- 1986-10-23 DE DE8686114710T patent/DE3672570D1/de not_active Expired - Fee Related
- 1986-10-23 EP EP86114710A patent/EP0224039B1/de not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
EP0224039A2 (de) | 1987-06-03 |
EP0224039B1 (de) | 1990-07-11 |
US4654120A (en) | 1987-03-31 |
JPS62106644A (ja) | 1987-05-18 |
EP0224039A3 (en) | 1987-12-02 |
JPH0347740B2 (de) | 1991-07-22 |
CA1267349A (en) | 1990-04-03 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |