DE3686125D1 - Verfahren zur herstellung einer integrierten schaltung. - Google Patents
Verfahren zur herstellung einer integrierten schaltung.Info
- Publication number
- DE3686125D1 DE3686125D1 DE8686114064T DE3686125T DE3686125D1 DE 3686125 D1 DE3686125 D1 DE 3686125D1 DE 8686114064 T DE8686114064 T DE 8686114064T DE 3686125 T DE3686125 T DE 3686125T DE 3686125 D1 DE3686125 D1 DE 3686125D1
- Authority
- DE
- Germany
- Prior art keywords
- producing
- integrated circuit
- integrated
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 238000004519 manufacturing process Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/763—Polycrystalline semiconductor regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2254—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides
- H01L21/2255—Diffusion into or out of group IV semiconductors from or through or into an applied layer, e.g. photoresist, nitrides the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
- H01L21/743—Making of internal connections, substrate contacts
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Crystallography & Structural Chemistry (AREA)
- Element Separation (AREA)
- Electrodes Of Semiconductors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US06/793,518 US4745081A (en) | 1985-10-31 | 1985-10-31 | Method of trench filling |
Publications (2)
Publication Number | Publication Date |
---|---|
DE3686125D1 true DE3686125D1 (de) | 1992-08-27 |
DE3686125T2 DE3686125T2 (de) | 1993-03-11 |
Family
ID=25160098
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
DE8686114064T Expired - Fee Related DE3686125T2 (de) | 1985-10-31 | 1986-10-10 | Verfahren zur herstellung einer integrierten schaltung. |
Country Status (4)
Country | Link |
---|---|
US (2) | US4745081A (de) |
EP (1) | EP0221394B1 (de) |
JP (1) | JPS62105445A (de) |
DE (1) | DE3686125T2 (de) |
Families Citing this family (78)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS63122261A (ja) * | 1986-11-12 | 1988-05-26 | Mitsubishi Electric Corp | 半導体装置の製造方法 |
US4845051A (en) * | 1987-10-29 | 1989-07-04 | Siliconix Incorporated | Buried gate JFET |
US4835115A (en) * | 1987-12-07 | 1989-05-30 | Texas Instruments Incorporated | Method for forming oxide-capped trench isolation |
JPH01173714A (ja) * | 1987-12-21 | 1989-07-10 | Internatl Business Mach Corp <Ibm> | ブリツジ接点の形成方法 |
US4873205A (en) * | 1987-12-21 | 1989-10-10 | International Business Machines Corporation | Method for providing silicide bridge contact between silicon regions separated by a thin dielectric |
JPH0656865B2 (ja) * | 1988-10-13 | 1994-07-27 | 株式会社東芝 | 高耐圧素子用接着基板 |
IT1225625B (it) * | 1988-11-03 | 1990-11-22 | Sgs Thomson Microelectronics | Procedimento per la realizzazione di strutture di isolamento incassate nel substrato di silicio per dispositivi cmos ed nmos. |
US5105253A (en) * | 1988-12-28 | 1992-04-14 | Synergy Semiconductor Corporation | Structure for a substrate tap in a bipolar structure |
JPH02271535A (ja) * | 1988-12-28 | 1990-11-06 | Synergy Semiconductor Corp | バイポーラ構造における基板タップ及びこの製造方法 |
US5108946A (en) * | 1989-05-19 | 1992-04-28 | Motorola, Inc. | Method of forming planar isolation regions |
JPH0358484A (ja) * | 1989-07-27 | 1991-03-13 | Toshiba Corp | 半導体装置とその製造方法 |
US5223736A (en) * | 1989-09-27 | 1993-06-29 | Texas Instruments Incorporated | Trench isolation process with reduced topography |
US5077228A (en) * | 1989-12-01 | 1991-12-31 | Texas Instruments Incorporated | Process for simultaneous formation of trench contact and vertical transistor gate and structure |
US5159429A (en) * | 1990-01-23 | 1992-10-27 | International Business Machines Corporation | Semiconductor device structure employing a multi-level epitaxial structure and method of manufacturing same |
US5061652A (en) * | 1990-01-23 | 1991-10-29 | International Business Machines Corporation | Method of manufacturing a semiconductor device structure employing a multi-level epitaxial structure |
JP2641781B2 (ja) * | 1990-02-23 | 1997-08-20 | シャープ株式会社 | 半導体素子分離領域の形成方法 |
US5296392A (en) * | 1990-03-06 | 1994-03-22 | Digital Equipment Corporation | Method of forming trench isolated regions with sidewall doping |
US5139966A (en) * | 1990-04-02 | 1992-08-18 | National Semiconductor Corporation | Low resistance silicided substrate contact |
JP2757927B2 (ja) * | 1990-06-28 | 1998-05-25 | インターナショナル・ビジネス・マシーンズ・コーポレイション | 半導体基板上の隔置されたシリコン領域の相互接続方法 |
US5413966A (en) * | 1990-12-20 | 1995-05-09 | Lsi Logic Corporation | Shallow trench etch |
US5290396A (en) * | 1991-06-06 | 1994-03-01 | Lsi Logic Corporation | Trench planarization techniques |
US5192708A (en) * | 1991-04-29 | 1993-03-09 | International Business Machines Corporation | Sub-layer contact technique using in situ doped amorphous silicon and solid phase recrystallization |
US5250461A (en) * | 1991-05-17 | 1993-10-05 | Delco Electronics Corporation | Method for dielectrically isolating integrated circuits using doped oxide sidewalls |
US5225358A (en) * | 1991-06-06 | 1993-07-06 | Lsi Logic Corporation | Method of forming late isolation with polishing |
US5248625A (en) * | 1991-06-06 | 1993-09-28 | Lsi Logic Corporation | Techniques for forming isolation structures |
US5252503A (en) * | 1991-06-06 | 1993-10-12 | Lsi Logic Corporation | Techniques for forming isolation structures |
JPH0513566A (ja) * | 1991-07-01 | 1993-01-22 | Toshiba Corp | 半導体装置の製造方法 |
JPH05211239A (ja) * | 1991-09-12 | 1993-08-20 | Texas Instr Inc <Ti> | 集積回路相互接続構造とそれを形成する方法 |
US5185294A (en) * | 1991-11-22 | 1993-02-09 | International Business Machines Corporation | Boron out-diffused surface strap process |
JP2890380B2 (ja) * | 1991-11-27 | 1999-05-10 | 三菱電機株式会社 | 半導体装置およびその製造方法 |
US5236863A (en) * | 1992-06-01 | 1993-08-17 | National Semiconductor Corporation | Isolation process for VLSI |
US5217920A (en) * | 1992-06-18 | 1993-06-08 | Motorola, Inc. | Method of forming substrate contact trenches and isolation trenches using anodization for isolation |
US5346584A (en) * | 1993-07-28 | 1994-09-13 | Digital Equipment Corporation | Planarization process for IC trench isolation using oxidized polysilicon filler |
US5494857A (en) * | 1993-07-28 | 1996-02-27 | Digital Equipment Corporation | Chemical mechanical planarization of shallow trenches in semiconductor substrates |
US5479048A (en) * | 1994-02-04 | 1995-12-26 | Analog Devices, Inc. | Integrated circuit chip supported by a handle wafer and provided with means to maintain the handle wafer potential at a desired level |
US5492858A (en) * | 1994-04-20 | 1996-02-20 | Digital Equipment Corporation | Shallow trench isolation process for high aspect ratio trenches |
US5872044A (en) * | 1994-06-15 | 1999-02-16 | Harris Corporation | Late process method for trench isolation |
JPH08195433A (ja) * | 1995-01-19 | 1996-07-30 | Toshiba Corp | 半導体装置及びその製造方法 |
JP3360970B2 (ja) * | 1995-05-22 | 2003-01-07 | 株式会社東芝 | 半導体装置の製造方法 |
US5920108A (en) * | 1995-06-05 | 1999-07-06 | Harris Corporation | Late process method and apparatus for trench isolation |
US5859466A (en) | 1995-06-07 | 1999-01-12 | Nippon Steel Semiconductor Corporation | Semiconductor device having a field-shield device isolation structure and method for making thereof |
KR100192178B1 (ko) * | 1996-01-11 | 1999-06-15 | 김영환 | 반도체 소자의 아이솔레이션 방법 |
US5817560A (en) * | 1996-09-12 | 1998-10-06 | Advanced Micro Devices, Inc. | Ultra short trench transistors and process for making same |
JPH10284591A (ja) * | 1997-02-28 | 1998-10-23 | Internatl Rectifier Corp | 半導体装置及びその製造方法 |
US5851900A (en) * | 1997-04-28 | 1998-12-22 | Mosel Vitelic Inc. | Method of manufacturing a shallow trench isolation for a semiconductor device |
AT2173U1 (de) | 1997-06-19 | 1998-05-25 | Austria Mikrosysteme Int | Verfahren zur herstellung von begrenzten, dotierten teilgebieten in einem substratmaterial aus monokristallinem silizium |
AU8369398A (en) | 1997-07-11 | 1999-02-08 | Telefonaktiebolaget Lm Ericsson (Publ) | A process for manufacturing ic-components to be used at radio frequencies |
US6251734B1 (en) | 1998-07-01 | 2001-06-26 | Motorola, Inc. | Method for fabricating trench isolation and trench substrate contact |
US6251769B1 (en) * | 1999-07-02 | 2001-06-26 | United Microelectronics Corp | Method of manufacturing contact pad |
US6388305B1 (en) * | 1999-12-17 | 2002-05-14 | International Business Machines Corporation | Electrically programmable antifuses and methods for forming the same |
US6627949B2 (en) * | 2000-06-02 | 2003-09-30 | General Semiconductor, Inc. | High voltage power MOSFET having low on-resistance |
KR100389923B1 (ko) | 2001-01-16 | 2003-07-04 | 삼성전자주식회사 | 트렌치 소자 분리구조를 가지는 반도체 소자 및 트렌치소자 분리 방법 |
DE10110974C2 (de) * | 2001-03-07 | 2003-07-24 | Infineon Technologies Ag | Verfahren zum Verbreitern eines aktiven Halbleitergebiets auf einem Halbleitersubstrat |
JP2002359290A (ja) | 2001-03-27 | 2002-12-13 | Matsushita Electric Ind Co Ltd | 半導体集積装置 |
US6621136B2 (en) | 2001-09-28 | 2003-09-16 | Semiconductor Components Industries Llc | Semiconductor device having regions of low substrate capacitance |
US6696349B2 (en) * | 2001-11-13 | 2004-02-24 | Infineon Technologies Richmond Lp | STI leakage reduction |
KR100400254B1 (ko) * | 2001-12-18 | 2003-10-01 | 주식회사 하이닉스반도체 | 반도체 소자의 제조방법 |
US6724798B2 (en) | 2001-12-31 | 2004-04-20 | Honeywell International Inc. | Optoelectronic devices and method of production |
US6994903B2 (en) * | 2002-01-03 | 2006-02-07 | International Business Machines Corp. | Hybrid substrate and method for fabricating the same |
KR100669645B1 (ko) * | 2002-11-12 | 2007-01-16 | 마이크론 테크놀로지, 인크 | 씨모스 이미지 센서의 암전류를 감소시키기 위한 접지게이트 및 아이솔레이션 기술 |
US6646320B1 (en) * | 2002-11-21 | 2003-11-11 | National Semiconductor Corporation | Method of forming contact to poly-filled trench isolation region |
DE10320414A1 (de) * | 2003-05-07 | 2004-12-23 | Infineon Technologies Ag | Halbleiteranordnung mit Schutzanordnung zur Verhinderung einer Diffusion von Minoritätsladungsträgern |
US6818950B1 (en) * | 2003-05-13 | 2004-11-16 | Micrel, Inc. | Increasing switching speed of geometric construction gate MOSFET structures |
US7410864B2 (en) * | 2004-04-23 | 2008-08-12 | Infineon Technologies Ag | Trench and a trench capacitor and method for forming the same |
DE102004028679A1 (de) * | 2004-06-14 | 2006-01-05 | Infineon Technologies Ag | Isolationsgrabenanordnung |
US7468307B2 (en) | 2005-06-29 | 2008-12-23 | Infineon Technologies Ag | Semiconductor structure and method |
DE102006029701B4 (de) * | 2006-06-28 | 2017-06-01 | Infineon Technologies Ag | Halbleiterbauteil sowie Verfahren zur Herstellung eines Halbleiterbauteils |
US7982284B2 (en) | 2006-06-28 | 2011-07-19 | Infineon Technologies Ag | Semiconductor component including an isolation structure and a contact to the substrate |
DE102006046377A1 (de) * | 2006-09-29 | 2008-04-03 | Advanced Micro Devices, Inc., Sunnyvale | Halbleiterbauelement mit Isoliergräben, die unterschiedliche Arten an Verformung hervorrufen |
DE102007018098B4 (de) | 2007-04-17 | 2016-06-16 | Austriamicrosystems Ag | Verfahren zum Herstellen eines Halbleiterkörpers mit einem Graben und Halbleiterkörper mit einem Graben |
US8064224B2 (en) * | 2008-03-31 | 2011-11-22 | Intel Corporation | Microelectronic package containing silicon patches for high density interconnects, and method of manufacturing same |
DE102010006996B4 (de) | 2010-02-05 | 2017-08-24 | Austriamicrosystems Ag | Verfahren zur Herstellung eines Halbleiterbauelements |
US8492260B2 (en) * | 2010-08-30 | 2013-07-23 | Semionductor Components Industries, LLC | Processes of forming an electronic device including a feature in a trench |
US8647945B2 (en) * | 2010-12-03 | 2014-02-11 | International Business Machines Corporation | Method of forming substrate contact for semiconductor on insulator (SOI) substrate |
US8673737B2 (en) * | 2011-10-17 | 2014-03-18 | International Business Machines Corporation | Array and moat isolation structures and method of manufacture |
US20160043218A1 (en) * | 2014-08-05 | 2016-02-11 | Semiconductor Components Industries, Llc | Semiconductor component and method of manufacture |
US9812354B2 (en) | 2015-05-15 | 2017-11-07 | Semiconductor Components Industries, Llc | Process of forming an electronic device including a material defining a void |
CN109994537B (zh) | 2017-12-29 | 2022-09-06 | 联华电子股份有限公司 | 半导体元件及其制作方法 |
Family Cites Families (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4256514A (en) * | 1978-11-03 | 1981-03-17 | International Business Machines Corporation | Method for forming a narrow dimensioned region on a body |
US4462040A (en) * | 1979-05-07 | 1984-07-24 | International Business Machines Corporation | Single electrode U-MOSFET random access memory |
CA1142261A (en) * | 1979-06-29 | 1983-03-01 | Siegfried K. Wiedmann | Interconnection of opposite conductivity type semiconductor regions |
US4470062A (en) * | 1979-08-31 | 1984-09-04 | Hitachi, Ltd. | Semiconductor device having isolation regions |
JPS56137647A (en) * | 1980-03-31 | 1981-10-27 | Chiyou Lsi Gijutsu Kenkyu Kumiai | Semiconductor and its manufacture |
FR2480501A1 (fr) * | 1980-04-14 | 1981-10-16 | Thomson Csf | Dispositif semi-conducteur a grille profonde accessible par la surface et procede de fabrication |
JPS57201070A (en) * | 1981-06-05 | 1982-12-09 | Seiko Epson Corp | Semiconductor device |
US4446476A (en) * | 1981-06-30 | 1984-05-01 | International Business Machines Corporation | Integrated circuit having a sublayer electrical contact and fabrication thereof |
JPS5850752A (ja) * | 1981-09-21 | 1983-03-25 | Fujitsu Ltd | 半導体装置の製造方法 |
US4375124A (en) * | 1981-11-12 | 1983-03-01 | Gte Laboratories Incorporated | Power static induction transistor fabrication |
JPS58168233A (ja) * | 1982-03-30 | 1983-10-04 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS58220445A (ja) * | 1982-06-16 | 1983-12-22 | Toshiba Corp | 半導体集積回路の製造方法 |
US4473598A (en) * | 1982-06-30 | 1984-09-25 | International Business Machines Corporation | Method of filling trenches with silicon and structures |
JPS5982761A (ja) * | 1982-11-04 | 1984-05-12 | Hitachi Ltd | 半導体メモリ |
JPS59119848A (ja) * | 1982-12-27 | 1984-07-11 | Fujitsu Ltd | 半導体装置の製造方法 |
JPS59208750A (ja) * | 1983-05-12 | 1984-11-27 | Sanyo Electric Co Ltd | 半導体装置の配線構造 |
US4522662A (en) * | 1983-08-12 | 1985-06-11 | Hewlett-Packard Company | CVD lateral epitaxial growth of silicon over insulators |
US4661202A (en) * | 1984-02-14 | 1987-04-28 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
US4526631A (en) * | 1984-06-25 | 1985-07-02 | International Business Machines Corporation | Method for forming a void free isolation pattern utilizing etch and refill techniques |
US4554728A (en) * | 1984-06-27 | 1985-11-26 | International Business Machines Corporation | Simplified planarization process for polysilicon filled trenches |
US4688063A (en) * | 1984-06-29 | 1987-08-18 | International Business Machines Corporation | Dynamic ram cell with MOS trench capacitor in CMOS |
US4801989A (en) * | 1986-02-20 | 1989-01-31 | Fujitsu Limited | Dynamic random access memory having trench capacitor with polysilicon lined lower electrode |
DE3780840T2 (de) * | 1986-03-03 | 1993-03-25 | Fujitsu Ltd | Einen rillenkondensator enthaltender dynamischer speicher mit wahlfreiem zugriff. |
-
1985
- 1985-10-31 US US06/793,518 patent/US4745081A/en not_active Expired - Fee Related
-
1986
- 1986-08-20 JP JP61193004A patent/JPS62105445A/ja active Granted
- 1986-10-10 EP EP86114064A patent/EP0221394B1/de not_active Expired
- 1986-10-10 DE DE8686114064T patent/DE3686125T2/de not_active Expired - Fee Related
-
1988
- 1988-01-20 US US07/145,863 patent/US4924284A/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
DE3686125T2 (de) | 1993-03-11 |
US4924284A (en) | 1990-05-08 |
EP0221394B1 (de) | 1992-07-22 |
EP0221394A2 (de) | 1987-05-13 |
US4745081A (en) | 1988-05-17 |
JPS62105445A (ja) | 1987-05-15 |
JPH0344419B2 (de) | 1991-07-05 |
EP0221394A3 (en) | 1989-04-26 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
8364 | No opposition during term of opposition | ||
8339 | Ceased/non-payment of the annual fee |