DE3483809D1 - Verfahren zur herstellung einer dielektrisch isolierten integrierten schaltung. - Google Patents

Verfahren zur herstellung einer dielektrisch isolierten integrierten schaltung.

Info

Publication number
DE3483809D1
DE3483809D1 DE8484402044T DE3483809T DE3483809D1 DE 3483809 D1 DE3483809 D1 DE 3483809D1 DE 8484402044 T DE8484402044 T DE 8484402044T DE 3483809 T DE3483809 T DE 3483809T DE 3483809 D1 DE3483809 D1 DE 3483809D1
Authority
DE
Germany
Prior art keywords
producing
integrated circuit
dielectrically isolated
isolated integrated
dielectrically
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE8484402044T
Other languages
English (en)
Inventor
Satoru Tani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of DE3483809D1 publication Critical patent/DE3483809D1/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/74—Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
    • H01L21/743—Making of internal connections, substrate contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/038—Diffusions-staged
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/135—Removal of substrate
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/973—Substrate orientation
DE8484402044T 1983-10-12 1984-10-11 Verfahren zur herstellung einer dielektrisch isolierten integrierten schaltung. Expired - Fee Related DE3483809D1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58191181A JPS6081839A (ja) 1983-10-12 1983-10-12 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
DE3483809D1 true DE3483809D1 (de) 1991-02-07

Family

ID=16270245

Family Applications (1)

Application Number Title Priority Date Filing Date
DE8484402044T Expired - Fee Related DE3483809D1 (de) 1983-10-12 1984-10-11 Verfahren zur herstellung einer dielektrisch isolierten integrierten schaltung.

Country Status (6)

Country Link
US (1) US4624047A (de)
EP (1) EP0139587B1 (de)
JP (1) JPS6081839A (de)
KR (1) KR890003382B1 (de)
CA (1) CA1219379A (de)
DE (1) DE3483809D1 (de)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4923820A (en) * 1985-09-18 1990-05-08 Harris Corporation IC which eliminates support bias influence on dielectrically isolated components
US4807012A (en) * 1985-09-18 1989-02-21 Harris Corporation IC which eliminates support bias influence on dielectrically isolated components
US4870029A (en) * 1987-10-09 1989-09-26 American Telephone And Telegraph Company, At&T-Technologies, Inc. Method of forming complementary device structures in partially processed dielectrically isolated wafers
US4794092A (en) * 1987-11-18 1988-12-27 Grumman Aerospace Corporation Single wafer moated process
JPH01179342A (ja) * 1988-01-05 1989-07-17 Toshiba Corp 複合半導体結晶体
US4820653A (en) * 1988-02-12 1989-04-11 American Telephone And Telegraph Company Technique for fabricating complementary dielectrically isolated wafer
JPH02208952A (ja) * 1989-02-08 1990-08-20 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5272095A (en) * 1992-03-18 1993-12-21 Research Triangle Institute Method of manufacturing heterojunction transistors with self-aligned metal contacts
US5318916A (en) * 1992-07-31 1994-06-07 Research Triangle Institute Symmetric self-aligned processing
US5436173A (en) * 1993-01-04 1995-07-25 Texas Instruments Incorporated Method for forming a semiconductor on insulator device
US5914517A (en) * 1996-07-16 1999-06-22 Nippon Steel Corporation Trench-isolation type semiconductor device
US6040597A (en) * 1998-02-13 2000-03-21 Advanced Micro Devices, Inc. Isolation boundaries in flash memory cores
JP2002083876A (ja) * 2000-09-07 2002-03-22 Sanyo Electric Co Ltd 半導体集積回路装置の製造方法
TW512526B (en) * 2000-09-07 2002-12-01 Sanyo Electric Co Semiconductor integrated circuit device and manufacturing method thereof
KR20070069951A (ko) * 2005-12-28 2007-07-03 동부일렉트로닉스 주식회사 고전압용 바이씨모스소자의 제조방법

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3412295A (en) * 1965-10-19 1968-11-19 Sprague Electric Co Monolithic structure with three-region complementary transistors
US3412296A (en) * 1965-10-19 1968-11-19 Sprague Electric Co Monolithic structure with threeregion or field effect complementary transistors
US3509433A (en) * 1967-05-01 1970-04-28 Fairchild Camera Instr Co Contacts for buried layer in a dielectrically isolated semiconductor pocket
US3818583A (en) * 1970-07-08 1974-06-25 Signetics Corp Method for fabricating semiconductor structure having complementary devices
US3755012A (en) * 1971-03-19 1973-08-28 Motorola Inc Controlled anisotropic etching process for fabricating dielectrically isolated field effect transistor
US3798753A (en) * 1971-11-12 1974-03-26 Signetics Corp Method for making bulk resistor and integrated circuit using the same
JPS5120267B2 (de) * 1972-05-13 1976-06-23
US3876480A (en) * 1972-08-28 1975-04-08 Motorola Inc Method of manufacturing high speed, isolated integrated circuit
US3954522A (en) * 1973-06-28 1976-05-04 Motorola, Inc. Integrated circuit process
GB2060252B (en) * 1979-09-17 1984-02-22 Nippon Telegraph & Telephone Mutually isolated complementary semiconductor elements
US4255209A (en) * 1979-12-21 1981-03-10 Harris Corporation Process of fabricating an improved I2 L integrated circuit utilizing diffusion and epitaxial deposition
US4290831A (en) * 1980-04-18 1981-09-22 Harris Corporation Method of fabricating surface contacts for buried layer into dielectric isolated islands
US4408386A (en) * 1980-12-12 1983-10-11 Oki Electric Industry Co., Ltd. Method of manufacturing semiconductor integrated circuit devices
US4481707A (en) * 1983-02-24 1984-11-13 The United States Of America As Represented By The Secretary Of The Air Force Method for the fabrication of dielectric isolated junction field effect transistor and PNP transistor
JPS6074635A (ja) * 1983-09-30 1985-04-26 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
KR850003067A (ko) 1985-05-28
JPS6081839A (ja) 1985-05-09
EP0139587A2 (de) 1985-05-02
US4624047A (en) 1986-11-25
EP0139587A3 (en) 1987-11-25
JPS6362897B2 (de) 1988-12-05
KR890003382B1 (ko) 1989-09-19
EP0139587B1 (de) 1991-01-02
CA1219379A (en) 1987-03-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee